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Pins of I/O Port

The 8051 microcontroller has four 8-bit I/O ports named P0, P1, P2, and P3. Each port can be configured as an input or output. P1, P2, and P3 have internal pull-up resistors, while P0 is open-drain and does not have internal pull-ups. The document describes how to write 1s and 0s to output pins and read from input pins by manipulating the latch associated with each pin.

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143 views10 pages

Pins of I/O Port

The 8051 microcontroller has four 8-bit I/O ports named P0, P1, P2, and P3. Each port can be configured as an input or output. P1, P2, and P3 have internal pull-up resistors, while P0 is open-drain and does not have internal pull-ups. The document describes how to write 1s and 0s to output pins and read from input pins by manipulating the latch associated with each pin.

Uploaded by

api-19970915
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Pins of I/O Port

 The 8051 has four I/O ports


– Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）
– Port 1 （ pins 1-8 ） ： P1 （ P1.0 ～ P1.7 ）
– Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）
– Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）
– Each port has 8 pins.
 Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X
 Ex ： P0.0 is the bit 0 （ LSB ） of P0
 Ex ： P0.7 is the bit 7 （ MSB ） of P0
 These 8 bits form a byte.
 Each port can be used as input or output (bi-direction).

A Pin of Port 1

Read latch Vcc


TB2
Load(L1)

Internal CPU D Q P1.X


bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin P0.x
8051 IC
Writing “1” to Output Pin P1.X

Read latch Vcc


TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
Internal CPU D Q 1 P1.X
bus P1.X pin
0 M1
output 1
Write to latch Clk Q

TB1
Read pin

8051 IC
Writing “0” to Output Pin P1.X

Read latch Vcc


TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
Internal CPU D Q 0 P1.X
bus P1.X pin
1 M1
output 0
Write to latch Clk Q

TB1
Read pin

8051 IC
Reading “High” at Input Pin

Read latch Vcc 2. MOV A,P1


TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
Reading “Low” at Input Pin

Read latch Vcc 2. MOV A,P1


TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
Other Pins
 P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
 P0 has no internal pull-up resistors and does not
connects to Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X. 
 However, for a programmer, it is the same to program
P0, P1, P2 and P3.
 All the ports upon RESET are configured as output.
A Pin of Port 0

Read latch
TB2

Internal CPU D Q P0.X


bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin P1.x

8051 IC
Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0
DS5000 P0.1

Port 0
P0.2
8751 P0.3
8951 P0.4
P0.5
P0.6
P0.7
RESET Value of Some 8051 Registers:

Register Reset Value


PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.

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