Field-Effect Transistors (FETs)

Van Su Luong

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Contents
1. The JFET
2. JFET Characteristics and Parameters
3. JFET Biasing
4. The Ohmic Region
5. The MOSFET
6. MOSFET Characteristics and Parameters
7. MOSFET Biasing

8. The Common-Source Amplifier

9. The Common-Drain Amplifier
10. The Common-Gate Amplifier
11. The Class D Amplifier
12. MOSFET Analog Switching
13. MOSFET Digital Switching

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The FET

The idea for a field-effect transistor (FET) was first proposed by

Julius Lilienthal, a physicist and inventor. In 1930 he was granted
a U.S. patent for the device.
His ideas were later refined
and developed into the FET.
Materials were not available
at the time to build his
device. A practical FET was
not constructed until the
1950’s. Today FETs are the
most widely used
components in integrated
circuits.

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The JFET

The JFET (or Junction Field Effect Transistor) is a normally ON

device. For the n-channel device illustrated, when the drain is
positive with respect to the source and there is no gate-source
voltage, there is current in the channel.
RD

When a negative gate voltage is D

applied to the FET, the electric field n

causes the channel to narrow, which in G

+
p p VDD
–
turn causes current to decrease. VGG
– n

+ S

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The JFET

As in the base of bipolar transistors, there are two types of JFETs: n-

channel and p-channel. The dc voltages are opposite polarities for
each type.
RD
The symbol for an n-channel JFET is
shown, along with the proper
polarities of the applied dc Drain +
voltages. For an n-channel device, Gate VDD
the gate is always operated with a – Source
–
negative (or zero) voltage with VGG
respect to the source. +

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The JFET

There are three regions in the characteristic curve for a JFET as

illustrated for the case when VGS = 0 V.
Between A and B is the Ohmic region, ID

where current and voltage are related Ohmic region

by Ohm’s law. IDSS

B VGS = 0 C

From B to C is the active (or constant-

current) region where current is
essentially independent of VDS.

Beyond C is the breakdown region. Active region Breakdown

Operation here can damage the FET. 0
A (constant current)
VP (pinch-off voltage)
VDS

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The JFET

When VGS is set to different values, the relationship between

VDS and ID develops a family of characteristic curves for the
device.
An n-channel
ID

characteristic is
IDSS VGS = 0

illustrated here. VGS = –1 V

Notice that Vp is
positive and has the VGS = –2 V

same magnitude as VGS = –3 V

VGS(off). VGS = – 4 V
VGS = VGS(of f) = –5 V
VDS
VP = +5 V

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Ex#1

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Ex#2

A particular p-channel JFET has a VGS(off) = +4 V.

What is ID when V GS = +6 V?

The p-channel JFET requires a positive gate-to-source

voltage. The more positive the voltage, the less the
drain current. When VGS = 4 V, ID = 0. Any further
increase in VGS keeps the JFET cut off, so ID remains 0.

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The JFET

A plot of VGS to ID is called the transfer or transconductance

curve. The transfer curve is a is a plot of the output current
(ID) to the input voltage (VGS).
The transfer curve is based
ID

on the equation IDSS

2
 VGS 
I D = I DSS 1 − 
 V
 GS(off)  IDSS
2

By substitution, you can find IDSS

4

other points on the curve for –VGS

plotting the universal curve. VGS(off) 0.3 VGS(off) 0
0.5 VGS(off) Note

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The JFET

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The JFET

A certain 2N5458 JFET has IDSS = 6.0 mA and VGS(off) = – 3.5 V.

(a) Show the values of these end

points on the transfer curve. ID

IDSS = 6.0 mA
(b) Show the point for the case
when ID = 3.0 mA.

3.0 mA

(b) When ID = IDSS/2, VGS = 0.3VGS(off).

Therefore, VGS = -1.05 V –VGS
VGS(off) = -3.5 V -1.05 V 0

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2N5458 JFET

mho =
siemens

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Ex#3

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The JFET

The transconductance is the ratio of a change in output

current (ID) to a change in the input voltage (VGS).
I D
This definition is gm =
VGS
The following approximate
ID

formula is useful for calculating

IDSS

gm if you know gm0.

 V 
g m = g m0 1 − GS 
 V  ID
 GS(off) 

When a value of gm0 is not available in datasheet VGS

The value of gm0 can be found from –VGS

VGS(off) 0
2 I DSS
gm0 =
VGS(off)

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The JFET

Because the slope changes at every point along the curve,

the transconductance is not constant, but depends on where
it is measured.
I D (mA)

What is the transconductance for 10 mA

the JFET at the point shown? 8.0

6.0 5.7

4.0 3.7
I D 5.7 mA − 3.7 mA
gm = = 2.0
VGS −0.7 V − (−1.3 V)
2.0 mA –VGS
= = 3.33 mS −4 −3 −2 −1 0
0.6 V −1.3 −0.7

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JFET Input Resistance
VGS
The input resistance of a JFET is given by: RIN =
I GSS
where IGSS is the current into the reverse biased gate.
JFETs have very high input resistance, but it drops when the temperature
increases.

Compare the input resistance of a 2N5485 at 25 oC and at 100 oC. The

specification sheet shows that for VGS = -20 V, IGSS – 1 nA at 25 oC and 0.2
mA at 100 oC.
VGS 20 V
At 25 oC, RIN = = = 20 GΩ!
I GSS 1 nA
VGS 20 V
At 100 oC, RIN = = = 100 MΩ
I GSS 0.2 μA

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JFET Biasing

Self-bias is simple and effective, so it is the most common

biasing method for JFETs. With self bias, the gate is essentially
at 0 V.
An n-channel JFET is illustrated. The current in RS +VDD = +12 V
develops the necessary reverse bias that forces
the gate to be less than the source.
RD
1.5 kW

Assume the resistors are as shown and the drain VG = 0 V

current is 3.0 mA. What is VGS?

+ IS
RG RS 330 W
1.0 MW –

VG = 0 V; VS = (3.0 mA)(330 W) = 0.99 V

VGS = 0 – 0.99 V = - 0.99 V

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JFET Biasing

You can use the transfer curve to obtain a reasonable value

for the source resistor in a self-biased circuit.

I D (mA)

What value of RS should you use to 10 mA

set the Q point as shown? 8.0

6.0

Q 4.0
The Q point is approximately at ID
= 4.0 mA and VGS = -1.25 V. 2.0

–VGS
V 1.25 V −4 −3 −2 −1 0
RS = GS = = 375 W
ID 3.0 mA

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JFET Biasing

Voltage-divider biasing is a combination of a voltage-divider

and a source resistor to keep the source more positive than
the gate.
VG is set by the voltage-divider and is
+VDD

independent of VS. VS must be larger than RD

VG in order to maintain the gate at a R1 ID
negative voltage with respect to the VG
source.
VS IS
Voltage-divider bias helps stabilize the R2 RS
bias for variations between transistors.

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JFET Biasing

A graphical analysis of voltage-divider biasing is illustrated. A

typical transconductance curve for the 2N5485 is shown with IDSS
= 6.5 mA and VGS(off) = -2.2 V.
+VDD
Start with VG: +12 V
ID (mA) The Q-point is
VG = 2.79 V
read from the
VG/RS = 2.79 mA 8.0
plot. It is 3.3 R1 RD
3.3 MW 820 W
Connect 6.0 mA and -0.7 V.
the points to 2.79 V 2N5485
Q
establish the
4.0

load line. 2.0 R2 RS

1.0 MW 1.0 kW
–VGS VGS
−3 −2 −1 0 +1 +2 +3

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JFET Ohmic Region

As described before, the ohmic region is between the origin and

the active region. A JFET operated in this region can act as a
variable resistor.

Data from an actual FET is

7
Ohmic
shown. The slopes (which
6 VG = 0 V
region

represent conductance) of
5
VG = − 0.5 V
ID 4
successive VGS lines are (mA)
VG = −1.0 V

different in the ohmic region.

3
VG = −1.5 V
This difference is exploited for
2

use as a voltage controlled

1

resistance.
0
0 1 2 3 4 5 6 7 8
VDS (V)

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JFET Ohmic Region

Here is a circuit in which the JFET is used as a variable resistor.

Notice that that the drain is connected through a capacitor,
which means the JFET’s Q-point is at the origin.

The gain of the VCC

+15 V
BJT depends on
the dc voltage
RC
R1 3.9 kW Vout
56 kW
setting of VGG.
C1
Q1
2N3904 C2
1.0 µF
Vs = R2 10 µF R3
400 mV pp 39 kW RE Q2
100 k W −VGG
1.0 kHz 6.2 kW 2N5458

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The MOSFET

The metal oxide semiconductor FET uses an insulated gate to

isolate the gate from the channel. Two types are the
enhancement mode (E-MOSFET) and the depletion mode (D-
MOSFET).
An E-MOSFET has no channel E-MOSFET RD
Drain

until it is induced by a voltage

ID

applied to the gate, so it SiO2

n
Induced
channel n

operates only in enhancement +

+
–
– +

mode. An n-channel type is

Gate p substrate VDD
+ –
–
+ –

illustrated here; a positive gate n

VGG
+
–
n

voltage induces the channel.

Source

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The MOSFET

The D-MOSFET has a channel that can is controlled by the gate

voltage. For an n-channel type, a negative voltage depletes
the channel; and a positive voltage enhances the channel.

A D-MOSFET can RD
D-MOSFET RD

operate in either
mode, depending n n

on the gate
– + + –
– + + –
– + + + – +

voltage.
– +
p VDD + – p VDD
– –
– + + –
– + + –
– +
VGG n VGG n
+ –

operating in D-mode operating in E-mode

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The MOSFET

MOSFET symbols are shown. Notice the broken line representing the
E-MOSFET that has an induced channel. The n channel has an
inward pointing arrow.

E-MOSFETs D-MOSFETs
D D D D

G G G G

S S S S
n channel p channel n channel p channel

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The MOSFET

The transfer curve for a MOSFET is has the same parabolic

shape as the JFET but the position is shifted along the x-axis.
The transfer curve for an n-channel E-MOSFET is entirely in the
first quadrant as shown.
The curve starts at VGS(th), which is ID

a nonzero voltage that is required

to have channel conduction. The
equation for the drain current is
I D = K (VGS − VGS(th) )
2

0 VGS(th) +VGS

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The MOSFET

Recall that the D-MOSFET can be operated in either mode. For

the n-channel device illustrated, operation to the left of the y-
axis means it is in depletion mode; operation to the right means
is in enhancement mode.
As with the JFET, ID is zero at VGS(off).
When VGS is 0, the drain current is IDSS,
ID

which for this device is not the

maximum current. The equation for
drain current is I DSS
2
 VGS 
I D  I DSS 1 − 
 V
 GS(off) 
–VGS
VGS(off) 0

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MOSFET Biasing

E-MOSFETs can be biased using bias methods like the BJT methods
studied earlier. Voltage-divider bias and drain-feedback bias are
illustrated for n-channel devices.
+V DD +VDD

RD RD
R1 RG

R2

Voltage-divider bias Drain-feedback bias

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MOSFET Biasing

The simplest way to bias a D-MOSFET is with zero bias. This works
because the device can operate in either depletion or
enhancement mode, so the gate can go above or below 0 V.

+VDD +VDD

RD RD

C
VG = 0 V IDSS ac
input
VGS = 0
RG RG

Zero bias, which can only be used for the D-MOSFET

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FET Amplifiers and Switching
Circuits

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The Common-Source Amplifier

+VDD

In a CS amplifier, the input signal is

applied to the gate and the output RD
C3
signal is taken from the drain. The
Vout
C1
amplifier has higher input resistance
and lower gain than the equivalent RL
CE amplifier. Vin RG RS C2

The voltage gain is given by the equation Av = gmRd.

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The Common-Source Amplifier

/rɪˈsɪprəkl/ synonym as Inverse proportional

Recall that conductance is the reciprocal of resistance and
admittance is the reciprocal of impedance. Data sheets typically
specify the forward transfer admittance, yfs rather than
transconductance, gm. The definition of yfs is
I D
y fs =
VG

DYNAMIC CHARACTERISTICS Symbol Min Typ Max Unit

Forward Transfer Admittance 2N5457 |Yfs| 1000 3000 5000 m mhos
(VDS = 15 Vdc, VGS = 0) 2N5458 1500 4000 5500

An alternate gain expression for a CS amplifier is Av = yfsRd.

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The Common-Source Amplifier

You can estimate what the transfer characteristic

ID (mA)

looks like from values on the specification sheet, but

keep in mind that large variations are common 9

with JFETs. For example, the range of specified

values for a 2N5458 is shown.
So, if you have a selection of JFET and you random
pick one out, it can have values anywhere within 2
these ranges
– VGS (V)
–7 –1 0

OFF CHARACTERISTICS Symbol Min Typ Max Unit

Gate-Source Cutoff Voltage 2N5457 V GS(off) -0.5 - -6.0 Vdc
(VDS = 15 Vdc, iD = 10 nAdc) 2N5458 -1.0 - -7.0

ON CHARACTERISTICS Symbol Min Typ Max Unit

Zero Gate-Source Drain Current 2N5457 I DSS 1.0 3.0 5.0 mAdc
(VDS = 15 Vdc, VGS = 0) 2N5458 2.0 6.0 9.0

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The Common-Source Amplifier

To analyze the CS amplifier. you need to start with dc values. It is useful to

estimate ID based on typical values; specific circuits will vary from this
estimate.

VDD
+12 V

For a typical 2N5458, what is the RD

drain current? 2.7 kW

C1 Vout

2N5458
From the specification sheet, the 0.1 mF
typical IDSS = 6.0 mA and VGS(off) = -4 Vin
RG RS
V. These values can be plotted
100 mV C2
10 MW 470 W 10 mF
along with the load line to obtain a
graphical solution.
See the following slide…

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The Common-Source Amplifier
(continued)

A graphical solution is illustrated. On

the transconductance curve, plot Load line for 470 W resistor
the load line for the source resistor. ID (mA)

First, calculate VGS when ID is zero.

VGS = -IDRS = (0)(470 Ω) = 0 V
This establishes a point at the origin on the graph (ID = 0, 6
VGS = 0). Next, calculate VGS when ID = IDSS. From the curve
in Figure, IDSS = 6mA.
VGS = -IDRS = -(6 mA)(470 Ω) = -2.82 V Q 2.8 mA
This establishes a second point on the graph (ID = 6 mA,
VGS = -2.82 V)
– VGS (V)
Then read the current and ID = 2.8 mA and –4
-1.3 V
0
voltage at the Q-point. VGS = -1.3 V

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The Common-Source Amplifier

(continued)
2
 I D RS 
Alternatively, you can obtain ID using Equation : I D = I DSS 1 −
 V 
 GS(off) 

The solution to this quadratic equation is simplified using a calculator that can
handle quadratic equations. (you can use C, C#, VB, Matlab, Python, Labview
to program this equation)
ID=IDSS (1–(–ID RS/VG...
After entering the equation, enter ID= .0027494671581759
the known values, but leave ID open. IDSS= .006
For the typical values for the 2N5458, RS= 470 enter absolute
VGSOFF= 4.0
(IDSS = 6 mA and VGS(off) = -4 V) with a bound=(–1E 99,1E 99)
value

source resistance of 470 W, we find

2.75 mA. GRAPH RANGE ZOOM TRACE SOLVE

press F5

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Ex#1
Determine the Q-point for the JFET circuit in Figure (a)
The transfer characteristic curve is given in Figure (b)

For ID = 0,
VGS = -IDRS = (0)(680 V) = 0 V
4
This gives a point at the origin.
From the curve, IDSS = 4 mA; so ID = IDSS = 4
mA
VGS = -IDRS = -(4 mA)(680 V) = -2.72 V
This gives a second point at 4 mA and -
2.72 V

-6

(a) (b)

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The Common-Source Amplifier

Assume IDSS is 6.0 mA, VGS(off) is -4 V, and VGS = -1.3 V as found

previously. What is the expected gain?

VDD Output is inverted

+12 V (or phase = 180)
2 I DSS 2 ( 6.0 mA )
gm0 = = = 3.0 mS RD
VGS(off) 4 V 2.7 kW
Vout
 V 
C1
g m = g m 0 1 − GS  2N5458
 V 
 GS(off)  0.1 mF

 −1.3 V 
Vin
= 3.0 mS 1 − 100 mV RG RS C2
 470 W 10 mF
 −4.0 V 
10 MW

2.02 mS

Av = gmRd = (2.02 mS)(2.7 kW) = 5.454

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The Common-Source Amplifier

The gain is reduced when a load is connected to the amplifier because

the total ac drain resistance (Rd) is reduced.

How does the addition of the

VDD
+12 V
10 kW load affect the gain?
RD
2.7 kW
Vout
C1
2N5458
R R
Rd = D L 0.1 mF
RD + RL Vin

( 2.7 kW )(10 kW ) 100 mV RG RS C2 RL

10 MW 470 W 10 mF 10 kW
=
2.7 kW + 10 kW
= 2.13 kW

Av = gmRd = (2.02 mS)(2.13 kW) = 4.29

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 Ex#2
What is the total output voltage for the unloaded amplifier in Figure? IDSS is 4.3 mA; VGS(off) is -2.7 V.

We can use a graphical approach, if we

use the mathematical approach, Note
VGS = - IDRS

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Ex#3

If a 4.7 kΩ load resistor is ac coupled to the output of the amplifier in Example #2,
what is the resulting rms output voltage?

NOTE: The unloaded ac output voltage was 700 mV in Example #2

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Input Resistance

What input resistance is seen by the signal source in Figure below? IGSS = 30
nA at VGS = 10 V.

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The D-MOSFET

In operation, the D-MOSFET has the unique property in that it can be

operated with zero bias, allowing the signal to swing above and below
ground. This means that it can operate in either D-mode or E-mode.

ID

ent
em
nc
ha
+VDD

En
Q
RD C2
Vout
n Id
tio
C1 le
ep
D

RL –VGS 0 +VGS
Vin RG
Vgs

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The E-MOSFET

The E-MOSFET is a normally off device. The n-channel device is biased

on by making the gate positive with respect to the source. A voltage-
divider biased E-MOSFET amplifier is shown.

ID

Enhancement

+VDD

Q
RD IDQ
C3
R1 Vout
C1 Id

RL VGS
0 VGS(th)
Vin C2
R2 RS
Vgs

VGSQ

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The E-MOSFET

The E-MOSFET amplifier in

previous slide is illustrated in
Multisim using a 2N7000 MOSFET.

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The Common-Drain Amplifier

+VDD

In a CD amplifier, the input signal

is applied to the gate and the
C1
Vin C2

output signal is taken from the

Vout

source. There is no drain resistor,

RG RS RL

because it is common to the

input and output signals.

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The Common-Drain Amplifier
As in all amplifiers, the voltage gain is
Av = Vout/Vin. For the source-follower,
Vout is IdRs and Vin is Vgs + IdRs,
Therefore, the gate-to-source voltage gain
Av is IdRs /(Vgs + IdRs).
Substituting Id = gmVgs into the expression
gives the following result gV R
Av = m gs s

Vgs + g mVgs Rs Input Resistance

g m Rs
The voltage gain is given by the equation Av = Rin = RG / / RIN ( gate )
1 + g m Rs
The voltage gain is always < 1, but the power gain is not.

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The Common-Gate Amplifier

The voltage gain from source to drain is developed as follows:

Vout Vd I d Rd g mVgs Rd
Av = = = = = g m Rd
Vin Vgs Vgs Vgs

The voltage gain is given by the equation Av = g m Rd

Where Rd = RD //RL
I in = I s = I d = g mVgs
Input Resistance As you have seen, both
the common-source and common-drain Secon, the input voltage equals Vgs
configurations have extremely high input Vin = Vgs
resistances because the gate is the input
terminal. In contrast, the common-gate Therefore, the input resistance at the
configuration where the source is the input source terminal is
terminal has a low input resistance. This is Vin V 1
shown as follows. First, the input current is Rin ( source ) = = gs Rin ( source ) =
equal to the drain current.
I in g mVgs gm

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 EX#4
Determine the minimum voltage gain and input resistance of the amplifier. VDD is negative because it is
a p-channel device

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The Cascode Amplifier
The cascode connection is a
combination of CS and CG
amplifiers. This forms a good
high-frequency amplifier. The
input and output signals at 10
MHz are shown for this circuit
on the following slide…

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The Cascode Amplifier

The input signal for the

cascode amplifier is
shown in red; the output is
blue. What is the gain?

The peak of the input is

24.7 mV.
The peak of the output
is 2.33 V.
AV = 94.3

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The Class-D Amplifier

MOSFETs are useful as class-D amplifiers, which are very efficient

because they operate as switching amplifiers. They use pulse
width modulation, a process in which the input signal is
converted to a series of pulses. The pulse width varies
proportionally to the amplitude of the input signal.

Pulse-width modulation is easy to set up in Multisim. The following

slide shows the circuit. A sine wave is compared to a faster
triangle wave of the about the same amplitude using a
comparator (a 741 op-amp can be used at low frequencies).

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 The Class-D Amplifier

A circuit that you can

use in lab or in Multisim
to observe pulse width Op-amp set up
as a comparator
modulation in action.
The scope display is
shown on the following
slide…

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The Class-D Amplifier

The signal is the yellow sine wave and is compared repeatedly to the
triangle (cyan). The result of the comparison is the output (magenta).
/ˈsaɪæn/ /məˈdʒentə/
a blue-green colour between red and purple in colour

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 The Class-D Amplifier

The modulated signal is amplified by

class-B complementary MOSFET +VDD
transistors. The output is filtered by a low-
pass filter to recover the original signal
and remove the higher modulation Q1

frequency. Modulated
input Low-pass
PWM is also useful in control applications filter

such as motor controllers. MOSFETs are RL

widely used in these applications Q2
because of fast switching time and low
on-state resistance. –VDD

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The Analog Switch

MOSFETs are also used as analog switches to connect or disconnect

an analog signal. Analog switches are available in IC form – for
example the CD4066 is a quad analog switch that used parallel n-
and p-channel MOSFETs. The configuration shown allows signals to
be passed in either direction.
Advantages of MOSFETs are IN/OUT OUT/IN
that they have relatively low
on-state resistance and they
can be used at high
frequencies, such as found in
Control

video applications.
Simplified internal construction of a
When control signal is on, the in/output bidirectional IC analog switch.
signals is like the out/input signals.
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Quiz

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