1

XILINX
ISE PROJECT NAVIGATOR

2
STEP 1:Select new project to create a new project

STEP 2: Give project name and click next

Step 3: Give the following device specifications and click next

FAMILY :

SPARTAN 3A DSP

DEVICE :

XC3SD1800A

PACKAGE:

FG676

STEP 4: CLICK FINISH WHICH OPENS PROJECT WINDOW IN WHICH CLICK PROJECT>NEW
SOURCE

GIVE MODULE NAME. CHOOSE VERILOG MODULE AND CLICK NEXT

4
STEP 5:GIVE INPUT AND OUTPUT PINS AND THEN CLICK NEXT

STEP 6:TYPE YOUR CODE, SYNTHESIZE AND SIMULATE

EDK

6
STEP 1: AFTER SYNTHESIZING THE VERILOG CODE CLICK PROJECT>NEW SOURCE
CHOOSE EMBEDDED PROCESSOR AND GIVE FILE NAME

IT OPENS BASE SYSTEM BUILDER

STEP 2: SELECT I WOULD LIKE TO CREATE NEW DESIGN OPTION AND CLICK NEXT

7
STEP 3: SELECT SINGLE PROCESSOR SYSTEM AND CHOOSE 16 KB LOCAL MEMORY

STEP 4: GENERATE PROGRAMMING FILE IN ISE PROJECT NAVIGATOR AND UPDATE THE
BITSTREAM TO PROCESSOR

PLANAHEAD

9
STEP 1: SELECT CREATE NEW PROJECT AND CLICK NEXT, GIVE PROJECT NAME THEN
CLICK NEXT

STEP 2: SELECT SPECIFY RTL SOURCES AND CLICK NEXT

10
STEP 3: CLICK CREATE FILE, GIVE FILE NAME AND THEN CLICK NEXT

STEP 4: CHOOSE DEVICE PACKAGE DETAILS AND CLICK NEXT THEN FINISH

11
STEP 5: TYPE THE VERILOG CODE IN PROJECT MANAGER THEN SYNTHESIZE

STEP 6: CLICK OK TO IMPLEMEENT THE DESIGN

12
STEP 7: PLACE THE SCALAR PORTS SHOWN IN STEP 6 IN THE I/O PLANNER
DRAW P+MODULE IN DESIGN PLANNER

STEP 8: DRAG ALL THE INSTANCES AND PLACE IT IN P BLOCK

13
STEP 9: CLICK RUN DRC TO CHECK THE DESIGN

STEP 10: RUN NOISE ANALYSIS. VARY THE WASSO ANALYSIS PARAMETERS AND FIND
DIFFERENT WASSO ALLOWANCE AND UTILIZATION

14
STEP 11: CLICK REPORT TIMING>OK VIEW THE LOGICAL DELAY AND TOTAL DELAY IN
THE DESIGN

STEP 12: CLICK LAUNCH POWER ANALYSIS

15
STEP 13: ADDING IP CATALOG

CLICK IP CATALOG ON SIDEBAR AND SEARCH YOUR REQUIRED IP.

CUSTOMIZE THE REQUIRED IP BY DOUBLE CLICKING IT.

GIVE THE NEEDED INSTRUCTIONS AND CLICK GENERATE.

OPEN THE .VEO FILE GENERATED. NOW COPY THE CODE GIVEN
BELOW Begin Cut here for INSTANTIATION Template AND PASTE IT IN
THE VERILOG CODE IN WHICH YOU ARE USING THE IP AND GIVE ANY
CONVENIENT INSTANCE NAME

16

AFTER ADDING IP TO THE TOP MODULE LIKE A CALLING FUNCTION, DO

SYNTHESIZE AND IMPLEMENTATION AS BY THE ABOVE MENTIONED
STEPS.

17
EX NO: 1

PRIORITY ENCODER

DATE: 17/1/2012

AIM:
To design four bit priority encoder and verifying it by simulation using Xilinx ise project navigator.
PROGRAM:

module priority(d,a);
input [3:0]d;
output [1:0]a;
assign a[1]=d[3]|d[2];
assign a[0]=d[3]|((~d[2])&d[1]);
endmodule

18
SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: priority.ngr
: priority

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:6

Cell Usage :
# BELS

:2

LUT2

:1

LUT3

:1

# IO Buffers
#

IBUF

OBUF

:5
:3
:2

==================================================================
=======

Device utilization summary:

---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:

1 out of 16640

0%

19
Number of 4 input LUTs:
Number of IOs:
Number of bonded IOBs:

2 out of 33280

0%

6
5 out of 519

0%

SIMULATION:

RESULT:
Thus priority encoder is successfully designed and verified by simulation using ISE
project navigator.

20
EX NO 2

CARRY LOOK AHEAD ADDER

DATE: 24/1/2012

AIM:
To design four bit carry look ahead adder and verifying it by simulation using Xilinx ISE Project
navigator.
PROGRAM:

module CLA(sum,cout,a,b,cin);
output [4:1]sum;
output cout;
input [4:1]a,b;
input cin;
wire [4:2]c;
wire [4:1]p;
wire [4:1]g;
assign p[4:1]=a[4:1]^b[4:1];
assign g[4:1]=a[4:1]&b[4:1];
assign c[2]=(g[1]|(p[1]&cin));
assign c[3]=((g[2])|(p[2]&g[1])|(p[1]&p[2]&cin));
assign c[4]=((g[3])|(p[3]&g[2])|(p[2]&p[3]&g[1])|(p[1]&p[2]&p[3]&cin));
assign
cout=((g[4])|(p[4]&g[3])|(p[3]&p[4]&g[2])|(p[2]&p[3]&p[4]&g[1])|(p[1]&p[2]&p[3]&p[4]&
cin));
assign sum[4:2]=p[4:2]^c[4:2];
assign sum[1]=p[1]^cin;
endmodule

21
SYNTHESIZE REPORT:
========================================================================
=
*

Final Report

========================================================================
=
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: CLA.ngr
: CLA

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

: 14

Cell Usage :
# BELS

:8

:8

LUT3

# IO Buffers
#

IBUF

OBUF

: 14
:9
:5

========================================================================
=

Device utilization summary:

---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:
Number of 4 input LUTs:

4 out of 16640

0%

8 out of 33280

0%

22
Number of IOs:
Number of bonded IOBs:

14
14 out of 519

2%

SIMULATION:

RESULT:
Thus carry look ahead adder is successfully designed and verified by simulation using
ISE project navigator.

23
EX NO: 3

BCD ADDER

DATE: 31/1/2012

AIM:
To design four bit bcd adder and verifying it by simulation using Xilinx ise project navigator.
PROGRAM:

module fa(a,b,c,carry,sum);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=(a&b)|(c&(a^b));
endmodule

module bcdadder(input [3:0] a,b,input zero,output [4:0] sum);

wire t,c1,c2,c3,c4,c5,c6,c7,s0,s1,s2,s3,s4;
fa f11(a[0],b[0],zero,c1,s0);
fa f12(a[1],b[1],c1,c2,s1);
fa f13(a[2],b[2],c2,c3,s2);
fa f14(a[3],b[3],c3,s4,s3);
assign t=s4|(s3&(s2|s1));
assign sum[4]=t;
fa f21(s0,zero,zero,c4,sum[0]);
fa f22(s1,t,c4,c5,sum[1]);
fa f23(s2,t,c5,c6,sum[2]);
fa f24(s3,zero,c6,c7,sum[3]);
endmodule

24
SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: bcdadder.ngr
: bcdadder

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

: 14

Cell Usage :
# BELS

: 12

LUT3

:7

LUT4

:5

# IO Buffers
#

IBUF

OBUF

: 14
:9
:5

==================================================================
=======

Device utilization summary:

---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:

7 out of 16640

0%

25
Number of 4 input LUTs:
Number of IOs:
Number of bonded IOBs:

12 out of 33280

0%

14
14 out of 519

2%

SIMULATION:

RESULT:
Thus bcd adder is successfully designed and verified by simulation using ISE project
navigator.

26
EX NO 4A

MOD-8 RING AND JHONSON COUNTER

DATE: 7/2/2012

AIM:
To design mod 8 jhonson and ring counter and verifying it by simulation using Xilinx ise project
navigator.
PROGRAM:

module dff(d,clk,clr,preset,q);
input d,clk,clr,preset;
output reg q;
always@(posedge clk)
begin
if(!clr)
q=0;
else if(!preset)
q=1;
else
q=d;
end
endmodule

module mod8ringcounter(input clk,clr,preset,output [7:0] q);

dff d1(q[7],clk,clr,preset,q[0]);
dff d2(q[0],clk,clr,preset,q[1]);
dff d3(q[1],clk,clr,preset,q[2]);
dff d4(q[2],clk,clr,preset,q[3]);
dff d5(q[3],clk,clr,preset,q[4]);
dff d6(q[4],clk,clr,preset,q[5]);
dff d7(q[5],clk,clr,preset,q[6]);
dff d8(q[6],clk,preset,clr,q[7]);
endmodule

27
SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: mod8ringcounter.ngr
: mod8ringcounter

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

: 11

Cell Usage :
# BELS
#

INV

:2
:2

# FlipFlops/Latches
#

FDRS

:8
:8

# Clock Buffers
#

BUFGP

# IO Buffers
#

IBUF

OBUF

:1
:1
: 10
:2
:8

==================================================================
=======

Device utilization summary:

---------------------------

28
Selected Device : 3sd1800afg676-5

Number of Slices:

4 out of 16640

0%

Number of Slice Flip Flops:

8 out of 33280

0%

Number of 4 input LUTs:

2 out of 33280

0%

11 out of 519

2%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

11

1 out of

24

4%

SIMULATION:

RESULT:
Thus mod 8 ring counter is successfully designed and verified by simulation using
ISE project navigator.

29
EX NO 4B

MOD 8 JHONSON COUNTER

DATE: 7/2/2012

AIM:
To design mod 8 jhonson counter and verifying it by simulation using Xilinx ise project navigator.
PROGRAM:

module dff(q,d,clk,clr);
output q;
reg q;
input d,clk,clr;
always@(posedge clk)
begin
if(clr)
q<=1'b0;
else q<=d;
end
endmodule
module JOHNSON(q,clk,clr);
output [3:0]q;
input clk;
input clr;
dff d1(q[3],~q[0],clk,clr);
dff d2(q[2],q[3],clk,clr);
dff d3(q[1],q[2],clk,clr);
dff d4(q[0],q[1],clk,clr);
endmodule

30
SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: JOHNSON.ngr
: JOHNSON

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:6

Cell Usage :
# BELS
#

INV

:1
:1

# FlipFlops/Latches
#

FDR

:4
:4

# Clock Buffers
#

:1

BUFGP

:1

# IO Buffers

:5

IBUF

OBUF

:1
:4

==================================================================
=======

Device utilization summary:

---------------------------

31
Selected Device : 3sd1800afg676-5

Number of Slices:

2 out of 16640

0%

Number of Slice Flip Flops:

4 out of 33280

0%

Number of 4 input LUTs:

1 out of 33280

0%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

6
6 out of 519
1 out of

24

1%
4%

SIMULATION:

RESULT:
Thus mod 8 jhonson counter is successfully designed and verified by simulation
using ISE project navigator.

32

EX NO: 5

MOD 6 SYNCHRONOUS AND ASYNCHRONOUS COUNTER

DATE: 21/2/2012

AIM:
To design mod 6 synchronous and asynchronous counter and verifying it by simulation using Xilinx ise
project navigator.
PROGRAM:

module jkff(j,k,clk,clear,reset,d,q);
input j,k,clk,d,clear,reset;
output q;
reg q;
always@(negedge clk)
begin
if(clear|reset)
q=0;
else
q=(j&(~d))|((~k)&q);
end
endmodule

module SYNC_AND_ASYNH_COUNTER(clk,clear,q);
input clk,clear;
output [2:0] q;
wire reset,clk1;
jkff jk1(1'b1,1'b1,~clk,clear,reset,q[0],q[0]);
assign clk1=~(q[0]|clear);
jkff jk2(1'b1,1'b1,clk1,clear,reset,q[1],q[1]);
jkff jk3(q[1],1'b1,clk1,clear,reset,q[2],q[2]);
assign reset=q[2]&(~q[1])&q[0];
endmodule

33
SYNTHESIZE REPORT:

==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: SYNC_AND_ASYNH_COUNTER.ngr
: SYNC_AND_ASYNH_COUNTER

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:5

Cell Usage :
# BELS

:6

INV

:3

LUT2

:2

LUT4

:1

# FlipFlops/Latches
#

FDR_1

:3
:3

# Clock Buffers
#

:1

BUFGP

:1

# IO Buffers

:4

IBUF

OBUF

:1
:3

==================================================================
=======

34
Device utilization summary:
---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:

3 out of 16640

0%

Number of Slice Flip Flops:

3 out of 33280

0%

Number of 4 input LUTs:

6 out of 33280

0%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

5
5 out of 519
1 out of

24

0%
4%

SIMULATION:

RESULT:
Thus the mod 6 synchronous and asynchronous counter is successfully designed and
verified by simulation using ISE project navigator.

35

EX NO 6

PARITY CHECKER AND GENERATOR

DATE: 28/2/2012

AIM:
To design parity checker and generator and verifying it by simulation using Xilinx ise project
navigator.

PROGRAM:

module parity(Ce,Co,Pe,Po,b);
output Pe,Po,Ce,Co;
input [3:0]b;
assign Pe=(b[3]^b[2]^b[1]^b[0]);
assign Po=~(Pe);
assign Ce=(b[3]^b[2]^b[1]^b[0]);
assign Co=~(b[3]^b[2]^b[1]^b[0]);
endmodule

36
SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: parity.ngr
: parity

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:8

Cell Usage :
# BELS

:2

:2

LUT4

# IO Buffers
#

IBUF

OBUF

:8
:4
:4

==================================================================
=======

Device utilization summary:

---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:
Number of 4 input LUTs:

1 out of 16640

0%

2 out of 33280

0%

37
Number of IOs:
Number of bonded IOBs:

8
8 out of 519

1%

SIMULATION:

RESULT:
Thus parity checker and generator is successfully designed and verified by simulation
using ISE project navigator.

38
EX NO: 7

BIDIRECTIONAL BUFFER

DATE: 6/3/2012

AIM:
To design bidirectional buffer and verifying it by simulation using Xilinx ise project navigator.
PROGRAM:

module bidirectionalbuffer(bus1,bus2,clear,enable,clk);
inout [3:0] bus1,bus2;
input clk,enable,clear;
reg [3:0] a,b;
always@(posedge clk)
begin
if(clear)
begin
a=4'b0;
b=4'b0;
end
else if(enable)
begin
a=bus1;
b=bus2;
b=~a;
end
else
begin
a=bus1;
b=bus2;
a=~b;
end
end
assign bus1=a;

39
assign bus2=b;
endmodule
SYNTHESIZE REPORT:
========================================================================
=
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: bidirectionalbuffer.ngr
: bidirectionalbuffer

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

: 11

Cell Usage :
# BELS

:8

:8

LUT3

# FlipFlops/Latches
#

FDR

:8
:8

# Clock Buffers
#

BUFGP

# IO Buffers
#

IBUF

OBUF

:1
:1
: 10
:2
:8

==================================================================
=======

Device utilization summary:

40
---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:

4 out of 16640

0%

Number of Slice Flip Flops:

8 out of 33280

0%

Number of 4 input LUTs:

8 out of 33280

0%

11 out of 519

2%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

11

1 out of

24

4%

SIMULATION:

RESULT:
Thus bidirectional buffer is successfully designed and verified by simulation using
ISE project navigator.

41

EX NO: 8

WALLACE MULTIPLIER

DATE: 13/3/2012

AIM:
To design wallace multiplier and verifying it by simulation using Xilinx ise project navigator.
PROGRAM:

module walace(p,a,b,cin);
output [7:0]p;
input [3:0]a,b;
input cin;
wire [3:0]r1,r2,r3,r4;
wire [6:0]r11,r22,r33,r44,r111,r222,r333,r1111,r2222;
wire s1,s2,s3,s4,s5,s6,s7,s8,c1,c2,c3,c4,c5,c6,c7,c8;
assign r1[3:0]=(a[3:0]&({4{b[0]}}));
assign r2[3:0]=(a[3:0]&({4{b[1]}}));
assign r3[3:0]=(a[3:0]&({4{b[2]}}));
assign r4[3:0]=(a[3:0]&({4{b[3]}}));

assign r11[6:0]=r1[3:0];
assign r22[6:0]={r2[3:0],1'b0};
assign r33[6:0]={r3[3:0],2'b0};
assign r44[6:0]={r4[3:0],3'b0};
ha ha1(c1,s1,r11[1],r22[1]);
fa fa1(c2,s2,r11[2],r22[2],r33[3]);
fa fa2(c3,s3,r11[3],r22[3],r33[3]);
ha ha2(c4,s4,r22[4],r33[4]);

assign r111[6:0]={r33[3],s4,s3,s2,s1,r11[0]};

42
assign r222[6:0]={c4,c3,c2,c1,2'b0};
assign r333[6:0]={r44[6:0]};
ha ha3(c5,s5,r111[2],r222[2]);
fa fa3(c6,s6,r111[3],r222[3],r333[3]);
fa fa4(c7,s7,r111[4],r222[4],r333[4]);
fa fa5(c8,s8,r111[5],r222[5],r333[5]);

assign r1111[6:0]={r333[6],s8,s7,s6,s5,s1,r11[0]};
assign r2222[6:0]={c8,c7,c6,c5,3'b0};
CLA1 cla1(p[6:3],p[7],r1111[6:3],r2222[6:3],cin);
assign p[2:0]={s5,s1,r11[0]};
endmodule
module CLA1(sum,cout,a,b,cin);
output [4:1]sum;
output cout;
input [4:1]a,b;
input cin;
wire [4:2]c;
wire [4:1]p;
wire [4:1]g;
assign p[4:1]=a[4:1]^b[4:1];
assign g[4:1]=a[4:1]&b[4:1];
assign c[2]=(g[1]|(p[1]&cin));
assign c[3]=((g[2])|(p[2]&g[1])|(p[1]&p[2]&cin));
assign c[4]=((g[3])|(p[3]&g[2])|(p[2]&p[3]&g[1])|(p[1]&p[2]&p[3]&cin));
assign
cout=((g[4])|(p[4]&g[3])|(p[3]&p[4]&g[2])|(p[2]&p[3]&p[4]&g[1])|(p[1]&p[2]&p[3]&p[4]&
cin));
assign sum[4:2]=p[4:2]^c[4:2];

43
assign sum[1]=p[1]^cin;
endmodule
module fa(cout,sum,a,b,cin);
output cout,sum;
input a,b,cin;
assign sum=(a^b^cin);
assign cout=(((a^b)&cin)|(a&b));
endmodule
module ha(cout,sum,a,b);
output cout,sum;
input a,b;
assign sum=a^b;
assign cout=a&b;
endmodule

SYNTHESIZE REPORT:
========================================================================
=
*

Final Report

========================================================================
=
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format
Optimization Goal
Keep Hierarchy

: walace.ngr
: walace

: NGC
: Speed
: No

44
Design Statistics
# IOs

: 17

Cell Usage :
# BELS

: 31

LUT2

:5

LUT3

:5

LUT4

: 20

MUXF5

:1

# IO Buffers
#

IBUF

OBUF

: 17
:9
:8

========================================================================
=

Device utilization summary:

---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:

17 out of 16640

Number of 4 input LUTs:

Number of IOs:
Number of bonded IOBs:

0%

30 out of 33280

0%

17
17 out of 519

3%

45
SIMULATION:

RESULT:
Thus Wallace multiplier is successfully designed and verified by simulation using
ISE project navigator.

46
EX NO: 9

CARRY SAVE ADDER

DATE: 20/3/2012

AIM:
To design carry save adder and verifying it by simulation using Xilinx ise project navigator.
PROGRAM:

module carry(a,b,c,d,sum,cout);
input [3:0]a,b,c,d;
output [4:0]sum;
output cout;
wire s1,s2,s3,s4,s5,s6,s7,s8,c1,c2,c3,c4,c5,c6,c7,c8,c9;
wire [4:0]e,f;
fa fa1(a[0],b[0],c[0],s1,c1);
fa fa2(a[1],b[1],c[1],s2,c2);
fa fa3(a[2],b[2],c[2],s3,c3);
fa fa4(a[3],b[3],c[3],s4,c4);

fa fa5(d[0],s1,1'b0,s5,c5);
fa fa6(d[1],s2,c1,s6,c6);
fa fa7(d[2],s3,c2,s7,c7);
fa fa8(d[3],s4,c3,s8,c8);
assign e[4:0]={c4,s8,s7,s6,s5};
assign f[4:0]={c8,c7,c6,c5,1'b0};
CLA cla1(sum[3:0],c9,e[3:0],f[3:0],1'b0);
fa fa9(c4,c8,c9,sum[4],cout);
endmodule

module CLA(sum,cout,a,b,cin);
output [4:1]sum;
output cout;
input [4:1]a,b;

47
input cin;
wire [4:2]c;
wire [4:1]p;
wire [4:1]g;
assign p[4:1]=a[4:1]^b[4:1];
assign g[4:1]=a[4:1]&b[4:1];
assign c[2]=(g[1]|(p[1]&cin));
assign c[3]=((g[2])|(p[2]&g[1])|(p[1]&p[2]&cin));
assign c[4]=((g[3])|(p[3]&g[2])|(p[2]&p[3]&g[1])|(p[1]&p[2]&p[3]&cin));
assign
cout=((g[4])|(p[4]&g[3])|(p[3]&p[4]&g[2])|(p[2]&p[3]&p[4]&g[1])|(p[1]&p[2]&p[3]
&p[4]&cin));
assign sum[4:2]=p[4:2]^c[4:2];
assign sum[1]=p[1]^cin;
endmodule

module fa(a,b,cin,sum,cout);
output cout,sum;
input a,b,cin;
assign sum=(a^b^cin);
assign cout=(((a^b)&cin)|(a&b));
endmodule

48
SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: carrysavea.ngr
: carrysavea

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

: 22

Cell Usage :
# BELS

: 22

LUT3

: 12

LUT4

: 10

# IO Buffers

: 22

IBUF

: 16

OBUF

:6

==================================================================
=======

Device utilization summary:

---------------------------

Selected Device : 3sd1800afg676-5

Number of Slices:

13 out of 16640

0%

49
Number of 4 input LUTs:
Number of IOs:
Number of bonded IOBs:

22 out of 33280

0%

22
22 out of 519

4%

SIMULATION:

RESULT:
Thus carry save adder is successfully designed and verified by simulation using ISE
project navigator.

50
EX NO: 10A

CONVERSION OF JK TO T FLIPFLOP

DATE: 27/3/2012

AIM:
To design conversion of JK to T flipflop and verifying it by simulation using Xilinx ise project
navigator.
PROGRAM:

module jkff(j,k,clk,clear,d,q);
input j,k,clk,d,clear;
output q;
reg q;
always@(posedge clk)
begin
if(clear)
q=0;
else
q=(j&(~d))|((~k)&q);
end
endmodule

module JK2T(Q,T,clear,clk);
output Q;
input T,clk,clear;
wire D,J,K;
assign J=T;
assign K=T;
jkff jk1(J,K,clk,clear,D,Q);
assign D=Q;
endmodule

51
SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: JK2T.ngr
: JK2T

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:4

Cell Usage :
# BELS

:1

:1

LUT2

# FlipFlops/Latches
#

FDR

:1
:1

# Clock Buffers
#

:1

BUFGP

:1

# IO Buffers

:3

IBUF

OBUF

:2
:1

==================================================================
=======

Device utilization summary:

---------------------------

52
Selected Device : 3sd1800afg676-5

Number of Slices:

1 out of 16640

0%

Number of Slice Flip Flops:

1 out of 33280

0%

Number of 4 input LUTs:

1 out of 33280

0%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

4
4 out of 519
1 out of

24

0%
4%

SIMULATION:

RESULT:
Thus JK to T flipflop conversion is successfully designed and verified by simulation
using ISE project navigator.

53
EX NO: 10B

CONVERSION OF T TO JK FLIPFLOP

DATE: 27/3/2012

AIM:
To design conversion of T to JK flipflop and verifying it by simulation using Xilinx ise project
navigator.
PROGRAM:

module tff(t,d,clear,clk,q);
input t,d,clear,clk;
output q;
reg q;
always @(posedge clk)
begin
if(clear)
q=0;
else if(t==1)
q=~d;
else
q=d;
end
endmodule

module T2JK(j,k,clk,clear,q);
input j,k,clk,clear;
output q;
wire t,d;
assign t=(j&(~d))|(k&d);
tff tf1(t,d,clear,clk,q);
assign d=q;
endmodule

54

SYNTHESIZE REPORT:
==================================================================
=======
*

Final Report

==================================================================
=======
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: T2JK.ngr
: T2JK

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:5

Cell Usage :
# BELS

:1

:1

LUT3

# FlipFlops/Latches
#

FDR

:1
:1

# Clock Buffers
#

:1

BUFGP

:1

# IO Buffers

:4

IBUF

OBUF

:3
:1

==================================================================
=======

Device utilization summary:

---------------------------

55

Selected Device : 3sd1800afg676-5

Number of Slices:

1 out of 16640

0%

Number of Slice Flip Flops:

1 out of 33280

0%

Number of 4 input LUTs:

1 out of 33280

0%

Number of IOs:

Number of bonded IOBs:

Number of GCLKs:

5 out of 519
1 out of

24

0%
4%

SIMULATION:

RESULT:
Thus T to JK flipflop conversion is successfully designed and verified by simulation
using ISE project navigator.

Janakiram
an

Digitally signed by Janakiraman

DN: cn=Janakiraman, o=College of
Engineering, Guindy, ou=Anna
University,
email=janakiramanforu@yahoo.com
, c=IN
Date: 2012.06.13 23:32:18 +05'30'