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Question Bank PDF

The document contains 15 questions related to VLSI technology and design. The questions cover topics such as reducing complexity in IC design through hierarchy, regularity, modularity and locality; VLSI design flow using the Y chart; comparing semi-custom and full-custom design styles; general FPGA architecture; MOS transistor fabrication processes; isolation techniques between transistors; layout rules for a CMOS inverter; n-type MOSFET fabrication process; MOS structure band diagrams; drain current equations; threshold voltage calculations; and constant field scaling. The document provides the subject code, instructors, and head of the department for reference.

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180 views2 pages

Question Bank PDF

The document contains 15 questions related to VLSI technology and design. The questions cover topics such as reducing complexity in IC design through hierarchy, regularity, modularity and locality; VLSI design flow using the Y chart; comparing semi-custom and full-custom design styles; general FPGA architecture; MOS transistor fabrication processes; isolation techniques between transistors; layout rules for a CMOS inverter; n-type MOSFET fabrication process; MOS structure band diagrams; drain current equations; threshold voltage calculations; and constant field scaling. The document provides the subject code, instructors, and head of the department for reference.

Uploaded by

Tina Taylor
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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C. U.

SHAH COLLEGE OF ENGINEERING AND TECHNOLOGY


DEPARTMENT OF ELECRONICS AND COMMUNICATION

Subject: VLSI Technology and Design


Question bank 1
1)

Subject Code: 161004

Discuss following approaches (with examples) used to reduce complexity of IC design: 1. Hierarchy, 2. Regularity, 3. Modularity, and 4. Locality, 5.Yield, 6. Positive photoresist, 7. Substrate bias effect (body effect). 2) Discuss VLSI design flow in detail using Y chart 3) Compare Semi-custom and Full custom VLSI design style 4) Discuss general architecture of FPGA 5) Discuss fabrication process of NMOS transistor 6) Why do we need isolation between MOS transistors fabricated on a single chip? Explain etched field-oxide isolation and LOCOS isolation techniques with diagrams. 7) Draw layout of CMOS Inverter and indicate minimum eight layout rules of your choice in terms of . 8) Discuss process flow for the fabrication of an n-type MOSFET on p-type Silicon 9) Explain the band diagram of MOS Structure at surface inversion and derive the expression for threshold voltage. 10) With neat sketch explain gradual channel approximation and derive the equation for drain current in linear region mode and saturation mode. 11) Effect of channel length modulation and substrate bias on drain current of NMOS transistor. 12) Calculate the threshold voltage for a polysilicon gate nMOS transistor with the
16 10 ox -14 -2 A -3 D 10 19 -3 -3 ox -19 -8

following parameters: N = 2 x 10 cm , N = 2 x 10 cm , t = 300 x 10 cm, and N = 10 cm . Take kT/q = 26 mV, n = 1.45 x 10 cm , q = 1.6 x 10
i

C, = 3.97
ox

x 8.85 x 10

F/cm, = 11.7 x 8.85 x 10


si

-14

F/cm.

13) Calculate the threshold voltage VTO at VSB = 0, for a polysilicon gate nchannel MOS transistor, with the following parameters: Substrate doping density NA =1016 cm-3, polysilicon gate density ND =2 x 1020 cm-3, gate oxide thickness tox=500 Angstrom and oxide interface fixed charge density Nox= 4 x 1010 cm-2, F( gate) = 0.55V. Physical constants : Thermal voltage =KT/q = 0.026 volt Energy Gap of silicon(Si) =Eg = 1.12 eV Intrinsic Carrier Concentration of silicon = ni =1.45 x 1010 cm 3 Dielectric constant of vaccume = o =8.85 x 10-14 F/cm Dielectric constant of silicon = si = 11.7 x o F/cm Dielectric constant of silicon dioxide = ox = 3.97 x o F/cm 14) Consider a MOS system with the following parameters: tox =200Ao ,

GC = - 0.85 V, NA= 2*1015 cm-3, Qox= q* 2 *1011 C/cm2 1) Determine the threshold voltage V under zero bias at room temperature (T = 300 oK). Note that ox=3.97ev and si=11.7ev. 2) Determine the type (p-type or n-type) and amount of implant. 15) Explain constant field scaling device reduction strategy and show that the power density does not change in a device scaled using this technique.

Subject In-charge Mr. A. I. Darvadiya Mr. H. I. Delvadiya Mr. M. S. Nagar

Prof. D. N. Khandhar H.O.D. E.C.

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