Psahlem

Problem 1: Consider an nMOS having electron mobility of L,= 540 cm²v

Calculate the process transconductance for the gate oxide thickness of 12 nm and 8 nm.
Solution: Hy=540 cmv-ec

Eins Eo
Cor= lox
Eing=3.9 for SiO,
En = 8.85 x 10 Flcm

For to,= 12 nm= 12x 10m= 1.2x 10 ° cm.

l4
3.9 x 8.85 x 10- 14
Cor=
1.2 x 106

Co, =2.876 x 10 Flcm

The process transconductance K=u, Cor:
K=540 x 2.876 x 10
K= 155 u A/V
For tor= 8nm =8x 10 mn=8x 10 cm.
3.9x 8.85 x 10 l4
Cox= .8x 10-6
=4.314 x 10- Flcm2
K= 540x4.314 x 10
= 233 u Ay?
If the oxide thickness is reduced, then the process transconductance increases which
indicates the device is more sensitive.
 Problemn 2: Consider an n-channel MOSFET with the following characteristics:
lox= 10 nm, ,= 520 cm/v - sec, W Vn=7V, calculate the drain current
L8, for
Vgs=2 V and V, =1.2 V, Ve.=2 V and
Va, V.
Solution:

Lox= 10 x 10 m= 10x 10 cm.

Cox= Eins Eo 3.9 x8.,854 x 10 l414
'ox 10 × 10-7
=3.45 x 10 Flcm²
The process transconductance =Cor
K
K= 520x3.45 x 10
=1.794x 10-4 Ary2
= 179 u Ay²
The device transconductance W

B, = 179x 10°x8= 1.43 mAV?

When Ves=2 V and Ve= 1.2 V
sat = Vs - Vm
=2-7
= 13 V

Vde= 1.2 V< Vat Which says the device operates in linear
region, therefore the
current
=1.43x 10 [2 -.7-.6] x 1.2
=1.2 mA

When Ves =2 V and Va,=2 V

Vsat = Vs - Vm
=2.7

= 1.3 V
Since Va=2V> Var the device operates in saturated region. Therefore the current

-1.43
x 10(2-.7]
= 1.2l mA
Droblem 5: Calculate the drain current of
silicon
Lelum and ox= 20nm. The device is biased with VnMOS with V,=1 V, W 10 um,
=3 V and V, =5 V, with surface
ahility of 300 cm/V. Sec and set Vh= 0V. Also
=5V,
calculate the transconductance at
Ves=3V and Va
Solution: The nMOS is biased in saturation since V,> Vo- V,
Therefore the drain current equals;

lds= Cox L w(Vgs-V,

2

where = 300cm/V-S (surface mobility)

W=10 um; L=lum; C, = eo Eins E0 =8.85x 10 Fcm: =39 for silicon --dioxide
lox

ldr=300 x 3.9x 8.85x 10 14

10,(3-D-104 mÀ
X
20 x10-7 2

The transconductance equals:

W
&m = Cox L (Ves-Vi)
3.9 x 8.85 × 10 14
=300x x(3- 1)= 1.04
20 x 10-7 1
hem 0: Cakulate the native threshold voltage for a n-transistor at 300°%
prew nith a Si substrate with N |1.80 × 10, a SiO, gate oxide with lor
i. (Awume , - 0,9 \.=0) thickness 2

Co
+ Vo

Bulk potential

A= Boltzan's constant

= 1380x 107 J/PK

T=300 °K (Temperature)
19
q=1.602 x 10 coulomb (electric charge)
NA = 1.80 x 10° (Density of the carriers)
N,= 145 x 100 cm (at 300°K) (carrier concentration)
E,= 1.06 x10 12 Farad / cm.

1.380 x I0-23 x 300 1.80x 1ol6

1.602 x 10- 19 1.45 x 100
=.36 Volts

Eo Eins
Cox= lox

E)= 8.8S x 1 0 Fcm!

Ens =3.9 for silicon- dioxide

lox = 200 ¢

3.9 x 8.85 x 10 14
Cox=
.2x 10-5

=1.726 x 10 Farads/cm
 MONOCHROME COLOR
Vop
p-channel pul-up VDD
PMOS
In Out
A
n-channel pul-down
NMOS
GND
GND
(a)

VDD

PMOS VDD

PMOS

Input
Output Input Output

NMOS NMOS

GND
GND

(b)

Figure 1.68 The CMOS inverter (a) Circuit Diagram, Stick Drawing
(b) CMOS layer representation
 MONOCHROME COLOR
VDD
VDD

B
A-B
A
A-B

GND
GND

VDD

VDD
PMOS
PMOS
PMOS

In A
In A A-B
A·B In A In A

NMOS
NMOS

NMOS
NMOS
GND

GND

CMOS 2-input NAND Gate (a) Circuit Diagram, Stick Diagram

Figure 1.69 The
(b) CMOS layer Representation
0 Pegn
y(ae) (c+D] wying standad cMos orc (Bakea
Cuos. NnND and O clas no)
using pseudo NMoS oc (Class nob
Design F= [DE+A (B+) (Rle class nota)
Dengn 9= +B) D+E] wirg static
Sdentify boolean Lundion using CMOS C^DK
2= A8+9C+BD
Joyicg9
 = (A + BC) D t+ E
Static CMOS logic T
Voo
A

E
TT OIP

A
c
A
B,

Sh,
A,
-8,

Sh,
A
.B,

Sh,
A,
-B,

Sh, Sh,

Figure 4.46 Barrel shifter

nteror
Shi Sh1 Sh2 Sh2 Sh4 Sh4

As

Az B,

A >B,

A >Bo

Figure 4.47 Logarithmic shifter