UNIT-I

1 a) Enumerate various VLSI Technologies? [L1] [CO2] [2M]

b) Define Threshold Voltage of the MOS transistor. [L1] [CO2] [2M]
c) List the figure of merit of the MOS transistor. [L1] [CO2] [2M]
d) Define Trans conductance and Output Conductance. [L1] [CO2] [2M]
e) Discuss about body bias effect in the NMOS Transistor. [L2] [CO2] [2M]
2 a) Explain working of the NMOS Transistor. [L2] [CO2] [6M]
b) Summarize the evolution of microelectronics. [L2] [CO1] [4M]
3 a) What is the need of VLSI circuits? [L1] [CO2] [4M]
b) Compare the relative merits of three different forms of pull up for an inverter circuit. Which is the best
choice for realization? [L2] [CO2] [6M]
4 a) Compare CMOS with Bipolar technology in different aspects. [L2] [CO1] [4M]
b) Show the circuit diagram of a simple Bi CMOS inverter and explain its operation. [L1] [CO2] [6M]
5 Determine the relationship between Ids & Vds in non-saturated and saturated region. [L3] [CO2] 10M]
6 Illustrate the steps involved in NMOS fabrication process with neat sketches. [L2] [CO1] [10M]
7 a) Illustrate about basic MOS transistors. [L2] [CO1] [4M]
b) Explain the steps involved in Bi-CMOS fabrication process. [L2] [CO1] [6M]
8 Distinguish various pull-up loads used in Inverter Circuit. [L4] [CO5] [10M]
9 Explain the steps involved in PMOS fabrication process with neat sketches. [L2] [CO1] [10M]
10 a) Explain the steps involved in p-well CMOS fabrication process with neat sketches. [L2] [CO1] [6M]
b) Define Metal Oxide Semiconductor VLSI Technology. [L1] [CO1] [4M]
11 Explain the following briefly [L2] [CO2] [10M]
(i) Channel length Modulation
(ii) Trans conductance
(iii) Output Conductance
(iv) Figure of merit (ωo)

UNIT –II

1 a) List different MOS layers. [L1] [CO3] [2M]

b) Draw the circuit diagram of CMOS Inverter Circuit. [L4] [CO3] [2M]
c) Illustrate nMOS transistor in λ-based design rule. [L2] [CO3] [2M]
d) Illustrate a contact cut in λ-based design rule. [L2] [CO3] [2M]
e) Illustrate pMOS transistor in 2μm design rule. [L2] [CO3] [2M]
2 a) Explain the steps involved in VLSI Design flow. [L2] [CO3] [5M]
b) Construct the stick diagram of a 2-input CMOS NAND gate. [L3] [CO3] [5M]
3 a) What is lambda-based design rules? Explain. [L1] [CO3] [5M]
b) Illustrate design rules for wires and MOS transistors. [L2] [CO3] [5M]
4 a) Summarize 2µm based design rules with neat sketches. [L2] [CO3] [5M]
b) Draw the layout diagram of NMOS inverter circuit such that both input and output points are connected
with Polysilicon layer. [L4] [CO3] [5M]
5 a) Explain about Stick diagram with one example. [L2] [CO3] [5M]
b) Sketch the layout diagram for 2-input CMOS NAND gate. [L3] [CO3] [5M]
6 a) Explain 2µm design rules for contacts and transistors. [L2] [CO3] [5M]
b) Sketch the layout diagram for CMOS inverter. [L3] [CO3] [5M]
7 a) Construct stick diagram for = ( + ) in NMOS design style. [L3] [CO3] [5M]
b) Construct the layout diagram for 2-input CMOS NOR gate. [L3] [CO3] [5M]
8 Construct layout diagram for the logic equations in CMOS logic.
 (i) = ( + ) (ii) Z= ( + ) [L3] [CO3] [10M]
9 a) Illustrate λ-design rules for contact cuts. [L2] [CO3] [5M]
b) How a p-MOS transistor forms in lambda-based design rules? Explain. [L1] [CO3] [5M]
10 a) Illustrate stick diagram of AND-OR-INVERTER in CMOS design Style. [L2] [CO3] [5M]
b) Explain about Implant and demarcation line in stick diagrams with neat sketches. [L2] [CO3] [5M]
11 a) Construct the stick diagram for 2-input CMOS XOR gate. [L3] [CO3] [5M]
b) Explain different types of MOS layers used in VLSI circuits. [L2] [CO1] [5M]

OBJECTIVE:

1. NMOS devices are formed in

a) p-type substrate of high doping level
b) n-type substrate of low doping level
c) p-type substrate of moderate doping level
d) n-type substrate of high doping level
Answer: c
Explanation: nMOS devices are formed in a p-type substrate of moderate doping level. nMOS
devices have higher mobility and is cheaper.
2. Source and drain in nMOS device are isolated by
a) a single diode
b) two diodes
c) three diodes
d) four diodes
Answer: b
Explanation: The source and drain regions are formed by diffusing n-type impurity, it gives rise
to depletion region which extend in more lightly doped p-region. Thus Source and drain in a
nMOS device are isolated by two diodes.

3. In depletion mode, source and drain are connected by

a) insulating channel
b) conducing channel
c) Vdd
d) Vss
Answer: b
Explanation: In depletion mode, source and drain are connected by conducting channel but the
channel can be closed by applying suitable negative voltage to the gate.

4. The condition for non saturated region is

a) Vds = Vgs – Vt
b) Vgs lesser than Vt
c) Vds lesser than Vgs – Vt
d) Vds greater than Vgs – Vt
Answer: c
Explanation: The condition for non saturated region is Vds lesser Vgs – Vt. In non saturation
region MOSFET acts as voltage source. Varying Vds will provide significant change in drain
current.

5. In enhancement mode, device is in condition

a) conducting
b) non conducting
c) partially conducting
d) insulating
Answer: b
Explanation: In enhancement mode, the decive is in non conducting condition. For n-type FET,
thershold voltage is positive and p-type threshold voltage is negative.

6. The condition for non conducting mode is

a) Vds lesser than Vgs
b) Vgs lesser than Vds
c) Vgs = Vds = 0
d) Vgs = Vds = Vs = 0
Answer: d
Explanation: In enhancement mode the device is in non conducting mode, and its condition is
Vds = Vgs = Vs = 0.

7. nMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: nMOS transistors are acceptor doped. Acceptor is a dopant which when added
forms p-type region. Some of the accpetors are silicon, boron, aluminium etc.

8. MOS transistor structure is

a) symmetrical
b) non symmetrical
c) semi symmetrical
d) pseudo symmetrical
Answer: a
Explanation: MOS transistor structure is completely symmetrical with respect to source and
drain.

9.. pMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor doped forms
p-type region and donor doped forms n-type region.

10. Inversion layer in enhancement mode consists of excess of

a) positive carriers
b) negative carriers
c) both in equal quantity
d) neutral carriers
Answer: b
Explanation: Inversion layer in enhancement mode consists of excess of negative carriers that is
electron.

11. The condition for linear region is

a) Vgs lesser than Vt
b) Vgs greater than Vt
c) Vds lesser than Vgs
d) Vds greater than Vgs
Answer: b
Explanation: The condition for linear region is Vgs > Vt. The power of MOS in linear region is
less. It is a power dissipating region.

12. As source drain voltage increases, channel depth

a) increases
b) decreases
c) logarithmically increases
d) exponentially increases
Answer: b
Explanation: As source drain voltage Vds increases, the channel depth at the drain end decreases.

13. Speed power product is measured as the product of

a) gate switching delay and gate power dissipation
b) gate switching delay and gate power absorption
c) gate switching delay and net gate power
d) gate power dissipation and absorption
Answer: a
Explanation: Speed power product is measure in picojoules and it is the product of gate
switching delay and gate power dissipation.

MOS TRANSISTORS

1. MOS transistors consists of

a) semiconductor layer
b) metal layer
c) layer of silicon-di-oxide
d) all of the mentioned
Answer: d
Explanation: MOS transistors is formed as a sandwich consisting of a semiconductor layer, a
silicon-di-oxide layer and a metal layer.

2. In MOS transistors, is used for their gate

a) metal
b) silicon-di-oxide
c) polysilicon
d) gallium
Answer: c
Explanation: In MOS transistors, polycrystalline silicon is used for their gate region instead of
metal. Polysilicon gates have replaced all other older devices.

3. The gate region consists of

a) insulating layer
b) conducting layer
c) lower metal layer
d) p type layer
Answer: b
Explanation: The gate region is a sandwich consisting of semiconductor layer, an insulating layer
and an upper metal layer.

4. Electrical charge flows from

a) source to drain
b) drain to source
c) source to ground
d) source to gate
Answer: a
Explanation: Electrical charge or current flows from source to drain depending on the charge
applied to the gate region.

5. Source in MOS transistors is doped with material

a) n-type
b) p-type
c) n & p type
d) none of the mentioned
Answer: a
Explanation: Source and drain in the MOS transistors are doped with N-type material and
substrate is doped with p-type material.

6. In N channel MOSFET which is the more negative of the elements?

a) source
b) gate
c) drain
d) source and drain
Answer: a
Explanation: In N channel MOSFET, source is the more negative of the elements and in the case
of P channel MOSFET, it is the more positive of the elements.

7. If the gate is given sufficiently large charge, electrons will be attracted to

a) drain region
b) channel region
c) switch region
d) bulk region
Answer: b
Explanation: If the gate is given sufficiently large charge, the negative charge carreirs, electrons
will be attracted from the bulk of the substrate material into the channel region below the oxide.
8. Enhancement mode device acts as switch, depletion mode acts as _ switch
a) open, closed
b) closed, open
c) open, open
d) close, close
Answer: a

Explanation: Enhancement mode transistor acts as open switch whereas depletion mode transistor actsas
normally closed switch.

9. Depletion mode MOSFETs are more commonly used as

a) switches
b) resistors
c) buffers
d) capacitors
Answer: b
Explanation: Depletion mode MOSFETs are more commonly used as resistors than as switches.
As permanently on switch it has high resistance.

10. Enhancement mode MOSFETs are more commonly used as

a) switches
b) resistors
c) buffers
d) capacitors
Answer: a

Explanation: Enhancement mode MOSFETs are more commonly used as switches and depletion mode
devices are more used as resistors.

11. Depletion mode transistor should be large.

a) true
b) false
Answer: a
Explanation: Depletion mode transistors should be made large that is long and thin to create the
large „on‟ resistance.
12. Which expression is true?
a) charging time < discharging time
b) charging time > discharging time
c) charging time = discharging time
d) charging time and discharging time are not related
Answer: b
Explanation: When driving a capacitive output load, charging time will be long compared to the
discharging time.

13. Overheating in device occurs due to less number of resistors per unit area.
a) true
b) false
Answer: b
Explanation: When the number of resistors per unit area increases, the device may not dissipate
heat very well. This results in device overheating which leads to its failure.
14. In n channel MOSFET, is constant
a) channel length
b) channel width
c) channel depth
d) channel concentration

Answer: a
Explanation: In all n channel MOSFET transistors, channel length is constant where as channel
width can be varied.

VLSI Design
1. VLSI technology uses to form integrated circuit
a) transistors
b) switches
c) diodes
d) buffers
Answer: a
Explanation: Very-large scale integration is the process of creating integrated circuit with
thousands of transistors into one single chip.
2. Medium scale integration has
a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates

Answer: c
Explanation: Small scale integration has one or more logic gate. Further improved technology is
medium scale integration which consists of hundred logic gates. Large scale integration has
thousand logic gates.

3. The difficulty in achieving high doping concentration leads to

a) error in concentration
b) error in variation
c) error in doping
d) distrubution error
Answer: b
Explanation: As photolithography comes closer to fundamental law of optics, achieving high
accuracy in doping concentration becomes difficult, which leads to error due to variation.

NMOS Fabrication
1. nMOS fabrication process is carried out in
a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals
Answer: a
Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high
purity.
2. impurities are added to the wafer of the crystal
a) n impurities
b) p impurities
c) siicon
d) crystal
Answer: b
Explanation: p impurities are introduced as the crystal is grown. This increases the hole
concentration in the device.

3. What kind of substrate is provided above the barrier to dopants?

a) insulating
b) conducting
c) silicon
d) semi conducting
Answer: a
Explanation: Above a layer of silicon dioxide which acts as barrier, insulating layer is provided
upon which other layers may be deposited and patterned.

4. The photoresist layer is exposed to

a) visible light
b) ultraviolet light
c) infra red light
d) LED
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where
diffusion is to take place.

5. In nMOS device, gate material could be

a) silicon
b) polysilicon
c) boron
d) phosporus
Answer: b
Explanation: In nMOS device, the gate material could be metal or polysilicon. This polysilicon
layer has heavily doped polysilicon deposited by CVD.

6. The commonly used bulk substrate in nMOS fabrication is

a) silicon crystal
b) silicon-on-sapphire
c) phosporus
d) silicon-di-oxide
Answer: c
Explanation: In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-
on-sapphire.

7. In nMOS fabrication, etching is done using

a) plasma
b) hydrochloric acid
c) sulphuric acid
d) sodium chloride
Answer: a
Explanation: In nMOS fabrication, etching is done using hydroflouric acid or plasma. Etching is
a process used to remove layers from the surface.

8. Heavily doped polysilicon is deposited using

a) chemical vapour decomposition
b) chemical vapour deposition
c) chemical deposition
d) dry deposition
Answer: b
Explanation: The polysilicon layer consists of heavily doped polysilicon deposited by chemical
vapour deposition.
9. In diffusion process, impurity is desired
a) n type
b) p type
Answer: a
Explanation: Diffusion is carried out by heating the wafer to high temperature and passing a gas
containing the desired ntype impurity.
10. Contact cuts are made in
a) source
b) drain
c) metal layer
d) diffusion layer
Answer: a
Explanation: Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts
are those places where connection has to be made.
11. Interconnection pattern is made on
a) polysilicon layer
b) silicon-di-oxide layer
c) metal layer
d) diffusion layer
Answer: c
Explanation: The metal layer is masked and etched to form interconnection pattern. The metal
layer was formed using aluminium deposited over the formed surface.
12. SIlicon-di-oxide is a good insulator.
a) true
b) false
Answer: a
Explanation: SIlicon-di-oxide is a very good insulator so a very thin layer is required in the
fabrication of MOS transistor.
13. is used to suppress unwanted conduction
a) phosporus
b) boron
c) silicon
d) oxygen
Answer: b
Explanation: Boron is used to suppress the unwanted conduction between transistor sites. It is
implanted in the exposed regions.
14. Which is used for the interconnection?
a) boron
b) oxygen
c) aluminium
d) silicon
Answer: c
Explanation: Aluminium is the suitable material used for the circuit interconnection or
connecting two layers.

CMOS Fabrication
1. CMOS technology is used in developing
a) microprocessors
b) microcontrollers
c) digital logic circuits
d) all of the mentioned
Answer: d
Explanation: CMOS technology is used in developing microcontrollers, microprocessors, digital
logic circuits and other integrated circuits.

2. CMOS has
a) high noise margin
b) high packing density
c) high power dissipation
d) high complexity
Answer: b
Explanation: Some of the properties of CMOS are that it has low power dissipation, high packing
density and low noise margin.

3. In CMOS fabrication, nMOS and pMOS are integrated in same substrate.

a) true
b) false
Answer: a
Explanation: In CMOS fabrication, nMOS and pMOS are integrated in the same chip substrate.
n-type and p-type devices are formed in the same structure.
4. P-well is created on
a) p subtrate
b) n substrate
c) p & n substrate
d) none of the mentioned
Answer: b
Explanation: P-well is created on n substrate to accommodate n-type devices whereas p-type
devices are formed in the ntype substrate.
5. Oxidation process is carried out using
a) hydrogen
b) low purity oxygen
c) sulphur
d) nitrogen
Answer: a
Explanation: Oxidation process is carried out using high purity oxygen and hydrogen. Oxidation
is a process of oxidizing or being oxidised.
6. Photo resist layer is formed using
a) high sensitive polymer
b) light sensitive polymer
c) polysilicon
d) silicon di oxide
Answer: b
Explanation: Light sensitive polymer is used to form the photoresist layer. Photoresist is a light
sensitive material used to form patterned coating on a surface.
7. In CMOS fabrication,the photoresist layer is exposed to
a) visible light
b) ultraviolet light
c) infra red light
d) fluorescent
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where
diffusion is to take place.
8. Few parts of photoresist layer is removed by using
a) acidic solution
b) neutral solution
c) pure water
d) diluted water
Answer: a
Explanation: Few parts of photoresist layer is removed by treating the wafer with basic or acidic
solution. Acidic solutions are those which have pH less than 7 and basic solutions have greater
than 7.
9. P-well doping concentration and depth will affect the
a) threshold voltage
b) Vss
c) Vdd
d) Vgs
Answer: a
Explanation: Diffusion should be carried out very carefully, as doping concentration and depth
will affect both threshold voltage and breakdown voltage.
10. Which type of CMOS circuits are good and better?
a) p well
b) n well
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of lower
substrate bias effect.
11. N-well is formed by
a) decomposition
b) diffusion
c) dispersion
d) filtering
Answer: b
Explanation: N-well is formed by using ion implatation or diffusion. Ion implantation is a
process by which ions of a material are accelerated in an electrical field and impacted into a
solid. Diffusion is a process in which net movement of ions or molecules play a major role.
12. is sputtered on the whole wafer
a) silicon
b) calcium
c) potassium
d) aluminium
Answer: d
Explanation: Aluminium is sputtered on the whole waffer before removing the excess metal from
the wafer.
1. MOS technology has more load driving capability.
a) true
b) false
Answer: b
Explanation: One of the disadvantage of MOS technology is it has limited load driving
capabilities.
2. What is the disadvantage of MOS device?
a) limited current sourcing
b) limited voltage sinking
c) limited voltage sourcing
d) unlimited current sinking
Answer: a
Explanation: MOS devices have limited current sourcing and current sinking abilities.
3. What are the advantages of BiCMOS?
a) higher gain
b) high frequency characteristics
c) better noise characteristics
d) all of the mentioned
Answer: d
Explanation: BiCMOS provides higher gain, better noise and high frequency characteristics than
MOS transistors.
4. What are the features of BiCMOS ?
a) low input impedance
b) high packing density
c) high input impedance
d) bidirectional
Answer: a
Explanation: Some of the features of BiCMOS are low input impedance, low packing density,
unidirectional, high output drive current etc.
5. BiCMOS has low power dissipation.
a) true
b) false
Answer: b
Explanation: BiCMOS has high power dissipation and CMOS has low power dissipation.
6. CMOS is
a) unidirectional
b) bidirectional
c) directional
d) none of the mentioned
Answer: a
Explanation: BiCMOS is unidirectional and CMOS is bidirectional.

7. In bipolar transistor, its quality can be improved by

a) increasing collector resistance
b) decreasing collector resistance
c) collector resistance does not affect the quality
d) decreasing gate resistance
Answer: b
Explanation: The quality of bipolar transistor can be improved by reducing the collector
resistance, which can be done by using the additional layer of n+ subcollector.
8. BiCMOS can be used in
a) amplifyig circuit
b) driver circuits
c) divider circuit
d) multiplier circuit
Answer: b
Explanation: BiCMOS is more advantageous and improved than CMOS and it can be used in I/O
and driver circuits.

9. Advantages of E-beam masks are

a) small feature size
b) larger feature size
c) looser layer
d) complex design
Answer: a
Explanation: The advantages of E-beam masks are it has tighter layer to layer registration and it
has smaller feature sizes.
10. Which process is used in E-beam machines?
a) raster scanning
b) vector scanning
c) both of the mentioned
d) none of the mentioned
Answer: c
Explanation: The two approaches to the design of E-beam machines are raster scanning and
vector scanning.
11. What is the feature of vector scanning?
a) faster
b) slow
c) easy handling
d) very simple design
Answer: a
Explanation: Vector scanning is faster but data handling involved is more complex. Vector
scanning is done between the end points.
12. Which has high input resistance?
a) nMOS
b) CMOS
c) pMOS
d) BiCMOS
Answer: b
Explanation: CMOS technology has high input resistance and is best for constructing simple
low-power logic gates.

13. BiCMOS has lower standby leakage current.

a) true
b) false
Answer: b
Explanation: BiCMOS has potential for high standby leakage current and has high power
consumption compared to CMOS.

VLSI Questions and Answers – NMOS and

CMOS Fabrication
1. Lithography is:
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip

Answer: a
Explanation: Lithography is the process used to develop a pattern to a layer on the chip.

2. Silicon oxide is patterned on a substrate using:

a) Physical lithography
b) Photolithography
c) Chemical lithography
d) Mechanical lithography

Answer: b
Explanation: Silicon oxide is patterned on a substrate using Photolithography.

3. Positive photo resists are used more than negative photo resists because:
a) Negative photo resists are more sensitive to light, but their photo lithographic resolution
is not as high as that of the positive photo resists
b) Positive photo resists are more sensitive to light, but their photo lithographic resolution
is not as high as that of the negative photo resists
c) Negative photo resists are less sensitive to light
d) Positive photo resists are less sensitive to light

Answer: a
Explanation: Negative photo resists are more sensitive to light, but their photo lithographic
resolution is not as high as that of the positive photo resists. Therefore, negative photo resists
are-used less commonly in the manufacturing of high-density integrated circuits.

4. The is used to reduce the resistivity of poly silicon:

a) Photo resist
b) Etching
c) Doping impurities
d) None of the mentioned
Answer: c
Explanation: The resistivity of poly silicon is reduced by Doping impurities.

5. The isolated active areas are created by technique known as:

a) Etched field-oxide isolation
b) Local Oxidation of Silicon
c) Both the mentioned
d) None of the mentioned
Answer: c
Explanation: To create isolated active areas both the techniques can be used. Among them Local
Oxidation of Silicon(LOCOS) is most efficient.
6. The chemical used for shielding the active areas to achieve selective oxide growth is:
a) Silver Nitride
b) Silicon Nitride
c) Hydrofluoric acid
d) Polysilicon
Answer: b
Explanation: Selective oxide growth is achieved by shielding the active areas. Silicon nitride
(Si3N4) is used for shielding the active areas during oxidation, which effectively inhibits oxide
growth.
7. The dopants are introduced in the active areas of silicon by:
a) Diffusion process
b) Ion Implantaion process
c) Chemical Vapour Deposition
d) Either Diffusion or Ion Implantaion Process
Answer: d
Explanation: Two ways to add dopants are diffusion and ion implantation.

8. To grow the polysilicon gate layer, the chemical used for chemical vapour deposition is:
a) Silicon Nitride(Si4N3)
b) Silane gas(SiH4 )
c) Silicon oxide
d) None of the mentioned
Answer: b
Explanation: Silicon Wafer is placed in a reactor with silane gas (SiH4), and they are heated
again to grow the polysilicon layer by chemical vapor deposition.
9. The process by which Aluminium is grown over the entire wafer , also filling the contact cuts
is:
a) Sputtering
b) Chemical vapour deposition
c) Epitaxial growth
d) Ion Implantation
Answer: a
Explanation: Aluminum is sputtered over the entire wafer, it also fills the contact cuts.

10. Chemical Mechanical Polisihing is used to:

a) Remove silicon oxide
b) Remove silicon nitride and pad oxide
c) Remove polysilicon gate layer
d) Reduce the size of the layout
Answer: b
Explanation: The pad oxide and nitride are removed using a Chemical Mechanical Polishing
(CMP) step.
12. Gate oxide layer consists of:
a) SiO2 layer, overlaid with a few layers of an oxynitrided oxide
b) Only SiO2 Layer
c) SiO2 layer with Polysilicon Layer
d) SiO2 layer and stack of epitaxial layers of Polysilicon
Answer: a
Explanation:Current processes seldom use a pure SiO2 gate oxide, but prefer to produce a stack
that consists of a few atomic layers, each 3–4 Å thick, of SiO2 for reliability, overlaid with a few
layers of oxy-nitrided oxide (one with nitrogen added).
13. What is Piranha Solution
a) It is a 3:1 to 5:1 mix of nitric acid and hydrogen peroxide that is used to develop the oxide
layer on silicon substrate
b) It is a 3:1 to 5:1 mix of sulphuric acid and hydrofluoric acid that is used to clean silicon wafers
removing organic and metal contaminants or photo resist after metal patterning
c) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to grow the oxide
layer on the silicon
d) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to clean wafers of
organic and metal contaminants or photo resist after metal patterning
Answer: d
Explanation: Piranha solution is a 3:1 to 5:1 mix of sulfuric acid and hydrogen-peroxide that is
used to clean silicon wafers of metal and organic contaminants or photo-resist after metal
patterning.

Ids versus Vds Relationships

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Ids versus Vds
Relationships”.

1. Ids depends on
a) Vg
b) Vds
c) Vdd
d) Vss
Answer: b
Explanation: Ids depends on both Vgs and Vds. The charge induced is dependent on gate to
source voltage Vgs also charge can be moved from source to drain under influence of electric
field created by Vds.
2. Ids can be given by
a) Qc x Ʈ
b) Qc / Ʈ
c) Ʈ / Qc
d) Qc / 2Ʈ

Answer: b
Explanation: Ids can be given as charge induced in the channel(Qc) divided by transit time (Ʈ ).
Ids is equivalent to (-Isd).

3. Transit time can be given by

a) L / v
b) v / L
c) v x L
d) v x d
Answer: a
Explanation: Transit time (Ʈ ) can be given by lenght of channel(L) by velocity(v). Transit time is
the time required for an electron to travel between two electrodes.
4. Velocity can be given as
a) µ / Vds
b) µ / Eds
c) µ x Eds
d) Eds / µ
Answer: b
Explanation: Velocity can be given as the product of electron or hole mobility(µ) and electric
field(Eds). It gives the flow velocity which an electron attains due to electric field.
5. Eds is given by
a) Vds / L
b) L / Vds
c) Vds x L
d) Vdd / L
Answer: a
Explanation: Electric field(Eds) can be given as the ratio of Vds and L. Eds is the electric field
created from drain to source due to volta Vds.

6. Mobility of proton or hole at room temperature is

a) 650 cm2/V sec
b) 260 cm2/V sec
c) 240 cm2/V sec
d) 500 cm2/V sec
Answer: c
Explanation: The value of mobility of proton or hole at room temperature is 240 cm2/V sec. This
gives the measure of how fast an electron can move.
7. In resistive region
a) Vds greater than (Vgs – Vt)
b) Vds lesser than (Vgs – Vt)
c) Vgs greater than (Vds – Vt)
d) Vgs lesser than (Vds – Vt)

nswer: b
Explanation: In non saturated or resistive region, Vds lesser than Vgs – Vt where Vds is the
voltage between drain and source, Vgs is the gate-source voltage and Vt is the threshold voltage.
8. The condition for saturation is
a) Vgs = Vds
b) Vds = Vgs – Vt
c) Vgs = Vds – Vt
d) Vds greater than Vgs – Vt

Answer: b
Explanation: The condition for saturation is Vds = Vgs – Vt, since at this point IR drop in the
channel equals the effective gate to channel voltage at the drain.

9. Threshold voltage is negative for

a) nMOS depletion
b) nMOS enhancement
c) pMOS depletion
d) pMOS enhancement

Answer: a
Explanation: The threshold voltage for nMOS depletion denoted as Vtd is negative.

10. The current Ids as Vds increases

a) increases
b) decreases
c) remains fairly constant
d) exponentially increases

Answer: c
Explanation: The current Ids remains fairly constant as Vds increases in the saturation region.

11. In linear region, channel exists

a) uniform
b) non-uniform
c) wide
d) uniform and wide

Answer: a
Explanation: In linear region of MOSFET, the channel is uniform and narrow. This is the
concentration distribution.

12. When the channel pinches off?

a) Vgs>Vds
b) Vds>Vgs
c) Vds>(Vgs-Vth)
d) Vgs>(Vds-Vth)

Answer: c
Explanation: In MOSFET, in saturation region, when Vds > (Vgs – Vth), the channel pinches off
that is the channel current at the drain spreads out.

13. When threshold voltage is more, leakage current will be

a) more
b) less
c) all of the mentioned
d) none of the mentioned

Answer: b
Explanation: Increasing the threshold voltage, leads to small leakage current when turned off and
reduces current flow when turned on.

14. MOSFET is used as

a) current source
b) voltage source
c) buffer
d) divider

Answer: a
Explanation: MOSFET is used as current source. Bipolar junction transistor also acts as good
current source.

Parameters of MOS Transistors

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Parameters of
MOS Transistors”.

1. The work function difference is neagative for

a) silicon substrate
b) polysilicon gate
c) both of the mentioned
d) none of the mentioned

Answer: c
Explanation: The work function difference between gate and Si (Φms) is negative for silicon
substrate and polysilicon gate.
2. Substrate bias voltage is positive for nMOS.
a) true
b) false

Answer: b
Explanation: Substrate bias voltage Vsb is positive for pMOS and negative for nMOS.

3. According to body effect, substrate is biased with respect to

a) source
b) drain
c) gate
d) Vss

Answer: a
Explanation: According to body effect, substrate is biased with respect to the source. Body effect
can be seen as a change in the threshold voltage.

4. Increasing Vsb, the threshold voltage

a) does not effect
b) decreases
c) increases
d) exponentially increases

Answer: c
Explanation: Increasing the substrate bias voltage Vsb, increases the threshold voltage because it
depletes the channel of charge carriers.

5. Transconductance gives the relationship between

a) input current and output voltage
b) output current and input voltage
c) input current and input voltage
d) output current and output voltage

Answer: b
Explanation: Transconductance expresses the relationship between output current Ids and input
voltage Vgs.

6. Transconductance can be increased by

a) decreasing the width
b) increasing the width
c) increasing the length
d) decreasing the length

Answer: b
Explanation: Transconductance gm of a MOS device can be increased by increasing its width
and it does not depend on length.

7. Increasing the transconductance

a) increases input capacitance
b) decreasing area occupied
c) decreasing input capacitance
d) decrease in output capacitance

Answer: a
Explanation: Increasing the transconductance gm results in increase in input capacitance and area
occupied as it is directly proportional.

8. Ids is to length L of the channel

a) directly proportional
b) inversely proportional
c) not related
d) logarithmically related

Answer: b
Explanation: Ids is inversely proportional to the length L of the channel and using this
relationship strong dependence of output conductance on channel length can be demonstrated.

9. Switching speed of a MOS device depends on

a) gate voltage above threshold
b) carrier mobility
c) length channel
d) all of the mentioned

Answer: d
Explanation: Switching speed of a MOS device depends on gate voltage above threshold and on
carrier mobility and inversely as the square of channel length.

10. A fast circuit requires

a) high gm
b) low gm
c) does not depend on gm
d) low cost
Answer: a
Explanation: A fast circuit requires gm as high as possible as the switching speed depends on
gate voltage above threshold and on carrier mobility and inversely to square of channel length.

11. Surface mobility depends on

a) effective drain voltage
b) effective gate voltage
c) channel length
d) effective source voltage

Answer: b
Explanation: Surface mobility is dependent on the effective gate voltage (Vgs-Vt). Electron
mobility on oriented n-type inversion layer surface is larger than that on a oriented surface.

12. MOS transistor is a

a) minority carrier device
b) majority carrier device
c) majority & minority carrier device
d) none of the mentioned

Answer: b
Explanation: MOS transistor is a majority carrier device,in which current in a conducting
channel between the source and drain is modulated by a voltage.

13. The MOS transistor is non conducting when

a) zero source bias
b) zero threshold voltage
c) zero gate bias
d) zero drain bias

Answer: c
Explanation: The MOS transistor normally is at cut-off or becomes non-conducting with zero
gate bias (gate voltage-source voltage).

nMOS Inverter
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “nMOS Inverter”.

1. Inverters are essential for

a) NAND gates
b) NOR gates
c) sequential circuits
d) all of the mentioned

Answer: d
Explanation: Inverters are needed for restoring logic levels for NAND and NOR gates, sequential
and memory circuits.

2. In basic inverter circuit, is connected to ground

a) source
b) gates
c) drain
d) resistance

Answer: a
Explanation: A basic inverter circuit consists of transistor with source connected to ground and a
load resistor connected from drain to positive supply rail Vdd.

3. In inverter circuit, transistors is used as load

a) enhancement mode
b) depletion mode
c) all of the mentioned
d) none of the mentioned

Answer: b
Explanation: Depletion mode transistors are preferred to be used as load in inverter circuits as it
occupies lesser area and are produced on silicon sibstrate unlike resistors.

4. For depletion mode transistor, gate should be connected to

a) source
b) drain
c) ground
d) positive voltage rail

Answer: a
Explanation: For the depletion mode transistor, gate is connected to source so it is always on and
only the characteristic curve Vgs=0 is relevant.

5. In nMOS inverter configuration depletion mode device is called as

a) pull up
b) pull down
c) all of the mentioned
d) none of the mentioned

Answer: a
Explanation: In nMOS inverter configuration, depletion mode devices are called as pull up and
enhancement mode devices are called as pull down transistor.

7. The ratio of Zp.u/Zp.d is given by

a) 1/4
b) 4/1
c) 1/2
d) 2/1

Answer: b
Explanation: The ratio of Zp.u/Zp.d where Z is determined by the length to width ratio of the
transistor, is given by 4/1.

8. Pass transistors are transistors used as

a) switches connected in series
b) switches connected in parallel
c) inverters used in series
d) inverter used in parallel

Answer: a
Explanation: Pass transistors are transistor used as switches in series with lines carrying logic
levels due to its isolated nature of the gate.

9. An inverter driven through one or more pass transistors has Zp.u/Zp.d ratio of
a) 1/4
b) 4/1
c) 1/8
d) 8/1

Answer: d
Explanation: An inverter driven directly from output of another has the ratio of 4/1 and if driven
through one or more pass transistors has the ratio of 8/1.

10. In depletion mode pull-up, dissipation is high since current flows when
a) Vin = 1
b) Vin = 0
c) Vout = 1
d) Vout = 0
Answer: a
Explanation: In nMOS depletion mode pull-up, dissipation is high since current flows Vin =
logical 1.

11. In complementary transistor pull-up, current flows when

a) Vin = 1
b) Vin = 0
c) current doesn‟t flow
d) Vout = Vin

Answer: c
Explanation: In complementary transistor pull-up no current flows either for logical 1 or 0, full
logical 1 and 0 levels are presented at the output.

CMOS Inverter
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “CMOS Inverter”.

1. CMOS inverter has regions of operation

a) three
b) four
c) two
d) five

Answer: d
Explanation: CMOS inverter has five distint regions of operation which can be determined by
plotting CMOS inverter current versus Vin.

2. If n-transistor conducts and has large voltage between source and drain, then it is said to be in
region
a) linear
b) saturation
c) non saturation
d) cut-off

Answer: b
Explanation: If n-transistor conducts and has large voltage between source and drain, then it is in
saturation.
3. If p-transistor is conducting and has small voltage between source and drain, then the it is said
to work in
a) linear region
b) saturation region
c) non saturation resistive region
d) cut-off region

Answer: c
Explanation: If p-transistor is conducting and has small voltage between source and drain, then it
is said to be in unsaturated resistive region.

4. In the region where inverter exhibits gain, the two transistors are in _ region
a) linear
b) cut-off
c) non saturation
d) saturation

Answer: d
Explanation: In the region where the inverter exhibits gain, the two transistors n and p operates
in saturation region.

5. If both the transistors are in saturation, then they act as

a) current source
b) voltage source
c) divider
d) buffer

Answer: a
Explanation: When both the transistors are in saturation, then act as current sources so that the
equivalent circuit is two current sources between Vdd and Vss.

6. If βn = βp, then Vin is equal to

a) Vdd
b) Vss
c) 2Vdd
d) 0.5Vdd

Answer: d
Explanation: If βn = βp, then Vin = 0.5Vdd which implies that the changeover between logic
levels is symmetrically disposed about the point.
7. Mobility depends on
a) transverse electric field
b) Vg
c) Vdd
d) Channel length

Answer: a
Explanation: Mobility is affected by transverse electric field and thus also depends on Vgs and
the mobility of p-device and n-device are inherently unequal.

8. In CMOS inverter, transistor is a switch having

a) infinite on resistance
b) finite off resistance
c) buffer
d) infinite off resistance

Answer: b
Explanation: In CMOS inverter, transistor is a awitch having finite on resistance and infinite off
resistance.

9. CMOS inverter has output impedance

a) low
b) high

Answer: a
Explanation: CMOS inverter has low output impedance and this makes it less prone to noise and
disturbance.

10. Input resistance of CMOS inverter is

a) high
b) low

Answer: a
Explanation: Input resistance of CMOS inverter is extremely high as it is a perfect insulator and
draws no dc input source.

11. Increasing fan-out, the propogation delay

a) increases
b) decreases
c) does not affect
d) exponentially decreases

Answer: a
Explanation: In CMOS inverter, increasing the fan-out also increases the propogation delay. Fan-
out is a term that defines the maximum number of digital inputs that the output of a single logic
gate can feed.

12. Fast gate can be built by keeping

a) low output capacitance
b) high on resistance
c) high output capacitance
d) input capacitance does not affect speed of the gate

Answer: a
Explanation: Fast gate can be built by keeping the output capacitance small and by decreasing
the on resistance of the transistor.

Characteristics of npn Bipolar Transistors

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Characteristics of
npn Bipolar Transistors”.

1. Transconductance of a bipolar is given by

a) (kT/q)/Ic
b) Ic/(kT/q)
c) (q/KT)/Ic
d) Ic/(q/KT)

Answer: b
Explanation: Transconductance gm of a bipolar transistor is given by gm = Ic/(kT/q).
Transconductance is the electrical characteristic relating the current through the output of a
device to the voltage across the input of a device.

2. Transconductance depends on the process.

a) true
b) false

Answer: b
Explanation: Transconductance gm is independent of process.
3. gm is on input voltage Vbe
a) inversely proportional
b) proportional
c) exponentially dependent
d) is not dependent

Answer: c
Explanation: Transconductance gm is exponentially dependent on input voltage Vbe ( base to
emitter voltage).

4. gm is to Ic
a) directly proportional
b) inversely proportional
c) not dependent
d) exponentially proportional

Answer: a
Explanation: Transconductance gm is directly proportional to Ic, collector current.

5. Transconductance is a
a) weak function
b) strong function
c) both
d) none of the mentioned

6. gm of bipolar is less than gm of MOS.

a) true
b) false

Answer: b
Explanation: Transconductance gm of bipolar is greater than gm of MOS if inputs are controlled
by equal amounts of charge.

7. Which of the following is true when inputs are controlled by equal amounts of charge?
a) Cg(MOS) = Cbase(bipolar)
b) Cg(MOS) greater than Cbase(bipolar)
c) Cg(MOS) lesser than Cbase(bipolar)
d) Cs(MOS) lesser than Cbase(bipolar)
Answer: a
Explanation: Cg(MOS) = Cbase(bipolar) when inputs are controlled by equal amounts of
charge, and then gm(bipolar) >> gm(MOS).

8. Which has better I/A ?

a) CMOS
b) bipolar
c) nMOS
d) pMOS

Answer: b
Explanation: Current/Area (I/A) of bipolar is five times better than CMOS and this can be
calculated using base resistance and base transit time.

9. Bipolar transistor exhibits delay

a) turn on
b) turn off
c) storage
d) all of the mentioned

Answer: d
Explanation: Bipolar transistors exhibits tun-on, turn-off, storage delays.

10. In bipolar transistor, which is heavily doped?

a) base region
b) emitter region
c) collector region
d) base and emitter

Answer: b
Explanation: In bipolar transistor, emitter region is heavily doped and base region is lightly
doped.

11. Bipolar transistor is a symmetrical device.

a) true
b) false

Answer: b
Explanation: Bipolar transistor is not symmetrical like other transistors.
BiCMOS Inverters
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “BiCMOS
Inverters”.

1. In BiCMOS, bipolar transistors are used to

a) drive input loads
b) drive output loads
c) to perform logic functions
d) to amplify the input voltage

Answer: b
Explanation: In BiCMOS, bipolar transistors are used to drive output loads. Bipolar transistor
can also be used as amplifier, switch or as an oscillator.

2. In BiCMOS, MOS switches are used to

a) drive input loads
b) drive output loads
c) to perform logic functions
d) to amplify the input voltage

Answer: c
Explanation: In BiCMOS circuits, MOS switches are used to perform logic functions. The ability
to turn the power MOS “ON” and “OFF” allows the device to be used as a very efficient switch
with switching speeds much faster than standard bipolar junction transistors.

3. The nMOS and pMOS transistors used in BiCMOS is

a) depletion mode
b) enhancement mode
c) only pMOS
d) only nMOS

Answer: b
Explanation: The nMOS and pMOS transistors used in BiCMOS device operates in enhancement
mode. Enhancement mode devices are mostly common switching elements in MOS.

4. The inverter has

a) low input impedance
b) high input impedance
c) high output impedance
d) high input and output impedance
Answer: a
Explanation: The inverter has low input impedance. The basic inverter circuit requires a
transistor with source connected to ground and a load resistor connected from the drain to positie
supply Vdd.

5. The inverter has

a) low output impedance
b) low input impedance
c) low power dissipation
d) high input and output impedance

Answer: a
Explanation: The inverter has low output impedance and low input impedance. These are some
of the properties of a BiCMOS inverter.

6. The inverter has

a) high current driving capability
b) occupies smaller area
c) high noise margin
d) all of the mentioned

Answer: d
Explanation: The inverter has high current driving capability, occupies smaller area and has high
noise margins.

7. Output voltage swing should be reduced for a better performance of BiCMOS circuit.
a) true
b) false

8. BiCMOS inverter requires high load current sourcing.

a) true
b) false

Answer: a
Explanation: BiCMOS inverter needs high load current sinking and sourcing. Sinking provides a
grounded connection to the load, whereas sourcing provides a voltage source to the load.

9. BiCMOS has standby leakage current

a) higher
b) lower
Answer: a
Explanation: BiCMOS has higher standby leakage current and thus has high power consumption.

10. For improved base current discharge, _ enhancement type nMOS devices have to be
added
a) two
b) three
c) one
d) four

Answer: a
Explanation: For improved base current discharge, two enhancement type nMOS transistors have
to be added.

11. The BJTs in the BICMOS circuit is in configuration:

a) Push-pull
b) Totem pole
c) Active high
d) Active low

Answer: b
Explanation: In BiCMOS circuit, the BJT transistors are in Totem pole configuration.

12. The MOSFETS are arranged in this configuration to provide:

a) Zero static power dissipation
b) High Input impedance
c) Both zero static power dissipation and high input imedance
d) None of the mentioned

Answer: c
Explanation: MOSFETs provide zero static power dissipation and high input impedance.

Latch-up in CMOS
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Latch-up in
CMOS”.
1. In latch-up condition, parasitic component gives rise to conducting path
a) low resistance
b) high resistance
c) low capacitance
d) high capacitance

Answer: a
Explanation: In latch-up condition, parasitic component gives rise to low resistance conducting
path between Vdd and Vss with disastrous results. Carefull control during fabrication is
necessary to avoid this problem.

2. Latch-up can be induced by

a) incident radiation
b) reflected radiation
c) etching
d) diffracted radiation

Answer: a
Explanation: Latch-up can be induced by glitches on the supply rail or by incident radiation.

3. How many transistors might bring up latch up effect in p-well structure?

a) two
b) three
c) one
d) four

Answer: a
Explanation: Two transistors and two resistances might bring up the latch-up effect in p-well
structure. These are associated with p-well and with regions of the substrate.

4. Substrate doping level should be decreased to avoid the latch-up effect.

a) true
b) false

Answer: b
Explanation: An increase in substrate doping level with a consequent drop in the value of Rs can
be used as a remedy for latch-up problem.

5. What can be introduced to reduce the latch-up effect?

a) latch-up rings
b) guard rings
c) latch guard rings
d) substrate rings

Answer: b
Explanation: The introduction of guard rings can reduce the effect of latch-up problem. Guard
rings are diffusions which decouple the parasitic bipolar transistors.

6. Which process produces circuit which are less prone to latch-up effect?
a) CMOS
b) nMOS
c) pMOS
d) BiCMOS

Answer: d
Explanation: BiCMOS process produces circuits which are less likely to suffer from latch-up
problems where as CMOS circuits are very highly prone to latch-up problems.

7. One of the factor in reducing the latch-up effect is

a) reduced p-well resistance
b) reduced n-well resistance
c) increased n-well resistance
d) increased p-well resistance

Answer: b
Explanation: One of the main factor in reducing the latch-up effect is reduced n-well resistance
Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and higher
value of holding current is also required.

8. The parasitic pnp transistor has the effect of carrier lifetime

a) increasing
b) decreasing
c) exponentially decreasing
d) exponentially increasing

Answer: b
Explanation: The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base
region.

9. The reduction in carrier lifetime brings about

a) reduction in alpha
b) reduction in beta
c) reduction in current
d) reduction in voltage

Answer: b
Explanation: The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base
region which results in radiation in beta.

10. To reduce latch-up effect substrate resistance should be high.

a) true
b) false

Answer: b
Explanation: To reduce the latch-up effect, substrate resistance Rs should be low. Reduction of
Rs and Rw means that larger lateral current is necessary to invite latch-up.

11. Latch-up is the generation of

a) low impedance path
b) high impedance path
c) low resistance path
d) high resistance path

Answer: a
Explanation: Latch-up is the generation of low-impedance path in CMOS chips between the
power suppply and ground rails.

12. Latch-up is brought about by BJTs

a) with positive feedback
b) with negative feedback
c) with no feedback
d) without BJT

Answer: a
Explanation: Latch-up occurs due to BJTs for a silicon-controlled rectifiers with positive
feedback and virtually short circuit the power and ground rail.

13. Sudden transient in power can cause latch-up.

a) true
b) false
Answer: a
Explanation: Sudden transient in power and ground buses are also among the reason which
causes latch-up effect.

14. BJT gain should be to avoid latch-up effect

a) increased
b) decreased
c) should be maintained constant
d) changed randomly

Answer: b
Explanation: BJT gain should be reduced by lowering the minority carrier lifetime through
doping of the substrate to lower the latch-up effect.

BiCMOS Logic Gates

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “BiCMOS Logic
Gates”.

1. The BiCMOS are preferred over CMOS due to:

a) Switching speed is more compared to CMOS
b) Sensitivity is less with respect to load capacitance
c) High current drive capability
d) All of the mentioned

Answer: d
Explanation: These are the 3 advantages of BiCMOS over CMOS.

2. The transistors used in BiCMOS are:

a) BJT
b) MOSFET
c) Both BJT and MOSFETs
d) JFET

Answer: c
Explanation: BiCMOS is a combination of both MOSFET and BJT.

3. The high current driving capability of the BiCMOS is due to:

a) NMOS in saturation mode
b) PMOS in saturation mode
c) CMOS
d) BJT

Answer: d
Explanation: BJT has the high current driving capability.

4. In BiCMOS inverter, the BJT used are:

a) Only Npn BJT
b) Only Pnp BJT
c) Both npn and pnp BJT
d) Multi emitter npn BJT

Answer: a
Explanation: npn BJTs are used in BiCMOS inverter.

5. The drawback of the BiCMOS circuits are:

a) Sensitivity is less load capacitance
b) Bipolar transistors are used for driving current to the load capacitance but not for the logic
operations
c) Increased fabrication Complexity
d) All of the mentioned

Answer: c
Explanation: The other 2 are the merits of BiCMOS, Increased fabrication Complexity is a
demerit of BiCMOS circuits.

6. The Bipolar Transistor is fabricated on :

a) Same substrate of nMOS
b) N-well in p Substrate
c) P-well in n Substrate
d) Same substrate of pMOS

Answer: a
Explanation: BiCMOS is fabricated on the same substrate of nMOS.

7. The n-well created for Bipolar Transistor in BiCMOS is used as:

a) Substrate
b) Collector
c) Emitter
d) None of the mentioned
Answer: b
Explanation: The created nWell is used as Collector region for BiCMOS.

8. The n-well collector is formed by:

a) Lightly doped n-type epitaxial layer on p-Substrate
b) Heavily doped n-type epitaxial layer on p-Substrate
c) Lightly doped n-type diffused layer on p-Substrate
d) Heavily doped n-type diffused layer on p-Substrate

Answer: a
Explanation: To make the doping concentration less than the emitter.

9. The collector contact region is doped with higher concentration of n-type impurities due to:
a) It creates a depletion region at the contact surface
b) It creates a low conductivity path between collector region and contact
c) It reduces a contact resistance
d) It can withstand high voltages as compared to collector region

Answer: c
Explanation: The collector contact region is doped with higher concentration of n-type impurities
reduces contact resistance.

Stick Diagram
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Stick Diagram”.

1. Stick diagrams are those which convey layer information through

a) thickness
b) color
c) shapes
d) layers

Answer: b
Explanation: Stick diagrams are those which convey layer information through color codes.
Thickness is not considered in this stick diagram representation.

2. Which color is used for n-diffusion?

a) red
b) blue
c) green
d) yellow

Answer: c
Explanation: Green color is used to show the presence of n-diffusion layer. The n-type diffusion
will dope the source or drain region in the p-well region.

3. Which color is used for implant?

a) red
b) blue
c) green
d) yellow

Answer: d
Explanation: Yellow color is used to represent implant layer.

4. Which color is used for contact areas?

a) red
b) brown
c) black
d) blue

Answer: c
Explanation: Black color is used to represent contact areas. This is the part where two different
touch or cross each other.

5. Which color is used for polysilicon?

a) brown
b) red
c) white
d) orange

Answer: b
Explanation: Red is used to represent polysilicon layers. It is a semi-conductor like material and
is a hyper pure form of silicon.

6. Which color is used for polysilicon 2?

a) blue
b) brown
c) orange
d) white
Answer: c
Explanation: Orange color is used to represent polysilicon-2 layer.

7. Which color is used for buried contact?

a) black
b) white
c) green
d) brown

Answer: d
Explanation: Brown color is used to represent buried contact. Buried contact is most widely
used, subject to fewer design rule restrictions and are smaller in area.

8. n and p transistors are separated by using

a) differentiation line
b) separation line
c) demarcation line
d) black line

Answer: c
Explanation: Demarcation line separates n and p transistors. Demarcation line is similar to dotted
line in brown.

9. layer should be over layer

a) ntype, polysilicon
b) polysilicon, ntype

Answer: b
Explanation: Polysilicon layer should be over n-type layer. This is the standard pattern used in
stick diagram representation.

11. Implant is represented using

a) black, dark line
b) black, dotted line
c) yellow, dark line
d) yellow, dotted line

Answer: d
Explanation: Implant is represented using yellow color dotted lines. It is drawn in the middle of
the nMOS or pMOS whereever the implant is used.
12. Stick diagram gives the position of placement of the element.
a) true
b) false

Answer: b
Explanation: Stick diagram does not show exact placement of components, transistor length,
wire length and width, tub boundaries etc.

13. When two or more cuts of same type cross or touch each other, that represents
a) contact cut
b) electrical contact
c) like contact
d) cross contact

Answer: b
Explanation: When two or more sticks of same type cross or touch each other, then that forms a
contact called electrical contact.

Design Rules and Layout-1

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Design Rules and
Layout-1”.

1. Circuit design concepts can also be represented using symbolic diagram.

a) true
b) false

Answer: a
Explanation: Circuit design concepts can be represented using stick diagrams and symbolic
diagrams. Stick diagrams represents different layers with color codes. Symbolic diagram
represents the structure with symbols with color codes.

2. Circuit designers need circuits

a) tighter
b) smaller layout
c) decreased silicon area
d) all of the mentioned
Answer: d
Explanation: Circuit designers in general prefer tighter, smaller layouts for improved
performance and decreased silicon area.

3. Process engineers want process

a) smaller
b) tighter
c) reproducible
d) non reproducible

Answer: c
Explanation: Process engineers wants design rules which are controllable and reproducible
process.

4. Maturity level of the process line affects design rules.

a) true
b) false

Answer: a
Explanation: Yes, the maturity level of the process line affects design rules.

5. Design rules does not specify

a) linewidths
b) separations
c) extensions
d) colours

Answer: d
Explanation: Design rules specify line widths, separations and extensions in terms of lambda.

6. The width of n-diffusion and p-diffusion layer should be

a) 3λ
b) 2λ
c) λ
d) 4λ
Answer: b

Explanation: The width of n-diffusion and p-diffusion should be 2λ according to design rules.

7. What should be the spacing between two diffusion layers?

a) 4λ
b) λ
c) 3λ
d) 2λ

Answer: c
Explanation: The spacing between two diffusion layers should be 3λ according to design rules
and standards.

8. What should be the width of metal 1 and metal 2 layers?

a) 3λ, 3λ
b) 2λ, 3λ
c) 3λ, 4λ
d) 4λ, 3λ

Answer: c
Explanation: The width of the metal 1 layer should be 3λ and metal 2 should be 4λ.

9. Implant should extend from all the channels

a) 2λ
b) 3λ
c) 4λ
d) λ

Answer: a
Explanation: Implant for a n-mos depletion mode transistor should extend minimum of 2λ from
the channel in all the directions.

10. Which type of contact cuts are better?

a) buried contacts
b) butted contacts
c) butted & buried contacts
d) none of the mentioned

Answer: a
Explanation: Buried contacts are much better than butted contacts. In butted contacts the two
layers are joined together or binded together using adhesive type of material where as in buried
contact one layer is interconcted or fitted into another.

11. Which design method occupies or uses lesser area?

a) lambda rules
b) micron rules
c) layer rule
d) source rule

Answer: b
Explanation: Micron rules occupies or consumes lesser area. 50% of the area usage can
bereduced by using micron rules over lambda rules.

12. Which gives scalable design rules?

a) lambda rules
b) micron rules
c) layer rules
d) thickness rules

Answer: a
Explanation: Lambda rules gives scalable design rules and micron rules gives
absolutedimensions.

13. Devices designed with lambda design rules are prone to shorts and opens.
a) true
b) false

Answers: b
Explanation: Lambda design rules prevents shorting, opens, contact from slipping out of area
tobe contacted.