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Parallel Binary Adder

The document summarizes two types of parallel binary adders: 1) Ripple carry adder which cascades full adders in series. The carry out of one stage is fed to the next, so the delay increases linearly with bit length. 2) Carry lookahead adder which calculates carry signals in advance based on input signals to reduce carry propagation time. It expresses the carry outputs C1 through C4 as functions of the generate and propagate signals and input carry C0, allowing the outputs to reach steady state faster than the ripple carry adder.

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403 views2 pages

Parallel Binary Adder

The document summarizes two types of parallel binary adders: 1) Ripple carry adder which cascades full adders in series. The carry out of one stage is fed to the next, so the delay increases linearly with bit length. 2) Carry lookahead adder which calculates carry signals in advance based on input signals to reduce carry propagation time. It expresses the carry outputs C1 through C4 as functions of the generate and propagate signals and input carry C0, allowing the outputs to reach steady state faster than the ripple carry adder.

Uploaded by

engr_467856898
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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CS-205 Logic Design & Switching Theory Parallel Binary Adder

S.E (EE) Session 2013 Course Instructor: Syed Jaseemuddin

Parallel Binary Adder


I. Ripple Carry Adder: The ripple carry adder is constructed by cascading full adders (FA) blocks in series. One full adder is responsible for the addition of two binary digits at any stage of the ripple carry. The carryout of one stage is fed directly to the carry-in of the next stage. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder. A number of full adders may be added to the ripple carry adder or ripple carry adders of different sizes may be cascaded in order to accommodate binary vector strings of larger sizes. For an n-bit parallel adder, it requires n computational elements (FA). Figure below shows an example of a parallel adder: a 4-bit ripple-carry adder. It is composed of four full adders. The augends bits of x are added to the addend bits of y respectfully of their binary position. Each bit addition creates a sum and a carry out. The carry out is then transmitted to the carry in of the next higher-order bit. The final result creates a sum of four bits plus a carry out (c4).

Figure 1.Parallel Adder: 4-bit Ripple-Carry Adder Block Diagram

Even though this is a simple adder and can be used to add unrestricted bit length numbers, it is however not very efficient when large bit numbers are used. One of the most serious drawbacks of this adder is that the delay increases linearly with the bit length. As mentioned before, each full adder has to wait for the carry out of the previous stage to output steady-state result. Therefore even if the adder has a value at its input terminal, it has to wait for the propagation of the carry. Taking again the example in figure 1, the addition of x3 and y3 cannot be carried out until c3 becomes available. In turn, c4 has to wait for c3, and so on down to c1. If one full adder takes Tfa seconds to complete its operation, the final result will reach its steady-state value only after 4Tfa seconds. II. Carry Look-ahead Adder: As seen in the ripple-carry adder, its limiting factor is the time it takes to propagate the carry. The carry look-ahead adder solves this problem by calculating the carry signals in advance, based on the input signals. The result is a reduced carry propagation time.

To be able to understand how the carry look-ahead adder works, we have to manipulate the Boolean expression dealing with the full adder. The Propagate P and generate G in a full-adder, is given as: CP = A+B CG = AB
Notice that both propagate and generate signals depends only on the input bits.

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CS-205 Logic Design & Switching Theory Parallel Binary Adder

S.E (EE) Session 2013 Course Instructor: Syed Jaseemuddin

The new expressions for CARRY-out of a full adder can be given as: Cout = AB + CIN(A+B) CG + CPCIN For 1st adder FA1 C1 = CG1 + CP1C0 For 2nd adder FA2 C2 = CG2 + CP2C1 C2 = CG2 + CP2 (CG1 + CP1C0) ; [Since Cout1=Cin1] C2 = CG2 + CP2 CG1 + CP2 CP1 C0) For 3rd adder FA3 C3 = CG3 + CP3C2 C3 = CG3 + CP3 (CG2 + CP2 CG1 + CP2 CP1 C0) ; [Since Cout2=Cin2] C3 = CG3 + CP3 CG2 + CP3CP2CG1 + CP3CP2CP1 C0 For 4th adder FA4 C4 = CG4 + CP4C3 C4 = CG4 + CP4 (CG3 + CP3CG2 + CP3CP2CG1 + CP3CP2CP1 C0) ; [Cout3=Cin3] C4 = CG4 + CP4 CG3 + CP4CP3CG2 + CP4CP3CP2CG1 + CP4CP3CP2CP1 C0 These expressions show that C2, C3 and C4 do not depend on its previous carry-in. Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady state. The same is also true for C2 and C3

Note: Label yourself! Or follow class lecture.

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