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Advanced Digital Design

This document discusses digital design building blocks and system mapping. It covers arithmetic and logic shifts, with arithmetic shifts filling the left end with the sign bit during a right shift. The document also summarizes digital design components like datapath units, control units, and buses/interconnects. It provides examples of registers, memory, and the control unit in a computer system.

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Ali Ahmad
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56 views11 pages

Advanced Digital Design

This document discusses digital design building blocks and system mapping. It covers arithmetic and logic shifts, with arithmetic shifts filling the left end with the sign bit during a right shift. The document also summarizes digital design components like datapath units, control units, and buses/interconnects. It provides examples of registers, memory, and the control unit in a computer system.

Uploaded by

Ali Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Advanced Digital Design

Lecture 09: Digital Design Building Blocks & System Mapping

Arithmetic And Logic Shift

An arithmetic right shift fills the left end with repetitions of the most significant bit (i.e. the sign bit). A logic right shift fills the left end with 0s.

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Examples
1) 0xF0 Arithmetic Shift (F0) 11110000 >> 2 11111100 (FC) Logic Shift (F0) 11110000 >> 2 00111100 (3C) 2) 0x5050 Arithmetic Shift (5050) 0101000001010000 >> 4 0000010100000101 Logic Shift Same as above (since the sign bit is 0) 3) 0xBBCC Arithmetic Shift (BBCC) 1011101111001100 >> 4 1111101110111100 Logic Shift (BBCC) 1011101111001100 >> 4 0000101110111100

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Arithmetic Shift for Division by power-of-two


Arithmetic shifts are used for signed integer data. For example, assume 8-bit Twos complement encoding, 0xF0 is 16. -16 divides by 4 is equivalent to right shift 16 by 2. The logic shift will give a result of +60 (00111100) rather than 4 (11111100). The repetition of the sign bit in the arithmetic shift enables us to use right shift to perform division by power-of-two.

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Digital Design Building Blocks


Datapth Unit Control Unit Busses / Interconnects

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Structure of a Computer
Computer = Processing Unit + Memory System

Processing Unit = Control + Datapath

Datapath = Functional Units + Registers


Functional Units = ALU, Multipliers, Dividers, etc. Registers = Program Counter, Shifters, Storage Registers Inputs = Machine Instruction, Datapath Conditions Outputs = Register Transfer Control Signals Instruction Interpretation = Instruction Fetch, Decode, Execute
Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Control = Finite State Machine

An Abstract View of the RISC Processor


Ideal Instruction Memory Instruction Address Next Address 32 PC

Control
Instruction Rd Rs 5 5 Rt 5 A Rw Ra Rb 32 32-bit Registers 32 B ALU 32 Data Address Data In Clk Data Out Control Signals Conditions

Ideal Data Memory

Clk

Clk

32

Datapath

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Components of the Datapath


Combinational Elements Storage Elements

Clocking methodology

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Combinational Logic Elements


CarryIn

Adder

32

Adder

32

Sum Carry

32 Select

MUX
A B

32 32

MUX

32

ALU
A 32

OP

ALU

32

Result

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

32

Storage Element: Register

Register

Write Enable Data In N Clk Data Out N

Similar to the D Flip Flop except


N-bit

input and output Write Enable input

Write Enable:
negated

(0): Data Out will not

change asserted (1): Data Out will become Data In


Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Storage Element: Register File

Register File consists of 32 registers:

RWRA RB Write Enable 5 5 5 busW 32 Clk 32 32-bit Registers busB 32 busA 32

Two 32-bit output busses: busA and busB One 32-bit input bus: busW

Register is selected by:


RA (number) selects the register to put on busA (data) RB (number) selects the register to put on busB (data) RW (number) selects the register to be written via busW (data) when Write Enable is 1 The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block:

Clock input (CLK)


RA or RB valid => busA or busB valid after access time.

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Storage Element: Idealized Memory

Write Enable Address DataOut 32

Memory (idealized)

One input bus: Data In One output bus: Data Out

Memory word is selected by:


Data In 32 Clk

Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block:

Clock input (CLK)


Address valid => Data Out valid after access time.

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Clocking Methodology
Clk Setup Hold Dont Care Setup Hold

. . .

. . .

. . .

. . .

All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time
Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Control Unit
The TheControl ControlUnit, Unit,also alsocalled calledthe theinstruction instructionunit. unit.It Itis is analogous analogousto tothe thebrain brainand andnervous nervoussystem systemin inthe thehuman human body. body. Main Mainparts: parts:Finite-State Finite-StateMachine Machine

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Controller Unit

A control unit decodes and executes instructions and moves data through the system. Control units can be microprogrammed or hardwired. A microprogram is a program written in a low-level language that is implemented by the hardware. Hardwired control units consist of hardware that directly executes machine instructions.

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Elements of the Control Unit

Standard FSM
State Register Next State Logic Output Logic (datapath control signaling) Plus Additional "Control" Registers: Instruction Register (IR) Program Counter (PC)
Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Busing Strategies
Register-to-Register Communications
Point-to-point Single shared bus Multiple special purpose busses

Tradeoffs between datapath/control complexity and amount of parallelism supported by the hardware

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Point-to-Point Connection Scheme

S0<1:0>

MUX

S1<1:0>

MUX

S2<1:0>

MUX

S3<1:0>

MUX

LD0

R0

LD1

R1

LD2

R2

LD3

R3

Four registers interconnected via 4:1 Mux's and point-to-point connections Edge-triggered N bit registers controlled by LDi signals N x 4:1 MUXes per register, controlled by Si<1:0> signals

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Single bus implementation

S<1:0>

MUX Single Bus

LD0

R0

LD1

R1

LD2

R2

LD3

R3

per register MUX block replaced by single block 25% hardware cost of previous alternative shared set of pathways is called a BUS

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Alternative implementation: Tri-State Buffers

Tri-state buffers as an interconnection scheme


LD0 S<1:0> D E C RO LD1 R1 LD2 R2 LD3 R3

Only one register's contents gated to shared bus at a time Preferred over MUXes

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

Multiple buses
Real datapaths are a compromise between the two extremes
BUS

Register Transfer Diagram or a Single Bus Design: (Highlights the connections between the REGISTERS and the Functional Unit)

Memory Address Bus

M A R

A P C I R A C B

M B R

Memory Data Bus

AC ALU A ("hardwired")

Advanced Digital Design Fall 2004 Lecture 09 Delivered By M. Mohsin Rahmatullah @ CASE

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