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Unit 3 Central Processing Unit-1-7

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24 views7 pages

Unit 3 Central Processing Unit-1-7

Uploaded by

Manesh Patel
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Subject title: Allied 4: COMPUTER SYSTEM ARCHITECTURE

YEAR 2018-19 ONWARDS SEMESTER: IV


SUBJECT CODE: 18BIT44A

UNIT III: Central processing unit: general


register organization – stack organization –
instruction formats – addressing modes – data
transfer and manipulation – programmed control
– reduced instruction set computer – CISC.

Central processing unit:


INTRODUCTION
The part of the computer that performs the bull<
of data-processing operations is called the central
processing unit and is referred to as the CPU. The
CPU is made up of three major parts, as shown in Fig.
The register set stores intermediate data used during
the execution of the instructions. The arithmetic logic
unit (ALU) performs the required micro operations for
executing the instructions. The control unit supervises
the transfer of information among the registers and
instructs the ALU as to which operation to perform.
The CPU performs a variety of functions dictated by
the type of instructions that are incorporated in the
computer. Computer architecture is sometimes
defined as the computer structure and behavior as
seen by the programmer that uses machine language
instructions. This includes the instruction formats,
addressing modes, the instruction set, and the
general organization of the CPU registers.
Components of CPU
General register organization
A bus organization for seven CPU registers is
shown in Fig. The output of each register is connected
to two multiplexers (MUX) to form the two buses A
and B . The selection lines in each multiplexer select
one register or the input data for the particular bus.
The A and B buses form the inputs to a common
arithmetic logic unit (ALU). The operation selected in
the ALU determines the arithmetic or logic micro
operation that is to be performed. The result of the
micro operation is available for output data and also
goes into the inputs of all the registers. The register
that receives the information from the output bus is
selected by a decoder. The decoder activates one of
the register load inputs, thus providing a transfer path
between the data in the output bus and the inputs of
the selected destination register.
The control unit that operates the CPU bus
system directs the information flow through the
registers and ALU by selecting the various
components in the system. For example, to perform
the operation
R 1 <--R2 + R3
the control must provide binary selection variables to
the following selector inputs:
1. MUX A selector (SELA): to place the content of R2
into bus A .
2 . MUX B selector (SELB): to place the content o f R
3 into bus B .
3 . ALU operation selector (OPR): to provide the
arithmetic addition A + B .
4. Decoder destination selector (SELD): to transfer
the content of the output bus into R1 .
The four control selection variables are generated
in the control unit and must be available at the
beginning of a clock cycle. The data from the two
source registers propagate through the gates in the
multiplexers and the ALU, to the output bus, and into
the inputs of the destination register, all during the
clock cycle interval. Then, when the next clock
transition occurs, the binary information from the
output bus is transferred into R 1. To achieve a fast
response time, the ALU is constructed with high-
speed circuits.
Control Word
There are 14 binary selection inputs in the unit, and
their combined value specifies a control word.

Encoding of register selection fields

ALU
The ALU provides arithmetic and logic operations. In
addition, the CPU must provide shift operations. The
shifter may be placed in the input of the ALU to
provide a pre shift capability, or at the output of the
ALU to provide post shifting capability. In some
cases, the shift operations are included with the ALU.

Examples of Micro operations


R 1 <- R 2 - R3
specifies R2 for the A input of the ALU, R3 for
the B input of the ALU, R1 for the destination
register, and an ALU operation to subtract A - B.

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