Fundamentals of Computer Systems

Finite State Machines

Stephen A. Edwards
Columbia University
Spring 2012
Finite State Machine Components
C
L
C
L
CLOCK
Next State Current State
Current State
Inputs
Next State
Current State
Inputs?
Outputs
Moore and Mealy Machines
Next State
Logic
Output Logic
CLK
Next
State
Current
State
Inputs Outputs
The Moore Form:
Outputs are a function of only the current state.
Moore and Mealy Machines
Next State
Logic
Output Logic
CLK
Next
State
Current
State
Inputs Outputs
The Mealy Form:
Outputs may be a function of both the current state and
the inputs.
A mnemonic: Moore machines often have more states.
Mealy Machines are the Most General
C
L
Current
State
Next State
Inputs Outputs
CLK
Another, equivalent way of drawing Mealy Machines
This is exactly the synchronous digital logic paradigm
Moore vs. Mealy FSMs
Alyssa P. Hacker has a snail that
crawls down a paper tape with
1s and 0s on it. The snail smiles
whenever the last four digits it
has crawled over are 1101.
Design Moore and Mealy FSMs of
the snails brain.
State Transition Diagrams: Looking for 1101
S0
0
Moore Machine: States indicate output
S0
Mealy Machine: Arcs indicate input/output
State Transition Diagrams: Looking for 1101
S0
0
S1
0
1
0
Moore Machine: States indicate output
S0
Mealy Machine: Arcs indicate input/output
State Transition Diagrams: Looking for 1101
S0
0
S1
0
S2
0
S3
0
S4
1
1
0
1 0 1
Moore Machine: States indicate output
S0
Mealy Machine: Arcs indicate input/output
State Transition Diagrams: Looking for 1101
S0
0
S1
0
S2
0
S3
0
S4
1
1
0
1 0 1
0
1
0
1
0
Moore Machine: States indicate output
S0
Mealy Machine: Arcs indicate input/output
State Transition Diagrams: Looking for 1101
S0
0
S1
0
S2
0
S3
0
S4
1
1
0
1 0 1
0
1
0
1
0
Moore Machine: States indicate output
S0
Mealy Machine: Arcs indicate input/output
State Transition Diagrams: Looking for 1101
S0
0
S1
0
S2
0
S3
0
S4
1
1
0
1 0 1
0
1
0
1
0
Moore Machine: States indicate output
S0 S1
1/0
0/0
Mealy Machine: Arcs indicate input/output
State Transition Diagrams: Looking for 1101
S0
0
S1
0
S2
0
S3
0
S4
1
1
0
1 0 1
0
1
0
1
0
Moore Machine: States indicate output
S0 S1 S2 S3
1/0
0/0
1/0 0/0
1/1
Mealy Machine: Arcs indicate input/output
State Transition Diagrams: Looking for 1101
S0
0
S1
0
S2
0
S3
0
S4
1
1
0
1 0 1
0
1
0
1
0
Moore Machine: States indicate output
S0 S1 S2 S3
1/0
0/0
1/0 0/0
1/1
0/0
1/0
0/0
Mealy Machine: Arcs indicate input/output
Moore Machine
Next State
S A S
S0 0 S0
S0 1 S1
S1 0 S0
S1 1 S2
S2 0 S3
S2 1 S2
S3 0 S0
S3 1 S4
S4 0 S0
S4 1 S2
Output
S Y
S0 0
S1 0
S2 0
S3 0
S4 1
CLK
CLK
CLK
S

0
S

1
S

2
A
S
0
S
1
S
2
Y
Moore Machine
Next State
S A S
000 0 000
000 1 001
001 0 000
001 1 010
010 0 011
010 1 010
011 0 000
011 1 100
100 0 000
100 1 010
Output
S Y
000 0
001 0
010 0
011 0
100 1
CLK
CLK
CLK
S

0
S

1
S

2
A
S
0
S
1
S
2
Y
Mealy Machine
S A S Y
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S3 0
S2 1 S2 0
S3 0 S0 0
S3 1 S1 1
CLK
CLK
S

1
S

0
A
S
0
S
1
Y
Mealy Machine
S A S Y
00 0 00 0
00 1 01 0
01 0 00 0
01 1 10 0
10 0 11 0
10 1 10 0
11 0 00 0
11 1 01 1
CLK
CLK
S

1
S

0
A
S
0
S
1
Y
More Intuitive Solutions using Shift Registers
A
Y
CLK
Mealy Form: Output Depends on Input Immediately
A
Y
CLK
Moore Form: Output Depends Only on State
FSM Example: A Trafc Light Controller
C
C
This controls a trafc
light at the intersection
of a busy highway and a farm
road. Normally, the highway
light is green but if a sensor
detects a car on the farm
road, the highway light turns
yellow then red. The farm road light then turns green
until there are no cars or after a long timeout. Then, the
farm road light turns yellow then red, and the highway
light returns to green. The inputs to the machine are
the car sensor, a short timeout signal, and a long
timeout signal. The outputs are a timer start signal and
the colors of the highway and farm road lights.
Source: Mead and Conway, Introduction to VLSI Systems, 1980, p. 85.
State Transition Diagram for the TLC
HG
H : G
F : R
HY
H : Y
F : R
C+L/ T
CL/ T
FG
H : R
F : G
FY
H : R
F : Y
S/ T
S/ T
CL/ T
C+L/ T
S/ T
S/ T
Inputs:
C: Car sensor
S: Short Timeout
L: Long Timeout
Outputs:
T: Timer Reset
H: Highway color
F: Farm road color
S H F
HG G R
HY Y R
FG R G
FY R Y
State Transition Diagram for the TLC
HG
H : G
F : R
HY
H : Y
F : R
C+L/ T
CL/ T
FG
H : R
F : G
FY
H : R
F : Y
S/ T
S/ T
CL/ T
C+L/ T
S/ T
S/ T
Inputs:
C: Car sensor
S: Short Timeout
L: Long Timeout
Outputs:
T: Timer Reset
H: Highway color
F: Farm road color
S H F
HG G R
HY Y R
FG R G
FY R Y
State Transition Diagram for the TLC
HG
H : G
F : R
HY
H : Y
F : R
C+L/ T
CL/ T
FG
H : R
F : G
FY
H : R
F : Y
S/ T
S/ T
CL/ T
C+L/ T
S/ T
S/ T
Inputs:
C: Car sensor
S: Short Timeout
L: Long Timeout
Outputs:
T: Timer Reset
H: Highway color
F: Farm road color
S H F
HG G R
HY Y R
FG R G
FY R Y
State Transition Diagram for the TLC
HG
H : G
F : R
HY
H : Y
F : R
C+L/ T
CL/ T
FG
H : R
F : G
FY
H : R
F : Y
S/ T
S/ T
CL/ T
C+L/ T
S/ T
S/ T
S C S L T S
HG 0 X X 0 HG
HG X X 0 0 HG
HG 1 X 1 1 HY
HY X 0 X 0 HY
HY X 1 X 1 FG
FG 1 X 0 0 FG
FG 0 X X 1 FY
FG X X 1 1 FY
FY X 0 X 0 FY
FY X 1 X 1 HG
Inputs:
C: Car sensor
S: Short Timeout
L: Long Timeout
Outputs:
T: Timer Reset
H: Highway color
F: Farm road color
S H F
HG G R
HY Y R
FG R G
FY R Y
State and Output Encoding
S C S L T S
HG 0 X X 0 HG
HG X X 0 0 HG
HG 1 X 1 1 HY
HY X 0 X 0 HY
HY X 1 X 1 FG
FG 1 X 0 0 FG
FG 0 X X 1 FY
FG X X 1 1 FY
FY X 0 X 0 FY
FY X 1 X 1 HG
S H F
HG G R
HY Y R
FG R G
FY R Y
First idea: use a binary
encoding:
HG 00
HY 01
FG 10
FY 10
G 00
Y 01
R 10
State and Output Encoding
S C S L T S
00 0 X X 0 00
00 X X 0 0 00
00 1 X 1 1 01
01 X 0 X 0 01
01 X 1 X 1 10
10 1 X 0 0 10
10 0 X X 1 11
10 X X 1 1 11
11 X 0 X 0 11
11 X 1 X 1 00
S H F
00 00 10
01 01 10
10 10 00
11 10 01
T = S
1
S
0
CL +S
1
S
0
S +
S
1
S
0
(C+L) +S
1
S
0
S
S

1
= S
1
S
0
S +S
1
S
0
+
S
1
S
0
S
S

0
= S
1
S
0
CL +S
1
S
0
S +
S
1
S
0
(C+L) +S
1
S
0
S
H
1
= S
1
H
0
= S
1
S
0
F
1
= S
1
F
0
= S
1
S
0
State and Output Encoding
S C S L T S
00 0 X X 0 00
00 X X 0 0 00
00 1 X 1 1 01
01 X 0 X 0 01
01 X 1 X 1 10
10 1 X 0 0 10
10 0 X X 1 11
10 X X 1 1 11
11 X 0 X 0 11
11 X 1 X 1 00
S H F
00 00 10
01 01 10
10 10 00
11 10 01
T = S
1
S
0
CL +S
0
S +
S
1
S
0
(C+L)
S

1
= S
0
S +S
1
S
0
S

0
= S
1
S
0
CL +
S
0
S +S
1
S
0
(C+L)
H
1
= S
1
H
0
= S
1
S
0
F
1
= S
1
F
0
= S
1
S
0
State and Output Encoding
S C S L T S
00 0 X X 0 00
00 X X 0 0 00
00 1 X 1 1 01
01 X 0 X 0 01
01 X 1 X 1 10
10 1 X 0 0 10
10 0 X X 1 11
10 X X 1 1 11
11 X 0 X 0 11
11 X 1 X 1 00
S H F
00 00 10
01 01 10
10 10 00
11 10 01
T = S
0

S
1
CL +S
1
(C+L)

+
S
0
S
S

1
= S
0
S +S
1
S
0
S

0
= S
0

S
1
CL +S
1
(C+L)

+
S
0
S
H
1
= S
1
H
0
= S
1
S
0
F
1
= S
1
F
0
= S
1
S
0
State and Output Encoding
1
0
1
0
1
0
1
0
C
L
C
L
S
1
T
S

1
S

0
S
S
S
1
S
S
0
S
1
F
1
S
0
H
0
S
1
H
1
S
0
F
0
T = S
0

S
1
CL +S
1
(C+L)

+
S
0
S
S

1
= S
0
S +S
1
S
0
S

0
= S
0

S
1
CL +S
1
(C+L)

+
S
0
S
H
1
= S
1
H
0
= S
1
S
0
F
1
= S
1
F
0
= S
1
S
0
State and Output Encoding
S C S L T S
HG 0 X X 0 HG
HG X X 0 0 HG
HG 1 X 1 1 HY
HY X 0 X 0 HY
HY X 1 X 1 FG
FG 1 X 0 0 FG
FG 0 X X 1 FY
FG X X 1 1 FY
FY X 0 X 0 FY
FY X 1 X 1 HG
S H F
HG G R
HY Y R
FG R G
FY R Y
Second idea: use a one-hot
encoding:
HG 0001
HY 0010
FG 0100
FY 1000
G 001
Y 010
R 100
State and Output Encoding
S C S L T S
0001 0 X X 0 0001
0001 X X 0 0 0001
0001 1 X 1 1 0010
0010 X 0 X 0 0010
0010 X 1 X 1 0100
0100 1 X 0 0 0100
0100 0 X X 1 1000
0100 X X 1 1 1000
1000 X 0 X 0 1000
1000 X 1 X 1 0001
S H F
0001 001 100
0010 010 100
0100 100 001
1000 100 010
T = S
0
CL +S
1
S +
S
2
(C+L) +S
3
S
S

3
= S
2
(C+L) +S
3
S
S

2
= S
1
S +S
2
(C+L)
S

1
= S
0
CL +S
1
S
S

0
= S
0
(CL) +S
3
S
H
R
= S
2
+S
3
H
Y
= S
1
H
G
= S
0
F
R
= S
0
+S
1
F
Y
= S
3
F
G
= S
2
State and Output Encoding
S

0
S

1
S

2
S

3
S
0
H
G
S
1
H
Y
F
R
H
R
S
S
2
F
G
C
L
S
3
F
Y
T = S
0
CL +S
1
S +
S
2
(C+L) +S
3
S
S

3
= S
2
(C+L) +S
3
S
S

2
= S
1
S +S
2
(C+L)
S

1
= S
0
CL +S
1
S
S

0
= S
0
(CL) +S
3
S
H
R
= S
2
+S
3
H
Y
= S
1
H
G
= S
0
F
R
= S
0
+S
1
F
Y
= S
3
F
G
= S
2