Moore Machine

It has one input (a), four internal states (S0 to S3), and one
output (y).

Present Next state

a=0 a=1 Output (y)
state

S0 S0 S2 0
S1 S0 S2 1
S2 S2 S3 1
S3 S3 S1 0

1
entity Moore is port( a, clk: in BIT;
when S2 => y <= ’1’;
y: out BIT);
if a = ’0’ then Next_State <= S2;
end Moore;
else Next_State <= S3;
end if;
architecture bhv of Moore is

type State_Type is (S0, S1, S2, S3); when S3 => y <= ’0’;
signal Current_State : State_Type; if a = ’0’ then Next_State <= S3;
signal Next_State : State_Type; else Next_State <= S1;
begin
end if;
end case;
end process Combin;
-- Process to hold combinatorial logic

Combin: process(Current_State, a)
-- Process to hold synchronous elements
begin
-- (flip-flops)
case Current_State is
Synch: process
when S0 => y <= ’0’;
begin
if a = ’0’ then Next_State <= S0;
wait until clk’event and clk = ’1’;
else Next_State <= S2; Curent_State <= Next_State;
end if; end process Synch;

when S1 => y <= ’1’; end bhv;

if a = ’0’ then Next_State <= S0;

else Next_State <= S2;

end if;

Moore Machine 2
 Mealy Machine
It has again one input (a), four internal states (S0 to S3), and one
output (y).

Present Next state Output (y)

state a=0 a=1 a=0 a=1

S0 S0 S2 0 1
S1 S0 S2 0 0
S2 S2 S3 1 0
S3 S3 S1 0 1

3
entity Mealy is port (a, clk: in BIT;
when S2 =>
y: out BIT);
if a = ’0’ then y <= ’1’;
end Mealy;
NEXT_STATE <= S2;
else y <= ’0’;
architecture bhv of Mealy is

NEXT_STATE <= S3;

type State_Type is (S0, S1, S2, S3);

end if;
signal Curent_State, Next_State: STATE_TYPE;

begin
when S3 =>
if a = ’0’ then y <= ’0’;
-- Process to hold combinatorial logic.
NEXT_STATE <= S3;
Combin: process(Current_State, a)
else y <= ’1’;
begin
NEXT_STATE <= S1;

case Current_State is
end if;

when S0 =>
end case;
if a = ’0’ then y <= ’0’;
end process Combin;
NEXT_STATE <= S0;
-- Process to hold synchronous elements
else y <= ’1’;
-- (flip-flops)
NEXT_STATE <= S2;
Synch: process
end if;
begin
wait until clk’event and Clk = ’1’;
when S1 =>

Current_State <= Next_State;

if a = ’0’ then y <= ’0’;

end process Synch;

NEXT_STATE <= S0;

else y <= ’0’;

end bhv;
NEXT_STATE <= S2;

Mealy Machine
end if;

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Rising-edge detector

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6
 Moore version
library ieee;

use ieee.std_logic_1164.all;

entity edge_detect is

port( clk, reset: in std_logic;

level: in std_logic;

tick: out std_logic );

end edge_detect;

architecture moore_arch of edge_detect is

type state_type is (zero, edge, one);

signal state_reg, state_next: state_type;

begin

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 Moore version
-- state register

process(clk,reset)

begin

if (reset='1') then

state_reg <= zero;

elsif (clk'event and clk='1') then

state_reg <= state_next;

end if;

end process;

-- next-state/output logic

process(state_reg,level)

begin

state_next <= state_reg;

tick <= '0';

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 Moore version
case state_reg is
when one =>
when zero=> if level= '0' then
if level= '1' then state_next <= zero;
state_next <= edge; end if;
end case;
end if;
end process;
when edge => end moore_arch;
tick <= '1';

if level= '1' then

state_next <= one;

else

state_next <= zero;

end if;

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 Mealy version
architecture mealy_arch of edge_detect is

type state_type is (zero, one);

signal state_reg, state_next: state_type;

begin

-- state register

process(clk,reset)

begin

if (reset='1') then

state_reg <= zero;

elsif (clk'event and clk='1') then

state_reg <= state_next;

end if;

end process;

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 Mealy version
process (state_reg,level) -- next-state/output logic

begin

state_next <= state_reg;

tick <= '0';

case state_reg is

when zero=>

if level= '1' then

state_next <= one;

tick <= '1';

end if;

when one =>

if level= '0' then

state_next <= zero;

end if;

end case;

end process;

end mealy_arch;
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 Gate-level
architecture gate_level_arch of edge_detect is

signal delay_reg: std_logic;

begin

-- delay register

process(clk,reset)

begin

if (reset='1') then

delay_reg <= '0';

elsif (clk'event and clk='1') then

delay_reg <= level;

end if;

end process;

-- decoding logic

tick <= (not delay_reg) and level;

end gate_level_arch;

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Comparison
there are several subtle differences in the designs
The Mealy machine-based design requires fewer states and
responds faster, but the width of its output may vary and
input glitches may be passed to the output.

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FSM
Example

Finite State Machine

Traffic Light Controller

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Traffic Light Controller Block
Diagram

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Traffic Light Controller (1)
library ieee;
use ieee.std_logic_1164.all;
–– vhdl model for the Traffic Light Control, sync reset,
-- encoded states

entity tlc_enc is port(

reset, car: in std_logic;
timer, clk: in std_logic;
stateout : out std_logic_vector(2 downto 0);
highway_light: out std_logic_vector(1 downto 0);
farm_light: out std_logic_vector(1 downto 0);
start_short_timer: out std_logic;
start_long_timer: out std_logic );
end tlc_enc;

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Traffic Light Controller (2)
architecture behavior of tlc_enc is
-- constants
constant HGC : std_logic_vector(2 downto 0) := ”000”;
constant HY : std_logic_vector(2 downto 0) := ”001”;
constant FG : std_logic_vector(2 downto 0) := ”010”;
constant FY : std_logic_vector(2 downto 0) := ”011”;
constant HG : std_logic_vector(2 downto 0) := ”100”;
constant GREEN : std_logic_vector(1 downto 0) := ”00”;
constant YELLOW: std_logic_vector(1 downto 0) := ”01”;
constant RED : std_logic_vector(1 downto 0) := ”11”;
-- signals
signal p_state, n_state : std_logic_vector(2 downto 0);

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 Traffic Light Controller (3)
begin

stateout <= p_state;

statereg: process(clk, reset)

if (reset = ’0’) then p_state <= HGC;

elsif (clk’event and clk = ’1’) then p_state <= n_state;

end if;

end process statereg;

comb: process(car, timer, p_state)

begin

–– default assignments

start_short_timer <= ’0’;

start_long_timer <= ’0’;

–– by default, stay in same state!!!

n_state <= p_state;

highway_light <= GREEN; farm_light <= RED;

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Traffic Light Controller (4)
if p_state = HG then

highway_light <= GREEN; farm_light <= RED;

if (timer = ’1’) then n_state <= HGC; end if;

end if;

if p_state = HGC then

highway_light <= GREEN; farm_light <= RED;

if car = ’1’ then n_state <= HY; start_short_timer <= ’1’; end if;

-- Start timer with short timeout value (yellow light)

end if;

if p_state = HY then

highway_light <= YELLOW; farm_light <= RED;

if timer = ’1’ then n_state <= FG; start_long_timer <= ’1’; end if;

-- Start timer with long timeout value

end if;

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Traffic Light Controller (5)
if p_state = FG then
highway_light <= RED; farm_light <= GREEN;
if timer = ’1’ or car = ’0’ then
n_state <= FY; start_short_timer <= ’1’; end if;
end if;

if p_state = FY then
highway_light <= RED; farm_light <= YELLOW;
if timer = ’1’ then
n_state <= HG; start_long_timer <= ’1’; end if;
end if;

end process comb;

end behavior;

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One–Hot Encoding for FSMs
uses one flip–flop per state
Only one flip–flop is allowed ’on’ at anytime
”0001”, ”0010”, ”0100”, ”1000”, for a 4 state FSM

Good for ’flip–flop’ rich implementation technologies

combinational logic is reduced, →a faster FSM
Speed increase is more significant for larger FSMs

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One Hot Encoding for TLC (1)
library IEEE; use IEEE.std_logic_1164.all;

entity tlc_onehot is port (

reset, car: in std_logic;
timer, clk: in std_logic;
stateout: out std_logic_vector(4 downto 0);
highway_light : out std_logic_vector(1 downto 0);
farm_light: out std_logic_vector(1 downto 0);
start_long_timer : out std_logic;
start_short_timer: out std_logic);

end tlc_onehot;

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One Hot Encoding for TLC (2)
architecture behavior of tlc_onehot is
-- constants
constant HG : integer := 0;
constant HGC : integer := 1;
constant HY : integer := 2;
constant FG : integer := 3;
constant FY : integer := 4;
constant GREEN : std_logic_vector(1 downto 0) := ”00”;
constant YELLOW: std_logic_vector(1 downto 0) := ”01”;
constant RED : std_logic_vector(1 downto 0) := ”11”;
-- signals
signal p_state, n_state : std_logic_vector(4 downto 0);

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One Hot Encoding for TLC (3)
begin
stateout <= p_state;

state: process(clk, reset)

begin
if (reset = ’0’) then p_state <= (HGC => ’1’, others => ’0’);
elsif (clk’event and clk = ’1’) then
p_state <= n_state;
end if;
end process state;

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One Hot Encoding for TLC (4)
comb: process(car, timer, p_state)
begin
–– default assignments
start_long_timer <= ’0’; start_short_timer <= ’0’; start <= ’0’;
n_state <= p_state;
highway_light <= GREEN; farm_light <= RED;

if p_state(HG) = ’1’ then

highway_light <= GREEN; farm_light <= RED;
if (timer = ’1’) then
n_state(HG) <= ’0’; n_state(HGC) <= ’1’; end if;
end if;

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One Hot Encoding for TLC (5)
if p_state(HGC) = ’1’ then
highway_light <= GREEN; farm_light <= RED;
if car = ’1’ then
n_state(HGC) <= ’0’; n_state(HY) <= ’1’;
start_short_timer <= ’1’; end if;
end if;

if p_state(HY) = ’1’ then

highway_light <= YELLOW; farm_light <= RED;
if timer = ’1’ then
n_state(HY) <= ’0’; n_state(FG) <= ’1’;
start_long_timer <= ’1’; end if;
end if;

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 One Hot Encoding for TLC (6)
if p_state(FG) = ’1’ then

highway_light <= RED; farm_light <= GREEN;

if timer = ’1’ or car = ’0’ then

n_state(FG) <= ’0’; n_state(FY) <= ’1’;

start_short_timer <= ’1’; end if;

end if;

if p_state(FY) = ’1’ then

highway_light <= RED; farm_light <= YELLOW;

if timer = ’1’ then

n_state(FY) <= ’0’; n_state(HG) <= ’1’;

start_long_timer <= ’1’; end if;

end if;

end process comb;

end behavior;

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 S0
1
A

S1 S5
Dec_n

B
Moving
object Inc_n B B A
S2
A B
Dec_n S3
Inc_n S4
A B

S0 S1 S2 S4 S2 S4 S5 S0 S1 S2 S3 S2

A
B
n-1 n+1

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Simplifying Assumptions
Maximum velocity of the object: 2 m/s
Only one object is aloud on the line
A and B are never simultaneous TRUE
Maximum n: 9999.
Overlapping n: 0000 + Error signal

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