Life on the Edge

A Universal Grammar of Class D

Amplification
Bruno Putzeys
Hypex Electronics, The Netherlands

On the occasion of the 124rd AES Convention, May, 2007

Copyright notice
This presentation 2008 Bruno Putzeys, Hypex
Electronics.
Do not distribute this file, instead link to this file on the
Hypex web site.

Contents
Definition
Basic principles
Class D as Power Converter

Output stage distortion

MOSFET switching behaviour
Output filter errors
Loop control
Topologies, equivalence
Effect of sampling
Effect on modulation linearity

Self-oscillating loops
EMI
Filter components
Board layout

Definition
A class D amplifier is a power amplifier where all active
devices in the power stage are operating in on/off
mode.
On=current, but no voltage
Off=voltage, but no current

Definition
Digital amplifier is an oxymoron
Voltage, current and time are physical quantities
(analogue).
Digital is strings of numbers.
Speakers dont understand numbers.
Class D requires analogue design skills to make work.
DSP control may help solve or exacerbate analogue
issues.

PWM basics
The archetype
+B

Q1

LOAD
Q2

LF in
Triwave in
-B

PWM basics
Two-state clocked PWM

AV

VPWM,pp
Vtri ,pp

VB VB

Vtri ,pp

Some conventions
M

100%

1
0
-1

0.5

75%

1
0
-1

50%

1
0
-1

-0.5

25%

1
0
-1

-1

0%

1
0
-1

t sw t on t off

fs

t on t off
M
t sw
t on

100%
t sw

M 2 1

Spectrum of 2-state PWM

Full-Bridge amplifier in 2 state PWM

Vdd
Vin

VH

VC

VH -VC

VH

Vdd
VC

Three-state PWM (class BD)

Vdd
Vin

VH

VC

VH-VC

VH

Vdd
VC

Spectrum of 3-state PWM

2-State vs 3-State
Three-state...
doubles sampling rate
Better efficiency vs bandwidth

halves open-loop error

Output filter?
Single-core
no excitation current
crossover distortion results

Two-core
excitation current doubles for constant sampling rate

Yet More Phases

Vdd

Vdd
V2

V3

Vdd
Vin

Vdd
V1

V4

It can get worse...

Volume Control
DSD data

Precision Voltage Supply

Power Stage

Shift Register

Permutation
Selector
LPF
Out

Class D as Power Converter

Half bridge
Vdd= 1V

Pdd= 0.375A* 1V= 0.375W

75%* 0.5A= 0.375A

= 75%
= 25%

0.5A

0.5V
0.5A
1
Puit= (0.5V)2* 1= 0.25W

-25%* 0.5A= -0.125A

Vss= -1V

Pss= -0.125A* 1V= -0.125W

Class D as Power Converter

Full bridge
Vdd= 1V

Pdd= 0.25A* 1V= 0.25W

0.25A

75%* 0.5A= 0.375A

Puit= (0.5V)2* 1= 0.25W
0.75V 1
0.25V

= 75%
= 25%

-25%* 0.5A= -0.125A

0.5A

= 25%
0.5A

-25%* 0.5A= -0.125A

= 75%
75%* 0.5A= 0.375A

0.25A

Inductor current
Small modulation index

VswVout

Current changes sense every cycle

Vout

Vsw
IL

IC
C

IC IR

IR
R (?)

IL

Inductor current
Large modulation index

VswVout

Current sense does not change

Vout

Vsw
IL

IC
C

IC IR

IR
R (?)

IL

Dead time effects

Simplified MOSFET model
D

D
G

G
S

Ron

Dead time effects

Small modulation index
+V

+V

+V

+V

-V

-V

-V

-V

PWM

Vsw

Dead time effects

Large modulation index
+V

+V

+V

+V

-V

-V

-V

-V

PWM

Vsw

2 3

Open-Loop Distortion

Analyser Reading

MOSFET parasitics

LD
CGD
CDS
LG

RG
CGS
LS

Parasitic capacitances

Gate Waveform (hard switching, ideal diode)

dVGS
IG
=
dt
CISS (VDS= VDD)

VGS (V)

dVGS
IG
=
dt
CISS (VDS= VDD)

Vth
VDS (V)
IDD

Vdd

VDS
dVDS
I
= G
dt
CRSS

ID
Vgs

Vdd
10V

Ig

ID (A)
IDD

Q G= IG* t ( C )

Gate Waveform (real diode)

VGS (V)

IDD
VDS

Vth

ID
Vgs

Vdd

VDS (V)

Q G= IG* t ( C )

Vdd
Ig

10V
ID (A)

Q G= IG* t ( C )

IDD

Q G= IG* t ( C )

Gate Gotchas
Until and during recovery

Dissipated power = Vcc*Qrr

Vds=Vcc
Gate capacitance is low
But wed like to go slow

After recovery

Vds<Vgs
Gate capacitance is high
Dissipated power = Vds*Id*time
Wed like to finish quickly

Current limiting gate driver works the wrong way round.

Output filter
Desired function
Attenuate the carrier

Undesired functions

Restrict bandwidth
Increase output impedance
Modify the frequency response
Add distortion

Load response of 2nd order LPF

Output Filter
The optimisation problem

Reduce Zout Increase fc Reduce attenuation

Improve Bandwidth Increase fc Reduce attenuation
Improve Flatness Increase fc Reduce attenuation
Reduce distortion Reduce L Reduce attenuation

The root cause

Controlled variable is an internal node
Output voltage is uncontrolled

Summary of (analogue!) nonidealities

Power Supply Rejection
PWM power stage is an AM modulator

Switch Timing
Dead time causes distortion

Output Filter
Output impedance is infinity at fc
Inductor is non-linear

Feedback
Solves many problems at once
Output impedance (post LPF only)
Distortion
Frequency response (post LPF only)

Why many dont use it

Audio folk lore
Feedback sounds bad
Class D is Digital

Why global feedback is even rarer

LC phase shift considered insurmountable
No rules of thumb

Delay in the LC filter?

gain

phase

group delay

Some control theory basics

y A(s) x B(s) y

y A(s) B(s) y A(s) x

A(s) x

A(s) x
y

1 A(s) B(s) 1 A(s) B(s) 1 A(s) B(s)

ETF & STF

1
ETF(s)
1 A(s) B(s)
A(s)
STF(s)
1 A(s) B(s)

Various permutations

A B
1
x

1 B A B
1 B A B

B A B
1
x

1 B A B
1 B A B

AC
1
x C

1 A A C
1 A A C

AC
1
x C

1 A C D
1 A C D

Various permutations

AL B A B
x

A B
1
x

1 AL
1 AL

AL B A B
x

AL
1
x

1 AL
1 AL

AL A A C
AC
1
y
x C

1 AL
1 AL

AL A C D
AC
1
y
x C

1 AL
1 AL

Loop needs
ETF must be stable and not have excessive gain
Poles well left of imaginary axis

ETF must have very low gain in audio band

Zeros close to or on imaginary axis

Loop function AL
Loop poles=zeros of ETF
Loop zeros must be freely settable

Universal loop control function

If AL ...
has n poles and n-1 zeros
has independantly settable zeros

...then
a stable loop is always possible
n 1

n 1

s z a s

AL s k

i 1
n

i 0
n

i
b

p
i i
i 1

i 0

Typical loops
1 pole, no zeros, pre-filter f/b only

Typical loops
2 poles, 1 zero, pre-filter f/b only

Typical loops
3 poles, 2 zeros, mixed feedback

Typical loops
3 poles, 2 zeros, global feedback

d/dt

...also known as...:

Typical loops
...PID!

Proportional
Integrating
Derivative

PI(I...)D control for global loops

Pro
Very low output impedance
Minimum 3rd order loop
Large loop gain

Nonlinear distortion from inductor is reduced

Known art

Contra
Cant get away with bad PCB layout

No good excuses for not using global feedback

Pre-LC and mixed f/b are provably suboptimal

Rearranged loops
Digital PWM + local loop (edge error correction)

Digital PWM

1-bit DAC

Pulse Shpr

Rearranged loops
Hidden analogue amplifier:

Digital PWM

analogue in

50% duty cycle

Pulse Shpr

Rearranged loops
No news at all, really:

analogue in

Rearranged loops
Indirect digital feedback

1-bit DAC

Noise
Shaped
PWM

Noise
Shaped
Corr

ADC

Rearranged loops
...a remarkable similarity...

Noise
Shaped
PWM

+
1-bit DAC

ADC

Noise
Shaped
Corr

Full ADC based feedback

ADC

H(z)

PWM

Full ADC based feedback

Reasons for use
Silicon area of ADC + loop control < equivalent analogue
loop.
Complicated linearization circuits
Start/stop/overload recovery

Not reasons for use

Nearly anything else:
digital, hence better
investor retention

Effect of sampling on loop control

Effect of sampling on loop control

Noise Shaper Theorem holds

NTF

Transform AL to z domain
Highly optimised AL may seem instable in linear analysis
and be critically damped in sampled system!

Effect of sampling on loop control

Most PWM is double-sided
fs = fsw (low modulation index)
fs = 0.5fsw (clipping)

ETF (NTF) becomes modulation dependent

Ripple aliasing

R
PWM

Triangular Reference=R

Control=(Input-PWM)*H(z)=C
PWM

Ripple aliasing
Ripple distorts carrier

Dealing with Ripple Aliasing

Local Error Feedback (PEDEC etc)
Digital PWM

1-bit DAC

Pulse Shpr

Operation
Minimal ripple in feedback loop.

Pro
Theoretically perfect regardless of loop order

Contra
Gains must be matched: 1-bit DAC and PWM must scale with supply
PWM generator is a problem in its own right
Not compatible with post-filter feedback

Dealing with Ripple Aliasing

Carrier slope correction (Candy)
Operation
Dynamically modify triangle wave slopes

Pro
Theoretically perfect for 1st order loop
Reasonably compatible with higher order including mixed post-filter
f/b

Contra
Complex triwave generation

Dealing with Ripple Aliasing

Minimum Aliasing Error filter (Risbo)

MAE

Operation
Ripple in feedback loop not reduced, phase shift optimised for
minimum impact.

Pro
Grafts well onto standard control circuit.
Compatible with post-filter feedback (perhaps not fully global)

Dealing with Ripple Aliasing

Invariant PWM (Yours Truly)
Operation
Secret

Pro
Perfectible for any loop (5th order with global f/b demonstrated)
Compatible with global f/b
Closed-form analysis and design

Contra
Complex triwave generation
High sensitivity to parts tolerance

Self-Oscillating Loops
Aim
Getting rid of the oscillator
Improving maximum modulation index

Self-Oscillating Loops
Hysteresis modulator

out

in
comparator

power stage

Hysteresis modulator
Operation
Vint

Vf
Va

Vb
t1

t0

Hysteresis modulator
Improved version

out

in
comparator

power stage

Hysteresis modulator
Output Signal
50
40
30
20
10
0
-10
-20
-30
-40
-50
0

500u

1m

Hysteresis modulator
Completely linear
Switching frequency falls early
becomes audible near clip

Hysteresis modulator
Post-LPF added

out

in
comparator

power stage

Less linear
No-load stability not guaranteed

Hysteresis modulator
Capacitor current feedback (Mueta)

in

Global loop
Good linearity
Current sense has low EMI sensitivity

out

Phase-shift controlled oscillation

Operation
Oscillation frequency set by loop phase

in

out

comparator power stage

Phase-shift controlled oscillation

Output signal
50
40
30
20
10
0
-10
-20
-30
-40

500u

1m

Phase-shift controlled oscillation

Nonlinear, depends on design
Switching frequency is more stable

Phase-shift controlled oscillation

Phase shift controlled oscillator with global loop (UcD)

Clead
Rf
in

Rlead

Ri
out

delay=tprop
comparator

power stage

UcD
Operation
Combined phase shift of output filter, lead network and
propagation delay set fosc.
Extra pole may be added

UcD
+180

Ph(Delay(f))

Ph(Hlpf(f)*Hfbn(f))
Ph(Hlpf(f)*Hfbn(f)*Delay(f))
Ph(Hlpf(f))
-180
100

1k

10k

100k

Oscillation Frequency

1M

Phase-shift controlled oscillation

Modulator gain

dV1/dt

dV2/dt

1/fsw

Phase-shift controlled oscillation

Small-signal linearized model

ADC

2 VCC fsw

dV1
dV2
dt
dt

Clead
Rf
in

Rlead

Ri
ADC

out

Phase-shift controlled oscillation

10
8
6
4
2
0
-2
-4
-6
-8
-10
0

100u

200u

Class D and EMI

Low-frequency EMI: Carrier and low harmonics.

Close match with theory.

Ripple cancelling possible.
Not an EMI issue except for long cables
Not a tweeter issue (come off it!)

Class D and EMI

Common and Differential Mode in H-Bridge Class D
Class AD. Carriers and modulation are out of phase

Note: Common-mode is what radiates off cables.

Class D and EMI

Class BD.
Carriers are in phase. Modulation is out of phase.

HF across load is reduced but CM increases.

Class D and EMI

Half bridge vs Full Bridge, Class AD vs BD
Half-bridge
Cant cancel either CM or DM
Common-mode is half of differential mode

AD
Common-mode voltage theoretically 0
Differential mode same as half bridge

BD
Differential mode cancels at low modulation...
...but that was not really a problem anyway.
Common-mode voltage same as half bridge

Class D and EMI

High-Frequency EMI: Leaking switching transients
Theoretical modeling is useless.
Capacitors become inductive
Inductors become capacitive
PCB becomes jumble of Ls and Cs.

No tricks. Only good hardware design helps.

Direct EMI problem under all circumstances.

Class D and EMI

Sensitive item 1: The capacitor.
Myth of the Low Inductance Capacitor.
(An Audiophile Favourite)
All modern film caps have sprayed end contacts.
Inductance is determined by geometry only (mostly size).

Bad.

Period.

Good.

Class D and EMI

Sensitive item 2: The inductor.
Stray fields out of toroids

Upright mounted toroids are worst.

Class D and EMI

Sensitive item 2: The inductor.
Beware of indirect Capacitive Coupling through Core
Tight windings are better
magnetically but worse
electrostatically.
No external electrostatic shield:
Capacitive coupling to chassis
etc. can get significant.

Toroids are not always optimal

Class D and EMI

Sensitive item 2: The inductor.
Ferrite inductors: avoid direct capacitive coupling
between windings

Hot end sees Cold end

2 layers is worst case situation
1 layer is best

Class D and EMI

Sensitive item 3: The PCB layout.
Contiguous ground plane
Keep connectors together

Avoid capacitive coupling to external parts

Minimize loop area (short traces)

Class D and EMI

Checking for EMI without Spectrum Analyser
Just probe around the external connections with a
scope!!!
If you see rubbish, there is rubbish
The higher the frequency, the more you should worry

Class D and EMI

Example: Amplifier A, rated 160W
FETs
Plane Split

Out

Line In

LPF

(sketch of circuit board found in commercially available amp)

DC in

Class D and EMI

Amplifier A, one output line
1V/div. Probe clip at RCA ground.

Class D and EMI

Amplifier A, common mode
500mV/div. Amp is claimed to pass FCC???

Class D and EMI

Amplifier A, differential mode
500mV/div. Note: relatively clean.

Class D and EMI

Example: Amplifier B, rated 2kW
LPF

DC in

Out
Line in

Power stage

Class D and EMI

Amplifier B, common mode
250mV/div. Probe clip at power GND faston tab

Class D and EMI

Amplifier B, differential mode
500mV/div.

Class D and EMI

Class D EMI is no mystery
Eyeballing components and PCB gives good indication
Invest in an analogue scope
Dont bother EMC testing if the scope pic isnt squeaky
clean

Summary
All Unique Class D Technologies are related
All draw from a limited set of concepts
Modulation technique
Power stage arrangement
Loop control

Not all are optimal

Too complex
Missed opportunities

Summary
Good design criteria: black box

Audio performance
Robustness
Simplicity
EMC, efficiency...

Bad design criteria: open box

Perceived novelty and uniqueness
Belief system
Digitalness
Feedbacklessness

Powerpoint appeal

Summary of summaries
The Road To Heaven
Specify the performance and accept the design

The Road To Hell

Specify the design and accept the performance

Thank you!