EXPERIMENT:1

INTRODUCTION TO VERILOG/VHDL AND DESIGN OF ALL

THE LOGIC GATES
INTRODUCTION
The word digital has made a dramatic impact on our society. More significant is a continuous
trend towards digital solutions in all areas – from electronic instrumentation, control, data
manipulation, signals processing, telecommunication etc., to consumer electronics. Development
of such solutions has been possible due to good digital system design and modeling techniques.

VERILOG AS AN HDL
Verilog has variety of constructs as part of it. All are aimed at providing a functionally tested and
a verified design description for the target FPGA or ASIC. The language has a dual function- one
fulfilling the need for a design description and the other fulfilling the need for verifying the
design for functionality and timing constraints like propagation delay, critical path delay, slack,
setup, and hold times.

Verilog as an HDL has been introduced here and its overall structure explained. A widely
used development tool for simulation and synthesis has been introduced; the brief procedural
explanation provided suffices to try out the Examples and Exercises in the text.

LEVELS OF DESIGN DESCRIPTION

The components of the target design can be described at different levels with the help of the
constructs in Verilog.

1.Gate level or Structural modeling

At the gate level of abstraction, design is carried out in terms of basic gates. All the basic gates
are available as ready modules called “Primitives.” Each such primitive is defined in terms of its
inputs and outputs. Primitives can be incorporated into design descriptions directly.

2.Data Flow

Data flow is the next higher level of abstraction. All possible operations on signals variables are
represented here in terms of assignments. All logic and algebraic operations are accommodated.
The assignments define the continuous functioning of the concerned block. At the data flow
level, signals are assigned through the data manipulating equations. All such assignments are
concurrent in nature.
3.Behavioral Level

Behavioral level constitutes the highest level of design description; it is essentially at the system
level itself. With the assignment possibilities, looping constructs and conditional branching
possible, the design description essentially looks like a “C” program. The statements involved
are “dense” in function. Compactness and the comprehensive nature of the design description
make the development process fast and efficient.

FUNCTIONAL VERIFICATON
Testing is an essential ingredient of the VLSI design process as with any hardware circuit. It has
two dimensions to it – functional tests and timing test. Both can be carried out with Verilog.
Often testing or functional verification is carried out by setting up a “test bench” for the design.
The test bench will have the design instantiated in it; it will generate necessary test signals and
apply them to the instantiated design. The outputs from the design are brought back to the test
bench for further analysis. The input signal combinations, waveforms and sequences required for
testing are all to be decided in advance and the test bench configured based on the same.
 B)DESIGN OF ALL THE LOGIC GATES

Aim:
To design all logic gates using gate level model of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Theory:
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary
conditions low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can, and generally does, change often, as the circuit processes data. In most logic gates,
the low state is approximately zero volts (0 V), while the high state is approximately five volts
positive (+5 V).

There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.

The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in
the same way as the logical "and" operator. The following illustration and table show the circuit
symbol and logic combinations for an AND gate. The output is "true" when both inputs are
"true." Otherwise, the output is "false."

The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive
"or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then
the output is "false."

A logical inverter, sometimes called a NOT gate to differentiate it from other types of electronic
inverter devices, has only one input. It reverses the logic state.

The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of the
logical operation "and" followed by negation. The output is "false" if both inputs are "true."
Otherwise, the output is "true."

The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both
inputs are "false." Otherwise, the output is "false."
The XOR (exclusive-OR) gate acts in the same way as the logical "either/or." The output is
"true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are
"false" or if both inputs are "true." Another way of looking at this circuit is to observe that the
output is 1 if the inputs are different, but 0 if the inputs are the same.

The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its output
is "true" if the inputs are the same and "false" if the inputs are different.

CIRCUIT DIAGRAMS:
Program:
module lg(a,b,y1,y2,y3,y4,y5,y6,y7);
input a,b;
output y1,y2,y3,y4,y5,y6,y7;
wire a,b;
and g1(y1,a,b);
or g2(y2,a,b);
not g3(y3,a);
nand g4(41,a,b);
nor g5(y5,a,b);
xor g6(y6,a,b);
xnor g7(y7,a,b);
endmodule

Test Bench:
module lg_tb;
wire y1,y2,y3,y4,y5,y6,y7;
reg a,b;
lg l1(a,b,y1,y2,y3,y4,y5,y6,y7);
initial
begin
a=0; b=0;
#10 a=0; b=1;
#10 a=1; b=0;
#10 a=1; b=1;
#50 $stop;
end
endmodule

Output:
Result:
Hence, all logic gates using data flow model of Verilog HDL program is designed and simulated
using Vivado 2014.4.
 EXPERIMENT:2

DESIGN OF HALF ADDER, FULL ADDER USING 3 MODELING

STYLES
A) Half Adder
Aim:
To design half adder using 3 modeling styles of Verilog HDL program and to perform
simulation.

Apparatus:

1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Program:
A) Gate level model B)Data flow model
module HA(a,b,sum,carry); module HA(a,b,sum,carry);
input a,b; input a,b;
output sum,carry; output sum,carry;
xor L1(sum, a,b); assign sum=a^b;
and L2(carry.a.b); carry=a&b;
endmodule endmodule

C)Behavioral model
module HA(a,b,sum,carry);
input a,b;
output sum,carry;
reg sum, carry;
always(a,b)
begin
if(a!=b)
sum=1;
else
sum=0;
end
always@(a,b)
begin
if(a==1&&b==1)
carry=1;
else
carry=0;
end
endmodule
 Test Bench:

module HA_tb;
wire sum, carry;
reg a,b;
HA l1(a,b,sum,carry);
initial
begin
a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
#10 a=0;b=1;
#50 $stop;
end
endmodule

Output:

Result:

Hence, Half adder using 3 modeling styles of Verilog HDL program is designed and simulated
using Vivado 2014.4.
 B)Full Adder
Aim:
To design full adder using 3 modeling styles of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Theory:
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to the another.
A full adder is a digital circuit that performs addition. Full adders are implemented with logic
gates in hardware. A full adder adds three one-bit binary numbers, two operands and a carry bit.
The adder outputs two numbers, a sum and a carry bit. The term is contrasted with a half adder,
which adds two binary digits.

A full adder takes two binary numbers plus a carry or overflow bit. The output is a sum and
another carry bit. Full adders are made from XOR, AND and OR gates in hardware. Full adders
are commonly connected to each other to add bits to an arbitrary length of bits, such as 32 or 64
bits. A full adder is effectively two half adders, an XOR and an AND gate, connected by an OR
gate.

BLOCK DIAGRAM:
CIRCUIT DIAGRAM:

TRUTH TABLE:
Program:

A) Data flow model:

module fa(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a^b^c;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule

B) Gate level or Structural model:

module fa(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire w1,w2,w3,w4,w5;
xor x1(w1,a,b);
xor x2(sum,w1,cin);
and a1(w2,a,b);
and a2(w3,b,cin);
and a3(w4,cin,a);
or r1(w5,w2,w3);
or r2(cout,w5,w4);
endmodule

C) Behavioral model:

module fa(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always@(a or b or cin)
begin
sum=a^b^cin;
cout=(a&b)|(b&cin)|(cin&a);
end
endmodule
Test Bench:

module fa_tb;
wire sum, cout;
reg a,b,cin;
fa l1((a,b,cin,sum,cout);
initial
begin
a=0;b=0;cin=0;
#10 a=0;b=0;cin=1;
#10 a=0;b=1;cin=0;
#10 a=0;b=1;cin=1;
#10 a=1;b=0;cin=0;
#10 a=1;b=0;cin=1;
#10 a=1;b=0;cin=1;
#10 a=1;b=1;cin=1;
#50 $stop;
end
endmodule

Output:
Result:

Hence, Full adder using 3 modeling styles of Verilog HDL program is designed and simulated
using Vivado 2014.4.
 EXPERIMENT:3
DESIGN OF HALF SUBTRACTOR, FULL SUBTRACTOR
USING 3 MODELING STYLES
A) Half Subtractor
Aim: To design half subtractor using 3 modeling styles of Verilog HDL program and to perform

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:
The half subtractor is also a building block for subtracting two binary numbers. It has two inputs
and two outputs. This circuit is used to subtract two single bit binary numbers A and B. The 'diff'
and 'borrow' are two output states of the half subtractor.

Block diagram:
Circuit Diagram:

Truth Table:
Program:
module hs(a,b,diff,borrow);
input a,b;
outpur diff, borrow;
assign diff=a^b:
assign borrow=~a&b;
endmodule

Test Bench:
module hs_tb;
reg a,b;
wire diff,borrow;
hs L1(a,b,diff, borrow);
initial
begin
a=0; b=0;
#10 a=0; b=1;
#10 a=1; b=0;
#10 a=1, b=1;
#50 $stop;
end
endmodule

Output:
Result:
Half Subtractor is designed using dataflow model of Verilog HDL program and simulation is
performed.

B) Full Subtractor

Aim: To design full subtractor using 3 modeling styles of Verilog HDL program and to perform

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Theory:
A full subtractor is a combinational circuit that performs subtraction involving three bits, namely
A (minuend), B (subtrahend), and Bin (borrow-in). It accepts three inputs: A (minuend), B
(subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout
(borrow out). The logic symbol and truth table are shown below.

Block Diagram:

Circuit Diagram:

Truth Table:
Program:
module fs(a,b,bin,d,bout);
input a,b,bin;
output d,bout;
assign d=a^b^bin;
assign bout=((~a)&(b^c))|(b&c);
endmodule

Test Bench:
module fs_tb:
reg a,b,bin,
wire d, bout;
fs L1(a,b,bin,d,bout);
initial
begin
a=0: b=0; c=0;
#10a=0: b=0; c=1;
#10a=0: b=1; c=0;
#10a=0: b=1; c=1;
#10a=1: b=0; c=0;
#10a=1: b=0; c=1;
#10a=1: b=1; c=0;
#10a=1: b=1; c=1;
#50 $stop:
end
endmodule
Output:

Result:
Full Subtractor is designed using dataflow model of Verilog HDL program and simulation is
performed.

EXPERIMENT:4
DESIGN OF 4X16 DECODER USING TWO 3X8 DECODERS
Aim:
To design 4X16 Decoder using two 3X8 Decoders using behavioral model of Verilog HDL
program and to perform simulation.
Apparatus:
1. Personal Computer
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:
A decoder is a combinational circuit constructed with logic gates. It is the reverse of the encoder.
A decoder circuit is used to transform a set of digital input signals into an equivalent decimal
code of its output. For ‘n’ inputs a decoder gives 2^n outputs. In this article, we will discuss on 4
to 16 decoder circuit design using 3 to 8 decoders.

Circuit Diagram:

Program:
module dec3x8(i,en,dec);
input [2:0]i;
input en;
output [7:0]dec;
reg [7;0]dec;
always@(i or en)
begin
if(en==0)
dec=8’b00000000;
elseif(en==1)
case(i)
0:dec=8’b00000001;
1:dec=8’b00000010;
2:dec=8’b00000100;
3:dec=8’b00001000;
4:dec=8’b00010000;
5:dec=8’b00100000;
6:dec=8’b01000000;
7:dec=8’b10000000;
default:dec=8’b11111111;
endcase
else
dec=256;
end
endmodule

module dec4x16(a,y);
input[3:0]a;
output[15;0]y;
dec3x8 X1(a[2:0],a[3],y[15:8]);
dec3x8 X2(a[2:0],~a[3],y[7:0]);
endmodule

Test Bench:
module dec4x16_tb;
reg[3:0]a;
wire[15;0]y;
dec4x16 L1(a,y);
initial
begin
a=4’b0;
#10 a=4’b1010;
#10 a=4’b1001;
#10 a=4’b1110;
#10 a=4’b1111;
#20 $stop;
end
endmodule
Output:

Result:
Decoder 4X16 is designed using Verilog HDL program and simulation is performed.

EXPERIMENT:5
DESIGN OF 8-TO-3 ENCODER (WITHOUT AND WITH
PRIORITY)
A)Without Priority
Aim:
To design 8-to-3 encoder without priority using behavioral model of Verilog HDL program and
to perform simulation.
Apparatus:
1. Personal Compute.r
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Theory:
An Encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another. The purpose of encoder is standardization,
speed, secrecy, security, or saving space by shrinking size. Encoders are combinational logic
circuits and they are exactly opposite of decoders. They accept one or more inputs and generate a
multibit output code.
Encoders perform exactly reverse operation than Decoder. An Encoder has M input and N output
lines. Out of M input lines only one is activated at a time and produces equivalent code on output
N lines. If a device output code has fewer bits than the input code has, the device is usually
called an encoder.
If the input circuit can guarantee at most a single-active input, a simple encoder is a better choice
than a priority encoder, since it requires less logic to implement but if not this become the major
disadvantage of simple encoder that is they can generate the wrong output when there is more
than one input present in a high state (logic state “1”) to rectify this problem a Priorityencoder is
used they act on the request of higher priority and the rest cases go in "don't care condition".
Octal to binary encoder
Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-to-8
decoder does. At any one time, only one input line has a value of 1.
BLOCK DIAGRAM:

TRUTH TABLE:
Program:
module enc(d,q);
input [7:0]d;
output [2:0]q;
wire [7:0]d;
reg [2:0]q;
always@(d)
begin
case(d)
8’b00000001 :q<=3’b000;
8’b00000010 :q<=3’b001;
8’b00000100 :q<=3’b010;
8’b00001000 :q<=3’b011;
8’b00010000 :q<=3’b100;
8’b00100000 :q<=3’b101;
8’b01000000 :q<=3’b110;
8’b10000000 :q<=3’b111;
default :q<=3’b000;
endcase
end
endmodule

Test Bench:

module enc_tb;
wire [2:0];
reg [7:0];
enc l1(d,q);
initial
begin
d=8’b00000001;
#10 d=8’b00000010;
#10 d=8’b00000100;
#10 d=8’b00001000;
#10 d=8’b00010000;
#10 d=8’b00100000;
#10 d=8’b01000000;
#10 d=8’b10000000;
#50 $stop;
end
endmodule

Output:

Result:
Hence, 8-to-3 encoder without priority using behavioral model of Verilog HDL program is
designed and simulated using Vivado 2014.4.
 B)WITH PRIORITY
Aim:
To design 8-to-3 encoder with priority using behavioral model of Verilog HDL program and to
perform simulation.
Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Theory:
A priority encoder provides n bits of binary coded output representing the position of the highest
order active input of 2ninputs. If two or more inputs are high at the same time, the input having
the highest priority will take precedence.
It's applications includes

 used to control interrupt requests by acting on the highest priority request.

 to encode the output of a flash analog to digital converter.

Block Diagram:

Truth Table:

INPUTS OUTPUTS
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
 0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1

Program:
module encwp(d,q);
input [7:0]d;
output [2:0]q;
wire [7:0]d;
reg [2:0]q;
always@(d)
begin
case(d)
8’b00000001 :q<=3’b000;
8’b0000001X :q<=3’b001;
8’b000001XX :q<=3’b010;
8’b00001XXX :q<=3’b011;
8’b0001XXXX :q<=3’b100;
8’b001XXXXX :q<=3’b101;
8’b01XXXXXX :q<=3’b110;
8’b1XXXXXXX :q<=3’b111;
default :q<=3’b000;
endcase
end
endmodule

Test Bench:

module enco_tb;
wire [2:0];
reg [7:0];
enco l1(d,q);
initial
begin
d=8’b00000001;
#10 d=8’b00000010;
#10 d=8’b00000100;
#10 d=8’b00001000;
#10 d=8’b00010010;
#10 d=8’b00100000;
#10 d=8’b01000100;
#10 d=8’b10010000;
#50 $stop;
 end
endmodule

Output:

Result:
Hence, 8-to-3 encoder with priority using behavioral model of Verilog HDL program is designed
and simulated using Vivado 2014.4.
 EXPERIMENT:6
DESIGN OF MULTIPLEXER AND DEMULTIPLEXER
A) Multiplexer
Aim:
To design 4 by 1 multiplexer using behavioral model of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:
Multiplexing is the generic term used to describe the operation of sending one or more analogue
or digital signals over a common transmission line at different times or speeds and as such, the
device we use to do just that is called a Multiplexer.
The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed to
switch one of several input lines through to a single common output line by the application of a
control signal. Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to the output.
Multiplexers, or MUX’s, can be either digital circuits made from high speed logic gates used to
switch digital or binary data or they can be analogue types using transistors, MOSFET’s or relays
to switch one of the voltage or current inputs through to a single output.
The most basic type of multiplexer device is that of a one-way rotary switch.
The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and data select
lines a, b is given as:
Q = abA + abB + abC + abD
In this example at any one instant in time only ONE of the four analogue switches is closed,
connecting only one of the input lines A to D to the single output at Q. As to which switch is
closed depends upon the addressing input code on lines “a” and “b“, so for this example to select
input B to the outputat Q, the binary input address would need to be “a” = logic “1” and “b” =
logic “0”.
Then we can show the selection of the data through the multiplexer as a function of the data
select bits.

BLOCK DIAGRAM:

TRUTH TABLE:
Program:
module mux4by1(s,d,y);
input [1:0]s;
input [3:0]d;
output y;
reg y;
always@(s)
begin
case({s[1],s[0]})
2’b00:y<=d[0];
2’b01:y<=d[1];
2’b10:y<=d[2];
2’b11:y<=d[3];
default:y<=d[0];
endcase
end
endmodule

Test Bench:
module mux4by1_tb;
wire y;
reg[1:0]s;
reg[3:0]d;
mux4by1 l1(s,d,y);
initial
begin
d=4’b1010;
s=2’b00;
#10 s=2’b01;
#10 s=2’b10;
#10 s=2’b11;
 #50 $stop;
end
endmodule

Output:

Result:
Hence, 4 by 1 multiplexer using behavioral model of Verilog HDL program is designed and
simulated using VIvado 2014.4.
 B) Demultiplexer
Aim:
To design 4 by 1 demultiplexer using behavioral model of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Theory:
The process of getting information from one input and transmitting the same over one of many
outputs is called Demultiplexing. If you recall the Multiplexer tutorial, there we discussed the
concept of Multiplexing. Demultiplexing is just the opposite of that.

A Demultiplexer is a combinational logic circuit that receives the information on a single input
line and transmits the same information over one of ‘n’ possible output lines.

In order to select a particular output, we have to use a set of Select Lines and the bit
combinations of these select lines control the selection of specific output line to be connected to
the input at a given instant. The below figure illustrates the basic idea of demultiplexer, in which
the switching of the input to any one of the four outputs is possible at a given instant.

Block Diagram:

Circuit Diagram:
Truth Table:

Program:
module demux14(a,s0,s1,y);
input a,s0,s1;
output [3;0]y;
reg [3:0]y;
always@(a,s0,s1)
begin
y[0]=((~s0)&(~s1)&(a));
y[1]=((~s0)&(s1)&(a));
y[2]=((s0)&(~s1)&(a));
y[3]=(s0&s1&a);
end
endmodule

Test Bench:
module demux14_tb:
reg a;s0;s1;
wire [3:0]y;
demux14 L1(a,s0,s1,y);
initial
begin
a=0;
s0=0;
s1=0;
a=0; s0=0; s1=0;
#10 a=0; s0=0; s1=1;
#10 a=0; s0=1; s1=0;
#10 a=0; s0=1; s1=1;
#10 a=1; s0=0; s1=0;
#10 a=1; s0=0; s1=1;
#10 a=1; s0=1; s1=0;
#10 a=1; s0=1; s1=1;
#50 $stop;
end
endmodule

Output:
Result:

Hence, 4 by 1 demultiplexer using behavioral model of Verilog HDL program is designed and
simulated using VIvado 2014.4.

EXPERIMENT:7
 DESIGN OF COMPARATOR

Aim:
To design 4 Bit comparator using data flow model of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:
Comparing two binary words for equality is a commonly used operation in computer systems
and device interfaces. A circuit that compares two binary words and indicates whether they are
equal is called a comparator.

Some comparators interpret their input words as signed or unsigned numbers and also indicate an
arithmetic relationship (greater or less than) between the words. These devices are often
called magnitude comparators.

A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central processing unit s (CPUs)
and microcontrollers (MCUs). Examples of digital comparator include the CMOS 4063 and 4585
and the TTL 7485 and 74682.
An XNOR gate is a basic comparator, because its output is "1" only if its two input bits are
equal.

Block Diagram:
Truth Table:

Inputs Outputs
a b a_lt_b a_gt_b a_eq_b
0110 1010 1 0 0
1010 0110 0 1 0
1010 1010 0 0 0

Program:

module comp(a,b,a_lt_b,a_gt_b,a_eq_b);
input [3:0]a;
input [3:0]b;
output a_lt_b,a_gt_b,a_eq_b;
wire a_lt_b,a_gt_b,a_eq_b;
assign a_lt_b=(a<b);
assign a_gt_b=(a>b);
assign a_eq_b=(a==b);
endmodule

Test Bench:

module comp_tb;
wire a_lt_b,a_gt_b,a_eq_b;
reg [3:0]a;
reg [3:0]b;
comp l1(a,b,a_lt_b,a_gt_b,a_eq_b);
initial
begin
a=4’b0110; b=4’b1010;
#10 a=4’b1010; b=4’b0110;
#10 a=4’b1010; b=4’b1010;
#50 $stop;
end
endmodule

Output:

Result:
Hence, 4 Bit comparator using data flow model of Verilog HDL program is designed and
simulated using Vivado 2014.4.

EXPERIMENT: 8
 DESIGN OF 4-BIT BINARY TO GRAY CODE CONVERTER
Aim:
To design 4-bit binary to gray converter using data flow model of Verilog HDL program and to
perform simulation.

Apparatus:
1.Personal Computer
2.Operating Systems-Linux
3.Xilinx 9.2i Vivado 2014.4

Theory:

The logical circuit which converts binary code to equivalent gray code is known as binary to
gray code converter. The gray code is a non weighted code. The successive gray code differs in
one bit position only that means it is a unit distance code. It is also referred as cyclic code. It is
not suitable for arithmetic operations. It is the most popular of the unit distance codes. It is also a
reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code about an axis
after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1 below the axis.

Block Diagram:

Truth Table:
 Binary input Gray output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
Program: 1 1 1 1 1 0 0 0

module btog(b,g);
input [3:0]b;
output [3:0]g;
wire [3;0]b,g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];
endmodule

Test Bench:

module btog_tb;
wire[3;0]g;
reg [3:0]b;
btog L1(b,g);
initial
begin
b=4’b0000;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#10 b=4’b0001;
#50 $stop;
end
endmodule

Output:

Result:
Hence, 4 bit binary to gray code converter using data flow model of Verilog HDL program is
designed and simulated using Vivado 2014.4.
 EXPERIMENT:9
DESIGN OF BCD TO EXCESS 3 CODE CONVERTER
Aim:
To design BCD to Excess 3 code converter using Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.
Theory:

The Excess-3 binary code is an example of a self-complementary BCD code. A self-

complementary binary code is a code which is always complimented in itself. By replacing the
bit 0 to 1 and 1 to 0 of a number, we find the 1's complement of the number. The sum of the 1'st
complement and the binary number of a decimal is equal to the binary number of decimal 9.

The process of converting BCD to Excess-3 is quite simple from other conversions. The Excess-
3 code can be calculated by adding 3, i.e., 0011 to each four-digit BCD code. Below is the truth
table for the conversion of BCD to Excess-3 code. In the below table, the variables A, B, C, and
D represent the bits of the binary numbers. The variable 'D' represents the LSB, and the variable
'A' represents the MSB. In the same way, the variables w, x, y, and z represent the bits of the
Excess-3 code. The variable 'z' represents the LSB, and the variable 'w' represents the MSB. The
'don't care conditions' is expressed by the variable 'X'.

Circuit diagram:

Truth Table:
Program:

module binary2ex3(b3,b2,b1,b0,e3,e2,e1,e0);
input b3,b2,b1,b0;
output e3,e2,e1,e0;
assign e3=b3|b0&b2|b2&b1;
assign e2=(~b1)&(~b0)&(b2)|(~b2)&(b0)|(~b2)&(b1);
assign e1=(~b1)&(~b0)|b1&b2;
assign e0=(~b1)&(~b0)|b1&(~b0);
endmodule

Test Bench:

module binary2ex3_tb;
reg b3, b2,b1,b0;
wire e3,e2,e1,e0;
binary2ex3 uut(b3,b2,b1,b0,e3,e2,e1,w0);
initial
begin

b3= 0; b2= 0; b1= 0; b0= 0;

#10 b3= 0; b2= 1; b1= 0; b0= 1;
#10 b3= 1; b2= 0; b1= 1; b0= 0;
#10 b3= 1; b2= 1; b1= 1; b0= 1;
#20 $stop;
end
endmodule

Output:

Result:

BCD to excess 3 code is designed using behavioral model of Verilog HDL program and simulated.
 EXPERIMENT:10
DESIGN OF FLIPFLOPS
A) SR FlipFlop

Aim:
To design SR flipflop using behavioral model of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:

An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the
inputs are turned off. This simple flip flop circuit has a set input (S) and a reset input (R). The
set input causes the output of 0 (top output) and 1 (bottom output). The reset input causes the
opposite to happen (top = 1, bottom =0). Once the outputs are established, the wiring of the
circuit is maintained until S or R go high, or power is turned off to the circuit.

This is a simple model of how one bit of RAM can be perpetuated. There are many issues not
shown here such as timing inputs and synchronization, but the simplicity of the circuit gives you
an idea of how RAM operates.

The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and consists of two gates.
The output of each gate is connected to one of the inputs of the other gate, giving a form of
positive feedback or ‘cross-coupling’.

51
BLOCK DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS
S R Q Q(not)
0 0 Q Q(not)
0 1 0 1
1 0 1 0
1 1 Z X

Program:

module srff(s,r,clk,rst,q,qnot);
input s,r,clk,rst;
output q,qnot;
reg q,qnot;
always@(posedgeclk)
begin
if(rst)
begin
q=0;
qnot=1;
end
else
begin
case({s,r})
2’b00:q=q;
2’b01:q=1’b0;
2’b10:q=1’b1;
52
2’b11:q=1’bz;
default:q=1’b0;
endcase
qnot=~q;
end
end
endmodule

Test Bench:

module srff_tb;
wire q,qnot;
reg s,r,clk,rst;
srff l1(s,r,clk,rst,q,qnot);
initial
begin
clk=0;
rst=1;
#6 rst=0;
s=1’b0;
r=1’b0;
#10 r=1’b1;
#5 s=1’b1; r=1’b0;
#10 r=1’b1;
#50 $stop;
end
always #5 clk=~clk;
endmodule

53
Output:

Result:
Hence, SR flipflop using behavioral model of Verilog HDL program is designed and simulated
using Vivado 2014.4.

54
 B) JK FlipFlop
Aim:
To design JK flipflop using behavioral model of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:

The JK Flip-flop is also called a programmable flip-flop because, using its inputs, J, K, S and R,
it can be made to mimic the action of any of the other flip-flop types.

As a starting point, assume that both J and K are at logic 1 and the outputs Q = 0 and Q = 1, this
will cause NAND 1 to be enabled, as it has logic 1 on two (J and Q) of its three inputs, requiring
only a logic 1 on its clock input to change its output state to logic 0. At the same time, NAND 2
is disabled, because it only has one of its inputs (K) at logic 1, its feedback input is at logic 0
because of the feedback from Q.

On the arrival of a clock pulse, the output of NAND 1 therefore becomes logic 0, and causes the
flip-flop to change state so that Q = 1 and Q = 0. This action enables NAND 2 and disables
NAND 1.

As this change of state at the outputs occurs however, there is a problem. If the clock pulse is
still high, or in its thold period when the flip-flop changes state, the output of NAND 2 will
instantly go to logic 0 and the flip-flop will reset back to its original state. This can then set up a
situation where the flip-flop will rapidly oscillate between its two states.

These problems caused by the output data ‘racing’ round the feedback lines from output to input
before the end of the clock pulse are known as RACE HAZARDS and of course must be
avoided. This can be done however, by using a more complex version of the circuit.

55
BLOCK DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS
J K Q Q(not)
0 0 Q Q(not)
0 1 0 1
1 0 1 0
1 1 Q(not) Q

Program:

module jkff(j,k,clk,rst,q,qnot);
input j,k,clk,rst;
output q,qnot;
reg q,qnot;
always@(posedgeclk)
begin
if(rst)
begin
q=0;
qnot=1;
end
else
begin
case({j,k})
2’b00:q=q;
2’b01:q=1’b0;
2’b10:q=1’b1;
2’b11:q=~q;
default:q=1’b0;
endcase

56
qnot=~q;
end
end
endmodule

Test Bench:

module jkff_tb;
wire q,qnot;
reg j,k,clk,rst;
jkff l1(j,k,clk,rst,q,qnot);
initial
begin
clk=0;
rst=1;
#6 rst=0;
j=1’b0;
k=1’b0;
#10 k=1’b1;
#5 j=1’b1; k=1’b0;
#10 k=1’b1;
#50 $stop;
end
always #5 clk=~clk;
endmodule

57
Output:

Result:
Hence, JK flipflop using behavioral model of Verilog HDL program is designed and simulated
using Vivado 2014.4.

58
 C) D FlipFlop
Aim:
To design JK flipflop using behavioral model of Verilog HDL program and to perform
simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:
The major drawback of the SR flip-flop (i.e. its indeterminate output and non-allowed logic
states) is overcome by the D type flip-flop. This flip-flop, together with its truth table and a
typical schematic circuit symbol, may be called a Data flip-flop because of its ability to ‘latch’
and remember data, or a Delay flip-flop because latching and remembering data can be used to
create a delay in the progress of that data through a circuit. To avoid the ambiguity in the title
therefore, it is usually known simply as the D Type. The simplest form of D Type flip-flop is
basically a high activated SR type with an additional inverter to ensure that the S and R inputs
cannot both be high or both low at the same time. This simple modification prevents both the
indeterminate and non-allowed states of the SR flip-flop. The S and R inputs are now replaced
by a single D input, and all D type flip-flops have a clock input.

As long as the clock input is low, changes at the D input make no difference to the outputs. The
truth table shows this as a ‘don’t care’ state (X). The basic D Type flip-flop shown is called a
level triggered D Type flip-flop because whether the D input is active or not depends on the logic
level of the clock input.

Provided that the CLK input is high (at logic 1), then whichever logic state is at D will appear at
output Q and (unlike the SR flip-flops) Q is always the inverse of Q.

If D = 1, then S must be 1 and R must be 0, therefore Q is SET to 1.

Alternatively,

If D = 0 then R must be 1 and S must be 0, causing Q to be reset to 0.

59
Block Diagram:

Truth Table:

INPUT OUTPUT
Clock
D Q Q’
LOW x 0 1
HIGH 0 0 1
HIGH 1 1 0

Program:

module dff(d,clk,rst,q);
input d,clk,rst;
output q;
reg q;
always@(posedgeclk)
begin
if(rst)
q=0;
else
q=d;
end
endmodule

60
Test Bench:

module dff_tb;
wire q;
reg clk,rst,d;
dff l1(d,clk,rst,q);
initial
begin
clk=0;
rst=1;
#10 rst=0;
#10 d=1;
#10 d=0;
#10 d=1;
#10 d=0;
#20 $stop;
end
always #5 clk=~clk;
endmodule

61
Output:

Result:
Hence, D flipflop using behavioral model of Verilog HDL program is designed and simulated
using Vivado 2014.4.

62
 D) T FLIPFLOP
Aim:
To design T flipflop using behavioral model of Verilog HDL program and to perform simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:
The “T” in “T flip-flop” stands for “toggle.” When you toggle a light switch, you are changing
from one state (on or off) to the other state (off or on). This is equivalent to what happens when
you provide a logic-high input to a T flip-flop: if the output is currently logic high, it changes to
logic low; if it’s currently logic low, it changes to logic high. A logic-low input causes the T flip-
flop to maintain its current output state. Thus, T flip-flop is a controlled Bi-stable latch where
the clock signal is the control signal. Thus, the output has two stable states based on the inputs

T flip-flops are handy when you need to reduce the frequency of a clock signal: If you keep the T
input at logic high and use the original clock signal as the flip-flop clock, the output will change
state once per clock period (assuming that the flip-flop is not sensitive to both clock edges).
Thus, the output clock will be half the frequency of the input clock.

Block Diagram:

63
Truth Table:

Program:

module tff(t,clk,rst,q);
input t,clk,rst;
output q;
reg q;
always@(posedgeclk)
begin
if(rst)
q=0;
elseif(t)
q=~q;
else
q=q;
end
endmodule

Test Bench:
module dff_tb;
wire q;
reg clk,rst,d;
dff l1(d,clk,rst,q);
initial
begin
clk=0;
rst=1;
#10 rst=0;
#10 d=1;
#10 d=0;
#10 d=1;

64
 #10 d=0;
#20 $stop;
end
always #5 clk=~clk;
endmodule

Output:

Result:
Hence, T flipflop using behavioral model of Verilog HDL program is designed and simulated
using Vivado 2014.4

65
 EXPERIMENT:11
DESIGN OF 4-BIT BINARY UP/DOWN COUNTER

Aim:
To design 4 bit binary UP/DOWN counter using behavioral model of Verilog HDL program and to
perform simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:

A 4-bit binary up/down counters counts sequence from 0000 to 1111 and 1111 to 0000. The
circuit operation can be explained as follows:

1. When the external input UP is equal to 1, no matter what the DOWN input is, the
circuit operates as an UP counter and counts sequence from 0000 to 1111.
2. When the external input DOWN is equal to 1 and UP is equal to 0, the circuit operates
as a DOWN counter and counts sequence from 1111 to 0000.
3. If both the inputs UP and DOWN are equal to 0, then the output of the flip-flop
remains unchanged.

Program:
module Counter( clk ,reset ,up,dout );
output [3:0] dout ;
reg [3:0] dout ;
input up;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin

if (reset)
dout <= 0;
else if (up)
dout <= dout + 1;

66
else
dout <=dout -1;
end
endmodule

Test Bench:
module Counter_tb;
reg clk,reset,up;
wire dout;
Counter uut (clk ,reset ,up,dout );
initial
begin
clk = 1;
reset = 1;
reset=0;t=1;
#100 up=1;
#200 up =0;
#200 $stop;
end
always #50 clk=~clk;
endmodule

Output:

Result:

4- bit binary counter using behavioral model of Verilog HDL program is designed and simulation is
performed.

67
 EXPERIMENT:12
DESIGN OF JOHNSON COUNTER

Aim:
To design Johnson counter using behavioral model of Verilog HDL program and to perform simulation.

Apparatus:
1. Personal Computer.
2. Operating systems-Linux.
3. Xilinx Vivado 2014.4.

Theory:
A Johnson counter is a digital circuit with a series of flip flops connected together in a
feedback manner. The circuit is special type of shift register where the complement output of the
last flip flop is fed back to the input of first flip flop. This is almost similar to ring counter with a
few extra advantages. When the circuit is reset all the flip flop outputs are made zero. For n-flip
flop Johnson counter we have a MOD-2n counter. That means the counter has 2n different states.

The circuit diagram for a 3 bit Johnson counter is shown below:

I have written a Verilog code for a 4-bit Johnson counter which has the following states:
0000 - 0001 - 0011 - 0111 - 1111 - 1110 - 1100 - 1000 - 0000 .... and so on

Program:

68
module johnson(clk,rst,count);
input clk,rst;
output [3:0]count;
reg [3:0]count_temp;
always@(posedge(clk0 or rst)
begin
if(rst==1’b1)
begin
count_temp=4’b0000;
end
else if(clk==1’b1)
begin
count_temp={count_temp[2:0],~count_temp[3]};
end
end
assign count=count_temp;
endmodule

Test Bench:

module johnson_tb;
reg clk,rst;
wire count;
johnson uut (clk,rst,count);

initial
begin

clk = 1; rst = 1;

#100; reset=0;
#500 $stop;
end

always #50 clk=~clk;

endmodule

Output:

69
Result:

Johnson counter using behavioral model of Verilog HDL program is designed and simulation is
performed.

70