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Content: What Is Verilog?

This document outlines the topics to be covered in a basic Verilog course, including data flow descriptions, behavioral descriptions, and structural descriptions. It also lists lab experiments for students to write HDL code for common logic gates, combinational circuits like decoders and multiplexers, and sequential circuits like a full adder. The course will have 30 students who will spend 30 hours learning basic Verilog topics and completing the listed lab experiments.

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0% found this document useful (0 votes)

130 views1 page

Content: What Is Verilog?

Uploaded by

sureshfm1

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Content

BASIC VERILOG TOPICS :

What is Verilog? Structure of Verilog Module, Operators, Data types, Types of Descriptions,
simulation and synthesis using Xilinx tool
Data Flow Descriptions :
Highlights of Data-Flow Descriptions, Structure of Data-Flow Description, Data Type Vectors.
Behavioral Descriptions :
Highlights of Behavioral Description, structure of HDL behavioral Description, The VHDL
variable Assignment Statement, sequential statements
Structural Descriptions :
Highlights of structural Description, Organization of the structural Descriptions, Binding,
Parameter statements.

Lab Experiments:
1. Write HDL code to realize all the logic gates
2. Write a HDL program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer.
3. Write a HDL code to describe the functions of a Full Adder
No of student
30

No of hours
30

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Content: What Is Verilog?

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BASIC VERILOG TOPICS :

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