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PD FP

The document summarizes 15 commands used for floorplanning and analysis in Innovus. Key commands include setDesignMode to define the process node, setLibraryUnit to set time and capacitance units, init_verilog to read verilog netlists, setMaxRouteLayer to set the routing layer limit, and saveDesign to save the design database. Other important commands are all_analysis_views to define analysis views, defIn/defOut to load and write DEF files, all_delay_corners to provide delay corners, setAnalysisMode to set analysis options, and check_timing to perform timing checks.

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253 views4 pages

PD FP

The document summarizes 15 commands used for floorplanning and analysis in Innovus. Key commands include setDesignMode to define the process node, setLibraryUnit to set time and capacitance units, init_verilog to read verilog netlists, setMaxRouteLayer to set the routing layer limit, and saveDesign to save the design database. Other important commands are all_analysis_views to define analysis views, defIn/defOut to load and write DEF files, all_delay_corners to provide delay corners, setAnalysisMode to set analysis options, and check_timing to perform timing checks.

Uploaded by

loknath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Floorplan Commands using innovus:

1.setDesignMode process <technologynode>

Description:Used to defin process node which your design has to close.

Ex:setDesignMode process 28

2.setLibraryUnit -time<units ,ps or ns> -cap<units,ff or pf>

Ex:setLibraryUnit time 1ps

3.init_verilog

Description:Specifies the gatelevel netlist to be read.

Ex:set init_verilog {a/b/c.v}

Simillary we can read mmcc files ,sdc etc(so not mentioning in the document)

4.setMaxRouteLayer <maximumlayer for your design>

Description:Specifies a routing layer limit for Trailroute.detailroute,pinsplacement


,standradcell placement, and CTS.

Ex:setMaxRouteLayer 7

5.saveDesign <filename.enc >

Description:Saves the database for all stages of the PD flow after importing.

Save Design <filename.enc> -def: saves a DEF file in addition saving place and
route files when you save the design.

Note:- use this command in the hieraichal flow where assemble design reads
only netlist and DEF file,not recommended for flat block.

saveDesign <filename.enc> -compress -verilog

-compress switch is used to compress the data which are big blocks,-nocompress
switch is used for small blocks.

-verilog switch writes out an ASCII verilog file.It is some times useful to save the
verilog to send to third party tools.

6.all_analysis_views

Description:Defines all the analysis views (views mean corners and mode in icc)
in the design.

Ex:all_analysis_views

Result:testmode_slowcorner funmode_fastcorner Turbomode_slowcorner


7.defIn <file.def>

Description:using this command we can load the saved floorplan def and I/o
placement def etc.

Ex: defIn floorplan.def

defIn nets :Reads the NETS section of the DEF file and ignores the remaining
sections

8.defOut

Description: writes the specified information to a def file.

Example: Load the design and defOut floorplan unplaced aaa.def

This command writes floorplan data and information on placed and unplaced
standarad cells.

By default defOut command writes out floorplan data and standarad cell placed
and unplaced information.

Ex:defIn file.sacndef

Ex:defOut test.def

Note: we have multiple options which are not mentioning in the document

9.defOutBysection

Description: writes information to specified section in a DEF file.

Example

defOutBysection noNets noComps -pins I/Ofile.def

writes out pin information with no component information and no net


information.

Note:There are so many other options , not mentioning in this document

10.all_delay_corners

Description:provides the objects of the corners (pvt conditions for our design)

Ex:all_delay_corners

Slow_125 fast_-40( these are the corneners for your design)

11.setAnalysisMode

Description: used to set aocv,clock gate chescks,case analysis to true or false

Ex:setAnalysisMode aocv true


12.check_timing

Description: Performs a variety of consistency and completeness checks on the


timing constraints specified for a design

Clock connectivity and data connectivity are checked to make sure clock or data
is propagated as expected.

Ex:check_timing -verbose > checktime.rpt

List out the

Clock_expected, ideal_clock_waveform no_input_delay data in the report and


provides the unconstrained pins.

Note: there are multiple optiona which are not mentioning in the document

13.checkPlace

Description:Checks Fixed and placed cell violations,adds violation markers to the


design.

Note:The utilization value reported by checkPlace and the density value reported
by timeDesign might differ,because checkPlace includes cellpadding while
timeDesign doesnot

14.checkFPlan

Description:Checks the quality of the floorplan to detect problems in the initial


stage itself

Ex:checkFPlan reportUtil

Reports utilization for the design

15.createPGPin

Description: creates a power/ground pin as per the specified coordinates of the


physical shape

Ex:createPGPin PWR net VDD

createPGPin GND net VSS

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