EDA TOOLS - Synopsys, cadence

APR EDA runs FUSION COMPILER, ICC2, innovus, encounter (its older version of innovus).
Floorplan – innovus (some product-based companies will prefer innovus because if we have 500 -600 macros it
will be easy to place those)
PNR both tools
get_cells/get_net/ get_pins (These commands are same for both the tools)
sdc commands both tool can use.

UPF(Synopsys) and CPF(cadence) are same

upf commands are made for Synopsys [Multi voltage designs] eg: create_power_domain
CPF: common power format
suppose if we do man create_power_domain in cadence tool? wont-work in cadence. But cadence tool
understands upf 1801 IEEE format.

dbget commands : data base information

data base information

use the command.

Select the
macro dbget selected.name

BUF*X*
dbget head.libcells.name BUF*X -innovus command it will give the list of buffers with different drive strengths
get_obj_cells BUF*X* -synopsys dbget top.inst.name #used to report all the instances name present in the
design.
dbget selected.pStatus #provide status of selcted object, fixed/placed/unplaced.

dbset Command
dbset selected.pStatus fixed #selected object will be fixed.

dbQuery #used to get information about in particular location how many std cells are there
edit commands:
editPowerVia #add via ad particular location
editPin #used to place pin/port
INNOVUS
innovus #command used to invoke innovus shell
win #to get gui window
win off #to close gui window
exit #to exit shell
saveDesign placement.enc #To save the block or design
Eg : saveDesign cts.enc.dat
restoreDesign placement.enc block_name #To restore the block or design
In innovus select one object, press q provides detail of that. name, status, orientation, hieght, width etc..
dbget selected.pgTerms.name
VSS VDD
dbget selected.pgTerms.net.name
VSS VDD
#term means pin/port
dbGet top.terms.name #command used to get port names.
set_visible_nets -all #command makes all nets visible.

unplaceAllBlock #command place all macros outside the core.

PD flow
import design **** sanity checks **** floorplan powerplan **** placement **** cts*** routing.

Import design:
set init_verilog ../../netlist.v

set lef_path../../all_design.lef
set tech_file../../file.tf
init_design ##the cmd used to read design using tcl variable.

sanity check:
checkDesign -netlist
check_library
check_instance_library_in_views
check_timing
Floorplan
* Gui: floorplan > specify floorplan > give height, width, spacing values and click okay.
Command: floorplan -d {w h left bottom right top} #to create floorplan using command
Command changeFloorplan -coreToLeft-coreToRight-coreToBottom-coreToT op # Use to modify I/O spacing.
command: changeFloorplan ###used to modify io spacing.
command: setObjFPlanBox Module block1 1 2 3 4 5 Module complete design ###used to create rectilinear
shape
Module ### if any complex Designs
Group ## if Any Voltage areas or voltage island avialble
command: defIn defin floorplan.def ##command used to read def file.
sdc file: #for both innovus and icc2 sdc commands are same.
create_cnstraint_mode
create_rc_corner
set_operation_condtions
source mmmc.tcl
viewdefinition.tcl
### all the active scenario for both setup n hold.
### vtg information
### how to save, free, restore
innovus> saveDesign import_design_done.enc innovus> exit
innovus> restoreDesign import_design.enc.dat block_name
cd./DB/import_design.enc.dat/ ###.enc.dat ---- every stage lib/lef/sdc/viewdefintiion/upetc...
innovus> restoreDesign import_design.enc.dat block_name -noTiming #restore design without timing mode,
helps to view, analyse deisgn but we cant save it.
innovus> freeDesign ##close current design in shell

Pin or port placement.

Gui ----edit ----pin editor -----select layer, side, spacing between each port
Command method
setPinConstraint #side, layer, spacing, reverse alternate, origin distance etc...
editPin -pin (pin1 pi2 pin3)
-side
 -edge
-start (040)
-end (40 40)
-layerH (METAL4 METAL6} -layerV (METALS METAL7}
-pattern reverse_alternate
-spacing
checkPinAssignment #to check ports are legal or illigual or unplaced.
illigual ###ports are not on track.
legalizePi-moveFixedPin -keepLayer -pin (pin1 pin2) #command legalalize the pin
selectIOPin
dbset selected.pStatus fixed
floorplan.def shape, die, core, io space, port placement.
dbget top.terms.name #command reports all the terms/port/pin name.
(pin1 pie2.....}
join [dbget top.terms.name ] \n #reports all the terms one after the next.
pin1
pin2
pin3
get_object_name [join [dbget top.terms.name] \n] > portname.rpt #command used to get all the port name in
one file.
###get_cell, get_plin, get_net, get_object_name |
###dbget commands
data base get information
----top
----head
----selected
innovus > dbget top. #press tab
#command used to get pointer to the top cell in the design
fplan hinst inst terms instTerms net wire via
: dbget top.terms. #press tab ex
dbget top.terms.name
llength [dbget top.terms.name]
#count of ports present in the design
dbget top.inst.name
#reports all the std. cells names insti
dbget top.inst.cell.name
#all reference name BUF1
dbget top.inst.cell.baseClass block
dbget top.inst.name #reports all the std. cells names inst1
dbget top.inst.cell.name #all reference name BUF1
dbget [dbget top.inst.cell.baseClass -p1 block].name
-p pinter to same location
-p1 pointer to one step back
-p2 -- pointer to two step back
-u uniqfy
dbget top.terms.layer.name -u METAL6 METAL7 METAL8
dbget top.inst.instterms.name
innvous > dbget head. ##point to the root of the cell
get_lib_cell "BUF #in icc2
dbget head.libcells.name *BUF*LVT
innovus > dbget selected.
#to get fro selected, select any object in ttol.
dbget selected.name
dbget selected.layer.name
dbget selected.layer.net.name

Floorplan area details

* dbget top.fplan.area #to get total area of the block
* dbget top.fplan.box #to get [urx ury llx lly]
* dbget top.fplan.boxes #to get rectilinear boxes
* dbget top.fplan.box_sizex #to get width
* dbget top.fplan.box_sizey #to get height

Macro Placement
hier1/hie/cell
hier2/hie/cell2
hier3/hie/cell3
selectInst hier1/hie/cell #14 #command used to select macro cells belong to same hier in gui.
hightlight -index 1
#command used to provide color
selectInst hier2/hie/cell #20 #command used to select macro cells belong to same hier in gui.
hightlight -index 2 #command used to provide color

placeInstance macro1 (0 0 1 2) #command used to place cell at particular location

dbget selected.orient
checkPlace #to see overlaps.
dbget top.pds.name #power domain name
* free_power_intent #remove if any power domain present
* read_power_intent -1801 upf.upf #read power domain
* commit_power_intent #commit into design
dbget top.pds.name
#report power domains name
dbget top.pds.pgTerms.name
dbget top.pds.pgNet.name
dbget top.pds.density
writeFPlanScript section Group -filname va_details.tcl # to write the script
writeFPlanSscript section blocks -filename macro.tcl
command: report PowerDomain # different power domains in the design information
innovus> help *power* #different power domains commands you can see using these command

How to create row, delete row, cut row

deleteRow -all
createRow -site H112-area 1 2 3 4
cuteRow
###why we do cut row over macro to avoid, because macro power routing starts from M3, M4,
based on requirement. if hard blockage creates, row we have to delete in that region.
selectInst *a/b/c/d * # what are cell present in the hierarchy. And used to highlight the cells in
the design
selectInst name1/name2*
press Z for zoom in , shift + z for zoom out
innovus> selectInsyByCellName BUF # to highlight reference name of particular cell in the
design
innovus> llength [dbget selected.name]
innovus> 2000
innovus> deselectAll
innovus> selectInsyByCellName INV
llength [dbget selected.name] #3000
innovus> 3000
port name clk_pll
selectInst clk_pll
selectInsyByCellName clk_pll #if you don’t know whether it is a pin or port (object not found
selectIOPin clk_pll
selectNet clk_pll_net
selectPin cell/A
select_obj name #if name of the object is pin/port/net/cell/inst -- then use this cmd
To create blockage in the design.
command: createPlaceBlockage -box-type -percentage hard/soft/partial
partial 60% in icc2 60% given, blocked percentage
partial 60% in innovus 60% given, allowed percentage
soft 60% -- in innovus, allow 60% buffer n inverters. # in innovus soft blockage will also come with some
percentage
command: deletePlace Blockage name deletePlaceBlockage -all
command: createRouteBlk name -box -layer deleteRouteBlk -all

halo/ keepout margin.

command : addHaloToBlock 1234-cell [dbget top.inst.cell.baseclass -p block]
: deleteHaloFromBlock -all

 addEndCap #to add endcap cells in the design

 verifyEndCap #to verify its placement setInstancePlacementStatus -name endcap status fixed #fix cells
before next stage.
 addWellTap -checkerboard -name
 verifyWellTap

Sanity Checks commands

 checkFPlan
 checkPlace
 checkDesign

Powerplan PG drc violations

clearDrc #to clear existing viol, in d violation browser.

 Verify_pg_short #to check any power, ground shorts present

 Verify_drc #to see drc
 verifyConnectivity #to check any opens
 editPowerVia #command used to add via
 Gui: rerouting:

Bind key
* Shift + R --- move/reshape/resize
* C-copy
* k - Ruler
* Shift + k --- delete ruler
* Shift + Y to create placement blockage
* Shift + B --- create routing blockage
* Shift + A --- edit wire
* Shift + X - cut wire by line
F2 window will come, save design
* Z --- zoom in
Shift + Z- zoom out
* f - fit
g-group #select cell n press g
* Shift + g – ungroup

Edit commands
* editSelect -net VDD
* editChangeNet -net VDD2
* editSelect -net name
* editChangeNet-layer_horizontal metal3 -layer_vertical metal4
* editSelect-layer METAL3
* editChangeStatus -to FIXED/ROUTED etc

Unplace Commands
unplaceAllBlocks
dbset [top.inst.cell.baseclass blocks -p].pstatus unplaced
* unplaceAllGuides #this command deletes all the bounds
* unplaceAllInsts I #unplace all standard cell.
innovus> help *edit*
innovus> help *unplace*
innovus> help *verify*

Placement
 region -- hard bound #same hier cell should sit, other cells are allowed.
 guide- soft bound #same hier cell can sit, other cells also allowed.
 fence exclusive bound #same hier cell should sit, other cells are not allowed.

deleteInstGroup name1_region
createInstGroup name1_region
addInstToInstGroup name1_region hier1/hier2/hier3/*
createRegion name1_region 1000 2000 1000 2000
select region In gui
dbget selected.members.name
dbget selected.density
dbget selected.name
Note: Region we can see only in floorplan view, we can’t see in placement view. Region’s density better to set
between 30 to 50.
Different views are available.

 Floorplan view
 Placement view

* setPlaceMode or set_place_mode
* Place_opt_design
Place_design [global place]
opt_design [detailed placement with timing optimization]
* reportCongestion
* report_timing-check_type setup
* checkPlace
* refine Place
place_design [places all the cells based on hierrachy, timing, congestion, withour fixing overlaps] optDesign -
preCTS [timing optimization, power optimization, drv optimization, area optimization etc...]
place_opt_design
checks after placements
1. checkPlace
overlaps/unplaced cells/ site is not correct / pin track alignments, base drc etc....
reason: improper netlist, less area, improper optimization
solution:
refinePlace
check with synthesis team density screen [partial blk]
cell padding/inst padding
module splitting [setPlaceMode -place_global_module_padding hire1/hire2/hie3*]

Placement gui
* Place > place standard cell
* Place > place spare cell
* Place > specify > cell padding
* Place > physical cell [end cap, tap, filler]
* Place > refine placement /
* Place > scan chain /
* Place> tie hi tie low /
* Place > ECO placement

Fixes
Gui: in view window - overlay [enable congestion hotspot/density in gui]
Congestion-density screen
Cell padding - specifyCellPad-cell-left 2-right
deleteCellPad *
o Inst padding -specifyInstPad name -left-right-top-bottom
deletelnstPad -all
* refinePlace
Check utilization
Check timing/fanout

Clock tree synthesis

Gui:
* setOptMode
* Set_ccopt_property
* setPlaceMode
* ccopt_design
* Report_timing-delay_told hold -max_paths 200 >
before_opt_hold_fix
* optDesign -postCTS -hold
* Report_timing-delay_told hold-max_paths 200 > after_opt_hold_fix

Clock tree reports

 Report_clock_tree_structure # clock tree structure buffers name
 Report_ccopt_clock_trees # summary of the clock tree about latency, skew
 Report_ccopt_skew_groups
 timeDesign-postCTS -outDir filename
 timeDesign-hold-postCTS -outDir filename
 Report_clock_timing
 Report_power or reportPower
 Report_area or reportArea

Upsize / down size, add buffer

* ecoChangeCell-inst CELL1/CELL2-cell BUF2X]
[before BUF1X --- BUF2X] - above command used for both, upsize/downsize, vt swap.
* ecoAddRepeater name -inst BUF -loc
* Any time while doing above commands need to setEcoMode, otherwise timing will update.
innovus> setECOMode -help
setECOMode -donttouch true-dontsize true -LECCheck false -update_timing false
ecoAddifepeater
setEcoMode -reset

Routing
* setNanoRoute Mode #signal routing timing driven , metal layer selection
* routeDesign
* optDesign-postRoute # fix the violation and any optimization issues will be fixed

Checks after routing

* Verify_drc
* Verify_Drc-check_short_only
* verifyConnectivity #opens
* ecoRoute
* ecoRoute -fix_drc

Physical cell commands

* addDecap-totCap 100-cell name_decap
* deleteDecap
* addFiller-cell fill-prefix
* deleteFiller
* addTieHiLo -cell tie -prefix

Gui PV related
Violation browser > select violations one by one, shows marker in guy
Verify > verify drc
Verify > verify connectivity
r-select object press r for move/resize/reshape
Shift + x for chopping
Shift + a - to edit wire, drw metal layer
Move the cell Moye
Auto command > ecoRoute -fix drc
#filler, metal filler run PV in seperate tool calibre /ICV
Pv anaylsis and fix
verify_drc
innovus> loadViolationReport -filename drc.out-type Calibre #tool creates violation markers.
verify_drc-check_short_only