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Bist Clock Gating

This document describes two scenarios for clocking a BIST system. In the first scenario, the BIST clock is distributed from the sequencer to the RAM and BIST wrapper. In the second scenario, a single clock gate is added in the sequencer to gate the BIST logic during functional mode, with the BIST clock now gated by a Bist_Enable signal and behavioral isolation clock gate.

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Nitish Kumar
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126 views1 page

Bist Clock Gating

This document describes two scenarios for clocking a BIST system. In the first scenario, the BIST clock is distributed from the sequencer to the RAM and BIST wrapper. In the second scenario, a single clock gate is added in the sequencer to gate the BIST logic during functional mode, with the BIST clock now gated by a Bist_Enable signal and behavioral isolation clock gate.

Uploaded by

Nitish Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Scenario 1: PRESENT BIST CLOCKING (As per my understanding)

clk

SEQUENCER

bistclk

bistclk

RAM

Functional RAM Clock

BIST WRAPPER

Scenario 2: Single clock gate added in sequencer to gate bist logic during functional mode.

TE
Behavioural ICG
Bist_Enable inserted in RTL

SEQUENCER
clk

bistclk

bistclk

RAM

Functional RAM Clock

BIST WRAPPER

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