2025-01-05

FPGA/ASIC Design with Verilog

Chapter 3: Sequential Logic Design -
Controllers
Duong Ngoc Phap, Ph.D
Faculty of Computer Engineering and Electronics
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com

January 5, 2025

3.1

Introduction
 Sequential circuit 1
• Output depends not just on present inputs (as in a
Combinational
1
0 F
combinational circuit), but on past sequence of inputs b digital circuit
 Stores bits, also known as having “state”
• Simple example: a circuit that counts up in binary
 In this chapter, we will: 1
a
• Design a new building block, a flip-flop, that stores one bit 0 Sequential ? F
b digital circuit
• Combine that block to build multi-bit storage – a register
si
• Describe the sequential behavior using a finite state ansis Must know
machine
sequence of
• Convert a finite state machine to a controller – a past inputs to
sequential circuit having a register and combinationalelogic know output
z

Note: Slides with animation are denoted with a small red "a" near the animated items
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3.2

Example Needing Bit Storage

Call Blue light
button Bit

 Flight attendant call button Cancel

button
Storage

• Press call: light turns on 1. Call button pressed – light turns on

Stays on after button released

Call Blue light
• Press cancel: light turns off button
Cancel
Bit
Storage
a

• Logic gate circuit to button

implement
Call this? Q 2. Call button released – light stays on
Cancel
a
Call Blue light
Doesn’t work. Q=1 when Call=1, but button Bit
doesn’t stay 1 when Call returns to 0 Cancel Storage
button
Need some form of “feedback” in the circuit
3. Cancel button pressed – light turns off

First attempt at Bit Storage

 We need some sort of feedback S Q
• Does circuit on the right do what we t
want?
No: Once Q becomes 1 (when S=1), Q
stays 1 forever – no value of S can bring Q
S 0back to 0 S 1 S 1 S 0
0Q S 1 0Q 1Q 1Q 1Q a
0 0 0 1 1
t t t t t

1
S
0
1
t
0
1
Q
0

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Bit Storage Using an SR Latch S (set) SR latch

 Does the circuit to the right, with cross-coupled NOR
gates, do what we want?
• Yes! How did someone come up with that circuit?
Maybe just trial and error, a bit of insight... Q

R (reset)
S=0 S=0 S=1 S=0
t t t t Recall…
1 1 0 0 0
0 0 1 1 1
0

1
1 1 0 0
0 Q 0 Q 1 Q 1 Q ecall
R
X ... 0

R=1 R=0 R=0 R=0

1
S
0
R1
0 a

t 1
0
1
Q
0

Example Using SR Latch for Bit Storage

 SR latch can serve as bit Call Blue light

storage in previous button

Cancel
Bit
Storage

example of flight- button

attendant call button

• Call=1 : sets Q to 1 C all
but ton
S

Q stays 1 even after Call=0

• Cancel=1 : resets Q to 0 Blue lig ht
Q
Cancel
but ton
R

 But, there’s a problem...

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Problem with SR Latch

 Problem
• If S=1 and R=1 simultaneously, we don’t know what value Q will
take
1
S=1 S=0 S=0 S
t t t 0
0 1 0 1
0 0 1 R
0
1
0 0 1 t
0 Q 1 Q 0 Q 0
1
R=1 R=0 R=0 Q
0

1
Q may oscillate. Then, because one path will be t
0
slightly longer than the other, Q will eventually 1
settle to 1 or 0 – but we don’t know which. Q
0

Problem with SR Latch

 Problem not just one of a user pressing two buttons at
same time
 Can also occur even if SR inputs come from a circuit that
supposedly never sets S=1 and R=1 at same time
• But does, due to different delays of different paths
1
Arbitrary
circuit SR latch X
S
X 0

1
Y
Q 0
Y R
1
S
The longer path from X to R than to S causes SR=11 for 0
short time – could be long enough to cause oscillation SR = 11
1
R
0

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Solution: Level-Sensitive SR Latch

 Add enable input “C” as shown Level-sensitive SR latch
• Only let S and R change when C=0 S
S1
 Enure circuit in front of SR never sets SR=11,
except briefly due to path delays
C
• Change C to 1 only after sufficient time for S and
R to be stable
Q
• When C becomes 1, the stable S and R value R
passes through the two AND gates to the SR R1
latch’s S1 R1 inputs.
S
Q’
Level-sensitive SR latch Though SR=11 briefly... C
1 Q
S S R
X S1 0
1 Level-sensitive
R
0
SR latch symbol
C 1 a
Clk C
0
Q 1
S1
R 0
R1
Y 1
R1 0

...S1R1 never = 11
9

Clock Signals for a Latch

 How do we know when it’s safe to set C=1?

• Most common solution –make C pulse up/down
 C=0: Safe to change X, Y Level-sensitive SR latch
 C=1: Must not change X, Y X
S
S1
 We’ll see how to ensure that later
• Clock signal -- Pulsing signal used to enable latches Clk
C

 Because it ticks like a clock Q

• Sequential circuit whose storage components all use R
R1
clock signals: synchronous circuit Y
 Most common type
 Asynchronous circuits – important topic, but left for
advanced course

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Clocks

 Clock period: time interval between pulses

• Above signal: period = 20 ns Freq Period

 Clock cycle: one such time interval 100 GHz 0.01 ns

10 GHz 0.1 ns
• Above signal shows 3.5 clock cycles 1 GHz 1 ns
 Clock frequency: 1/period 100 MHz 10 ns
10 MHz 100 ns
• Above signal: frequency = 1 / 20 ns = 50
MHz
 1 Hz = 1/s

11

Level-Sensitive D Latch
 SR latch requires careful D
D latch

design to ensure SR=11 never S

occurs C

 D latch relieves designer of R

Q

that burden 1
• InsertedD 0inverter ensures R
always opposite of S
D Q’
1
C C Q
0
1
S D latch symbol
0
1
R
0
1
Q
0

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Problem with Level-Sensitive D Latch

 D latch still has problem (as does SR latch)
• When C=1, through how many latches will a signal travel?
• Depends on for how long C=1
 Clk_A -- signal may travel through multiple latches
 Clk_B -- signal may travel through fewer latches
• Hard to pick C that is just the right length
 Can we design bit storage that only stores a value on the rising edge
of a clock signal?
rising edges
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 Clk

C1 C2 C3 C4

Clk

Clk_A Clk_B

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D Flip-Flop
 Flip-flop: Bit storage that stores on clock edge, not level rising edges
 One design -- master-servant Clk
• Two latches, output of first goes to input of second, master latch
has inverted clock signal
Note:
• So master loaded when C=0, then servant when C=1 Hundreds of
• When C changes from 0 to 1, master disabled, servant loaded with different flip-
flop designs
value that was at D just before C changed -- i.e., value at D during exist
rising edge of C
Clk
D flip-flop
D latch D latch D/Dm
D Q’
Dm Qm Ds Qs’
Cm
Q
Cm Cs Qs Qm/Ds
master servant Cs

Clk Qs

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D Flip-Flop

D Q’ D Q’ Internal design: Just

The triangle invert servant clock
means clock Q Q rather than master
input, edge
triggered
Symbol for rising-edge Symbol for falling-edge
triggered D flip-flop triggered D flip-flop

rising edges falling edges

Clk Clk

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D Flip-Flop
 Solves problem of not knowing through how many latches a signal travels when
C=1
• In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_B
• Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously --
then all four no longer pay attention to their input, until the next rising edge.
Doesn’t matter how long Clk is 1.

Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 T each
inside
fli w
pTwo olatches
l
-flop at inside
eachches
flip-flop

Clk

Clk_A Clk_B

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D Latch vs. D Flip-Flop

 Latch is level-sensitive: Stores D when C=1
 Flip-flop is edge triggered: Stores D when C changes
from 0 to 1
• Saying “level-sensitive latch,” or “edge-triggered flip-
flop,” is redundant
• Two types of flip-flops -- rising or falling edge triggered.
 Comparing behavior of latch and flip-flop:
Clk 1 2

D3 4 5 6

Q (D latch) 7 8

Q (D flip-flop) 9 10

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Flight-Attendant Call Button Using D Flip-

Flop
 D flip-flop will store bit Call Blue
Flight
button light
 Inputs are Call, Cancel, and present value of D attendant
call-button
Cancel
flip-flop, Q button system

 Truth table shown below

Preserve value: if Circuit derived from truth table,

Q=0, make D=0; if using Chapter 2 combinational
Q=1, make D=1 logic design process

Cancel -- make Call Call

but ton Blue
D=0 D Q’
light
Cancel
but ton
Cancel
Clk Q
Call -- make D=1 Q

Let’s give priority

to Call -- make
D=1

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Bit Storage Summary

SR latch Level-sensitive SR latch D latch D flip-flop
S (set) S D
S1 S D latch D latch
D Q’
Dm Qm Ds Qs’
C C Q
Cm Cs Qs
Q Q Q master servant
R
R1 R Clk
R (reset)

Feature: S=1 sets Q Feature: S and R only have Feature: SR can’t be 11 if D is Feature: Only loads D value
to 1, R=1 resets Q to effect when C=1. We can stable before and while C=1, present at rising clock edge, so
0. Problem: SR=11 design outside circuit so and will be 11 for only a brief values can’t propagate to other
yield undefined Q. SR=11 never happens when glitch even if D changes while flip-flops during same clock cycle.
C=1. Problem: avoiding C=1. Problem: C=1 too long Tradeoff: uses more gates
SR=11 can be a burden. propagates new values internally than D latch, and
through too many latches: requires more external gates than
too short may not enable a SR – but gate count is less of an
store. issue today.

 We considered increasingly better bit storage

until we arrived at the robust D flip-flop bit
storage
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Basic Register
 Typically, we store multi-bit items
• e.g., storing a 4-bit binary number
 Register: multiple flip-flops sharing clock signal
• From this point, we’ll use registers for bit storage
No need to think of latches or flip-flops
But now you know what’s inside a register
I3 I2 I1 I0
4-bit register
D D D D I3 I2 I1 I0
Q Q Q Q reg(4)
clk Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

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Example Using Registers: Temperature

Display
 Temperature history display
• Sensor outputs temperature as 5-bit binary number
• Timer pulses C every hour
• Record temperature on each pulse, display last three recorded values

Present 1 hour ago 2 hours ago

Display Display Display

x4 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
re x3
tu x2
ra TemperatureHistoryStorage
x1
sensor
empe x0
t
timer
C
(In practice, we would actually avoid connecting the timer output
C to a clock input, instead only connecting an oscillator output to a clock input.)

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Example Using Registers: Temperature

Display
 Use three 5-bit registers
a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
I4 Q4 I4 Q4 I4 Q4
x4
I3 Q3 I3 Q3 I3 Q3
x3
I2 Q2 I2 Q2 I2 Q2
x2
I1 Q1 I1 Q1 I1 Q1
x1
I0 Q0 I0 Q0 I0 Q0
x0
Ra Rb Rc
C
TemperatureHistoryStorage

x4...x0 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27

Ra 0 18 21 24 25 26 27

Rb 0 0 18 21 24 25 26

Rc 0 0 0 18 21 24 25

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3.3
Finite-State Machines (FSMs) and
Controllers
 Want sequential circuit with b Controller
laser
particular behavior over time x

clk

 Example: Laser timer patient

• Push button: x=1 for 3 clock

cycles
• How? Let’s try three flip-flops
b=1 gets stored in first D flip-
flop b
D Q D Q D Q
Then 2nd flip-flop on next
clk
cycle, then 3rd flip-flop on next
x
OR the three flip-flop outputs,
so x should be 1 for three cycles

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Need a Better Way to Design Sequential

Circuits
 Trial and error is not a good design method
• Will we be able to “guess” a circuit that works for other desired
behavior?
 How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10
cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input?
• And, a circuit built by guessing may have undesired behavior
 Laser timer: What if press button again while x=1? x then stays one another 3
cycles. Is that what we want?
 Combinational circuit design process had two important things
1. A formal way to describe desired circuit behavior
 Boolean equation, or truth table
2. A well-defined process to convert that behavior to a circuit
 We need those things for sequence circuit design

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Describing Behavior of Sequential Circuit:

FSM
 Finite-State Machine (FSM) Outputs: x
• A way to describe desired x=0 clk ^ x=1
behavior of sequential
circuit Off On
 Akin to Boolean equations for
combinational behavior clk ^
• List states, and transitions
among states Off On Off On Off On Off On
 Example: Make x change
toggle (0 to 1, or 1 to 0) every
clock cycle clk
cycle 1 cycle 2 cycle 3 cycle 4
 Two states: “Off” (x=0), and
“On” (x=1)
state Off On Off On
 Transition from Off to On, or
On to Off, on rising clock edge Outputs:
 Arrow with no starting state
points to initial state (when x
circuit first starts)

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FSM Example: 0,1,1,1,repeat

 Want 0, 1, 1, 1, 0, 1, 1, Outputs: x

1, ... x=0 clk ^ x=1 clk ^ x=1 clk ^ x=1

Off On1 On2 On3
• Each value for one clock
cycle clk ^

 Can describe as FSM

• Four states clk

• Transition on rising State Off On1 On2 On3 Off On1 On2 On3 Off

clock edge to next state Outputs:

x

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Extend FSM to Three-Cycles High Laser

Timer Inputs: b; Outputs: x
 Four states x=0
clk ^
 Wait in “Off” state while Off b’*clk^

b is 0 (b’) b*clk ^
 When b is 1 (and rising x=1 clk ^ x=1 clk ^ x=1

clock edge), transition to On1 On2 On3

On1
• Sets x=1 clk

• On next two clock edges, Inputs:

transition to On2, then b
On3, which also set x=1 State Off Off Off Off Off On1 On2 On3 Off

 So x=1 for three cycles Outputs:

after button pressed x

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FSM Simplification: Rising Clock Edges

Implicit Inputs: b; Outputs: x
 Showing rising clock on x=0
every transition: cluttered Off b’*clk^
clk ^

• Make implicit -- assume

every edge has rising clock, b*clk ^
x=1 clk ^ x=1 clk ^ x=1
even if not shown
On1 On2 On3
• What if we wanted a
transition without a rising
edge Inputs: b; Outputs: x
We don’t consider such x=0
asynchronous FSMs -- less Off b’
common, and advanced topic a

Only consider synchronous b

FSMs -- rising edge on every x=1 x=1 x=1
transition On1 On2 On3
Note: Transition with no associated condition thus
transistions to next state on next clock cycle

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FSM Definition
 FSM consists of Inputs: b; Outputs: x
• Set of states x=0

Ex: {Off, On1, On2, On3} Off b’

• Set of inputs, set of outputs b
Ex: Inputs: {x}, Outputs: {b} x=1 x=1 x=1
• Initial state On1 On2 On3
Ex: “Off”
• Set of transitions We often draw FSM graphically,
Describes next states known as state diagram
Ex: Has 5 transitions
Can also use table (state table), or
• Set of actions textual languages
Sets outputs while in states
Ex: x=0, x=1, x=1, and x=1

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FSM Example: Secure Car Key

 Many new car keys
include tiny computer
chip
• When car starts, car’s
computer (under engine
hood) requests identifier Inputs: a; Outputs: r
from key
• Key transmits identifier Wait
If not, computer shuts off r=0 a’
a
car
 FSM K1 K2 K3 K4

• Wait until computer r=1 r=1 r=0 r=1

requests ID (a=1)
• Transmit ID (in this case,
1101)

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FSM Example: Secure Car Key (cont.)

 Nice feature of FSM
Inputs: a; Outputs: r

Wait
• Can evaluate output r=0
a a’

behavior for different K1 K2 K3 K4

input sequence r=1 r=1 r=0 r=1

• Timing diagrams show

Q: Determine states and r value for
states and output given input waveform:
values for different
clk clk

input
Inputs
a
waveforms Inputs
a

State Wait Wait K1 K2 K3 K4 Wait Wait State Wait Wait K1 K2 K3 K4 Wait K1

Outputs Output a

r r

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FSM Example: Code Detector

 Unlock door (u=1) only when buttons s
Start
u
pressed in sequence: r
Red Code Door
• start, then red, blue, green, red a Green
g detector lock
b
 Input from each button: s, r, g, b Blue
a
• Also, output a indicates that some
colored button pressed
Inputs: s,r,g,b,a;
 FSM Wait
Outputs: u

• Wait for start (s=1) in “Wait” u=0 s s’ ar’ ab’ ag’ ar’
• Once started (“Start”) a

 If see red, go to “Red1” Start a’

 Then, if see blue, go to “Blue” u=0
ar
 Then, if see green, go to “Green” ab ag ar
Red1 Blue Green Red2
 Then, if see red, go to “Red2” a’ a’ a’
u=0 u=0 u=0 u=1
• In that state, open the door (u=1)
 Wrong button at any step, return Q: Can you trick this FSM to open the door,
to “Wait”, without opening door without knowing the code?
a
A: Yes, hold all buttons simultaneously

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Improve FSM for Code Detector

Inputs: s,r,g,b,a;
Outputs: u
Wait
u=0 s s’ ar’ ab’ ag’ ar’ a

Start
a’
u=0
ar
ab ag ar
Red1 Blue Green Red2
a’ a’ a’
u=0 u=0 u=0 u=1 Note: small problem still
remains; we’ll discuss later

 New transition conditions detect if wrong button pressed, returns to “Wait”

 FSM provides formal, concrete means to accurately define desired behavior

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Standard Controller Architecture

 How implement FSM as sequential circuit? Inputs: b; Outputs: x
• Use standard architecture
 State register -- to store the present state
x=0
 Combinational logic -- to compute outputs, and Off b’
next state
 For laser timer FSM
• 2-bit state register, can represent four states
b
• Input b, output x x=1 x=1 x=1
• Known as controller On1 On2 On3

outputs
outputs
inputs

b x FSM
FSM

FSM

Combinational n1
logic
inputs

outputs

I O
FSM

n0
FSM

Combinational
logic s1 s0
S clk State register
a m
m-bit m
clk
state register

N
General version
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3.4

Controller Design
 Five step controller design process

35

Controller Design: Laser Timer Example

 Step 1: Capture the FSM Inputs: b; Outputs: x
x=0
• Already done 00
Off b’

 Step 2: Create
a

b
x=1 x=1 x=1
architecture 01 On1 10 On2 11 On3

• 2-bit state register (for 4

states) outputs
outputs
inputs

b x FSM
FSM

FSM

• Input b, output x Combinational n1

logic
• Next state signals n1, n0 n0
s1 s0 a

 Step 3: Encode the states clk State register

• Any encoding with each
state unique will work

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Controller Design: Laser Timer Example

(cont)
 Step 4: Create state Inputs: b; Outputs: x
x=0
table 00
Off b’
a
b
x=1 x=1 x=1
01 On1 10 On2 11 On3

outputs
inputs
FSM
x

FSM
b
Combinational n1
logic
n0
s1 s0
clk State register

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Controller Design: Laser Timer Example

(cont)
 Step 5: Implement
outputs
inputs
FSM

x
FSM

combinational logic
Combinational n1
logic
n0
a
s1 s0
clk State register

x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0 = 1)

n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b

n1 = s1’s0 + s1s0’

n0 = s1’s0’b + s1s0’b’ + s1s0’b

n0 = s1’s0’b + s1s0’

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Controller Design: Laser Timer Example

(cont)
 Step 5: Implement FSM outputs b
Combinational Logic
x

outputs
combinational logic

inputs
FSM
x

FSM
b
Combinational
FSM inputs n1

(cont)
logic n1 a
n0
s1 s0
clk State register
n0

s1 s0

clk State register

x = s1 + s0
n1 = s1’s0 + s1s0’
n0 = s1’s0’b + s1s0’

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Understanding the Controller’s Behavior

x=0 x=0 x=0
00 b’ 00 b’ 00 b’
Off Off Off
b b b
x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1
01 On1 10 On2 11 On3 01 On1 10 On2 11 On3 01 On1 10 On2 11 On3

b x b x b x
0 0 0
0 0 0 1 0 0 1 1 1
0 0 1
n1 n1 n1
0 0 1
0 0 0 a
0 1 0
n0 n0 n0
0 1 0
0 0 0
s1 s0 s1 s0 s1 s0
clk clk clk
0 0 0 0 0 1
0 0 0 1 1 0

clk state=00 state=00 state=01

Inputs:
b
Outputs:
x

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Controller Example:
Button Press Synchronizer
cycle1 cycle2 cycle3 cycle4
clk
Inputs:
bi
Button press
bi bo
synchronizer Outputs:
controller
bo

 Want simple sequential circuit that converts button

press to single cycle duration, regardless of length of
time that button actually pressed
• We assumed such an ideal button press signal in earlier
example, like the button in the laser timer controller

41

Controller Example:
Button Press Synchronizer (cont)
outputs

bi bo
inputs

Step 2: Create architecture

FSM

FSM

FSM inputs: bi; FSM outputs: bo

Combinational
bi’ logic n1
bi
bi’ n0
A B C bi’ s1 s0 n1 = s1’s0bi + s1s0bi a
bi bi n0 = s1’s0’bi
bo=0 bo=1 bo=0 State register bo = s1’s0bi’ + s1’s0bi = s1s0
clk
Combinational logic
Step 1: FSM bo outputs
Combinational logic bi FSM
Inputs Outputs
s1 s0 bi n1 n0 bo n1
FSM inputs: bi; FSM outputs: bo 0 0 0 0 0 0
A
0 0 1 0 1 0
bi’ 0 1 0 0 0 1 n0
bi B
bi’ 0 1 1 1 0 1
00 bi 01 bi 10 bi’ 1 0 0 0 0 0 s1 s0
C
bo=0 bo=1 bo=0 1 0 1 1 0 0
State register
1 1 0 0 0 0 clk
Step 3: Encode states unused
1 1 1 0 0 0

Step 4: State table Step 5: Create

combinational circuit

Step 5: Create combinational circuit 42

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Controller Example: Sequence Generator

 Want generate sequence 0001, 0011, 1100, 1000, (repeat)
• Each value for one clock cycle
• Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”

w
Inputs: none; Outputs: w,x,y,z x Inputs: none; Outputs: w,x,y,z
wxyz=0001 wxyz=1000 y
Combinational z wxyz=0001 wxyz=1000
logic
A D n1 A D
n0 00 11
s1 s0
State register 01 10
B C clk B C
wxyz=0011 wxyz=1100 wxyz=0011 wxyz=1100
Step 1: Create FSM Step 2: Create architecture Step 3: Encode states
w
w = s1 x FSM outputs
x = s1s0’ y
y = s1’s0
z
z = s1’
a
n1 = s1 xor s0
n0 = s0’
n0 n1
s1 s0
clk State register
Step 4: Create state table
Step 5: Create combinational circuit
43

Controller Example: Secure Car Key

Inputs: a; Outputs: r
 (from earlier example)
Wait
r=0 a a’
Step 1

a
K1 K2 K3 K4
r=1 r=1 r=0 r=1
a r outputs
Combinational FSM
FSM
inputs n2
Step 2

logic
n1
n0

s2 s1 s0
clk State register

Inputs: a; Outputs: r

000
r=0 a’
a
Step 3

001 010 011 100

r=1 r=1 r=0 r=1
We’ll omit Step 5 Step 4

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Example: Seq. Circuit to FSM (Reverse

Engineering)
What does this y=s1’ a
A B

circuit do? z = s1s0’ states

x y FSMn1=(s1
outputsxor s0)x D C

n0=(s1’*s0’)x
z Outputs: y, z
FSM inputs
A B states
n1 yz=10 yz=10
with
D C outputs
n0 yz=00 yz=01

s1 s0
Inputs: x; Outputs: y, z
State register
clk x
x’ A B yz=10
yz=10 x’ x
Work backwards D x’ C yz=01

yz=00
Pick any state names you want x
states with
outputs and
transitions

45

Common Pitfalls Regarding Transition

Properties
a

 Only one condition b

should be true ab=11 –

next state? a

• For all transitions

leaving a state a
a
• Else, which one? a’b
 One condition must be a’b what if
ab=00?
true
a’b’
• For all transitions
leaving a state a

• Else, where go? a’b

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Verifying Correct Transition Properties

 Can verify using Boolean algebra Answer:
• Only one condition true: AND of each condition pair a= *(aa’b* a’) * b
(for transitions leaving a state) should equal 0  =0*b
proves pair can never simultaneously be true =0 a

• One condition true: OR of all conditions of transitions OK!

leaving a state) should equal 1  proves at least onea + a’b
condition must be true = a*(1+b) + a’b
= a + ab + a’b
• Example = a + (a+a’)b
a =a+b
Fails! Might not
be 1 (i.e., a=0,
a’b b=0)

Q: For shown transitions, prove whether:

* Only one condition true (AND of each pair is always 0)
* One condition true (OR of all transitions is always 1)

47

Evidence that Pitfall is Common

 Recall code detector FSM
• We “fixed” a problem with Wait
the transition conditions u=0 s s’ a

• Do the transitions obey the Start

two required transition u=0ar
a’
properties?
 Consider transitions of state ab ag ar
Red1 Blue Green Red2
Start, and the “only one true” a’ a’ a’
property u=0 u=0 u=0 u=1
ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g)
Intuitively: press red and blue
= (a*a’)r = 0*r = (a’*a)*(r’+b+g) = 0*(r’+b+g) buttons at same time: conditions
= (a*a)*r*(r’+b+g) = a*r*(r’+b+g) ar, and a(r’+b+g) will both be
=0 =0 = arr’+arb+arg true. Which one should be
taken?
= 0 + arb+arg
= arb + arg Q: How to solve? a

= ar(b+g) A: ar should be arb’g’

Fails! Means that two of Start’s (likewise for ab, ag, ar)
transitions could be true Note: As evidence the pitfall is common,
we admit the mistake was not intentional.
A reviewer of the book caught it.
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Simplifying Notations
 FSMs
a=0 a=0
b=1 b=0 a

c=0 c=1
• Assume unassigned clk a

output implicitly
assigned 0 b=1 c=1

 Sequential circuits
• Assume unconnected a

clock inputs connected to

same external clock

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3.5

More on Flip-Flops and Controllers

 Other flip-flop types
• SR flip-flop: like SR latch, but edge triggered
• JK flip-flop: like SR (SJ, RK)
But when JK=11, toggles
10, 01
• T flip-flop: JK with inputs tied together
Toggles on every rising clock edge
• Previously utilized to minimize logic outside flip-flop
Today, minimizing logic to such extent is not as
important
D flip-flops are thus by far the most common

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Non-Ideal Flip-Flop Behavior

 Can’t change flip-flop input too close to clock edge clk
• Setup time: time that D must be stable before edge
 Else, stable value not present at internal latch D
• Hold time: time that D must be held stable after edge
 Else, new value doesn’t have time to loop around and setup t ime
stabilize in internal latch
clk

D
Setup time violation
D latch C
D
S hold time
D 1
Q’ S
C 2
u
3 4
Q R
u R 7
Q’ Leads to oscillation!
Q 5 6

51

Metastability clk

 Violating setup/hold time can lead to bad

D
situation known as metastable state
• Metastable state: Any flip-flop state other
than stable 1 or 0 setup time
 Eventually settles to one or other, but we violation
don’t know which
• For internal circuits, we can make sure Q
observe setup time
• But what if input comes from external metastable
(asynchronous) source, e.g., button press? state
ai

 Partial solution
• Insert synchronizer flip-flop for asynchronous
input
 Special flip-flop with very small setup/hold a

time ai

• Doesn’t completely prevent metastability

synchronizer

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Metastability
 One flip-flop doesn’t completely solve problem
 How about adding more synchronizer flip-flops?
• Helps, but just decreases probability of metastability
 So how solve completely?
• Can’t! May be unsettling to new designers. But we just can’t guarantee a design
that won’t ever be metastable. We can just minimize the mean time between
failure (MTBF) -- a number often given along with a circuit

Probability of flip-flop being metastable is…

very
very very incredibly
low low low low
ai

synchronizers

53

Flip-Flop Set and Reset Inputs

 Some flip-flops have D Q’ D Q’ D
AR
Q’

additional inputs Q Q
Q
• Synchronous reset: clears AR AS
R

Q to 0 on next clock edge

• Synchronous set: sets Q cycle 1 cycle 2 cycle 3 cycle 4

to 1 on next clock edge

clk

• Asynchronous reset: clear D

Q to 0 immediately (not AR
dependent on clock edge)
Example timing diagram Q

shown
• Asynchronous set: set Q
to 1 immediately

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Initial State of a Controller

 All our FSMs had initial Inputs: x; Outputs: b
x=0
state Off b’
• But our sequential circuit b
designs did not x=1 x=1 x=1
On1 On2 On3
• Can accomplish using flip-
flops with reset/set inputs b x
Shown circuit initializes flip- Combinational
logic
n1
flops to 01 n0
• Designer must ensure reset State register
s1 s0

input is 1 during power up clk

of circuit D Q’ D Q’

By electronic circuit design R

Q
S
Q
reset

55

Glitching
 Glitch: Temporary values on outputs that appear soon after
input changes, before stable new output values
 Designer must determine whether glitching outputs may
pose a problem
• If so, may consider adding flip-flops to outputs
Delays output by one clock cycle, but may be OK

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Active Low Inputs

 We’ve assumed input

action occur when input is
D Q’
1
• Some inputs are instead Q
active when input is 0 -- R
“active low”
• Shown with inversion
bubble
• So to reset the shown flip-
flop, set R=0. Else, keep
R=1.

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Chapter Summary
 Sequential circuits
• Have state
 Created robust bit-storage device: D flip-flop
• Put several together to build register, which we used to hold state
 Defined FSM formal model to describe sequential behavior
• Using solid mathematical models -- Boolean equations for
combinational circuit, and FSMs for sequential circuits -- is very
important.
 Defined 5-step process to convert FSM to sequential circuit
• Controller
 So now we know how to build the class of sequential circuits
known as controllers

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Q&A

January 5, 2025

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