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Experiment 10: Multiplexers: Mr. Mohamed El-Saied

This document describes an experiment on multiplexers. The objectives are to realize a 2-to-1 multiplexer using logic gates and an 8-to-1 multiplexer using an IC 4051 chip. The theory section defines what a multiplexer is and describes how a 2-to-1 and 8-to-1 multiplexer works. It provides truth tables and logic diagrams. The components required are listed. Part A describes implementing the 2-to-1 and 8-to-1 multiplexers in practice. Part B provides exercises for students to implement an 8-to-1 multiplexer with logic gates, use multiplexers to design a full adder, and implement a function using a multiplexer.

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Estéfano Gómez
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308 views4 pages

Experiment 10: Multiplexers: Mr. Mohamed El-Saied

This document describes an experiment on multiplexers. The objectives are to realize a 2-to-1 multiplexer using logic gates and an 8-to-1 multiplexer using an IC 4051 chip. The theory section defines what a multiplexer is and describes how a 2-to-1 and 8-to-1 multiplexer works. It provides truth tables and logic diagrams. The components required are listed. Part A describes implementing the 2-to-1 and 8-to-1 multiplexers in practice. Part B provides exercises for students to implement an 8-to-1 multiplexer with logic gates, use multiplexers to design a full adder, and implement a function using a multiplexer.

Uploaded by

Estéfano Gómez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module: Logic Design Lab

Name: ……………………….........................
University no:……………………..
Group no: ……………
Lab Partner Name: Mr. Mohamed El-Saied
Experiment 10: Multiplexers

Objective: To realize and implement


 Two-to-one-line multiplexer using logic gates by on a breadboard.
 Eight-to-one-line Multiplexer Using IC 4051.
Components Required:
 Mini Digital Training and Digital Electronic Sets.
 IC 7404, IC 7408, IC 7432, IC 74153, IC 4051.
Theory:
A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. The selection of a particular input line is contro1led by a set of selection lines.
Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
selected.
Two-to-One-line Multiplexer (2x1 MUX): A two-to-one-line multiplexer connects one of two 1-bit sources
to a common destination, as shown in Fig 1. The circuit has two data input lines, one output line, and one
selection line S.
When S = 0, the upper AND gate is enabled and I0 has a path to the output.
When S = 1, the lower AND gate is enabled and I1 has a path to the output.
Multiplexer is often labeled as MUX in the block diagram

Truth table for 2x1 MUX

S Y

0 I0
1 I1

Y = S’I0 + SI1

Fig1: Logic diagram of 2x1 MUX

1
Eight-to-one-line multiplexer (8x1 MUX): An eight-to-one-line multiplexer is a combinational circuit where
one of the eight inputs is connected to one output. D0, D1, D2… D7 are the eight inputs. There are three select
lines S0, S1, and S2 to select input.
Truth table for 8-1 multiplexer:

S2 S1 S0 Y

0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

Y = S2’S1’S0’ D0 + S2’S1’S0 D1 + S2’S1S0’ D2 + S2’S1S0 D3 + S2S1’S0’ D4 + S2S1’S0 D5 + S2S1S0’ D6 + S2S1S0 D7

Each of the eight inputs, D0 through D7 is applied to one input of an AND gate. Selection lines S0, S1, and S2
are decoded to select a particular AND gate.

Fig: Logic diagram of 8-1 multiplexer

2
IC 4051 (Eight-to-One-line Mu1tiplexer):
IC 4051 is single 8-channel analog multiplexers/demultiplexers for application as digitally–controlled analog
switches. It contains 8 bidirectional and digitally controlled analog switches. A built-in level shifting is
included to allow an input range up to ±6 V (peak) for an analog signal with digital control signal of 0 to 6 V.
The VEE supply pin is provided for analog input signals. It has an inhibit (INH) input terminal to disable all
the switches when is at high level. For operation as a digital multiplexer/demultiplexer, VEE is connected to
GND. A, B and C control inputs select one channel out of eight

Pin diagram of IC 4051:

Pin description of IC 4051:

Part A: Practice Procedure:


1. Implement 2x1 multiplexer using logic gates and breadboard, and verify the truth table.
2. Implement 8x1 multiplexer using IC 4051.

Conclusions: Thus Multiplexer is studied.

3
Module: Logic Design Lab
Name: ...................................
University no:………………………..
Group no: …………………………….
Lab Partner Name: Mr. Mohamed El-Saied

Part B: Lab. Exercise:


Students are directed to do the following exercise.

Q1. Implement 8x1 line multiplexer using basic logic gates.


Draw the truth table of the circuit.
Write the Boolean expression for the output function.

Q2. Show how to implement full-adder circuit using two 4x1 line multiplexer.
Hint: S (x,y,z) = Σm(1,2,4,7), C (x,y,z) = Σm(3,5,6,7)

Q3. Implement the function F (A, B, C, D) = Σ (1, 3, 4, 11, 12, 13, 14, 15) using a multiplexer.

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