D FLIP-FLOP

VHDL CODE
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_ff is

Port ( d : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC:=’0’);

end d_ff;

architecture Behavioral of d_ff is

begin

process(d,clk,q)

begin

if(rising_edge(clk))then rising_edge(clk) or clk=’1’ and clk’event

q<=d;

end if;

end process;

end Behavioral;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY d_ff_tb_vhd IS

END d_ff_tb_vhd;

ARCHITECTURE behavior OF d_ff_tb_vhd IS

1
COMPONENT d_ff

PORT( d : IN std_logic; clk : IN std_logic; q : INOUT std_logic );

END COMPONENT;

--Inputs

SIGNAL d : std_logic := '0';

SIGNAL clk : std_logic := '1';

--BiDirs

SIGNAL q : std_logic;

BEGIN

uut: d_ff PORT MAP(

d => d,

clk => clk,

q => q

);

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

wait for 80 ns;

d<='1';

wait for 80 ns;

d<='0';

wait for 80 ns;

d<='1';

wait for 80 ns;

d<='0';

wait;

2
END PROCESS;

END;

SR FLIP-FLOP
VHDL CODE
entity SR_FF is

Port ( S : in STD_LOGIC; R : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC);

end SR_FF;

architecture Behavioral of SR_FF is

signal qtmp:std_logic:='0';

begin

process(s,r,clk)

begin

if(rising_edge(clk))then

if(s='0' and r='0')then

qtmp<=qtmp;

elsif(s='1' and r='0')then

qtmp<='1';

elsif(s='0' and r='1')then

qtmp<='0';

else

qtmp<='Z';

3
end if;

end if;

end process;

q<=qtmp;

end Behavioral;

(OR)

entity SR_FF is

Port ( CLK,S,R : in STD_LOGIC; Q : inout STD_LOGIC:=’0’);

end SR_FF;

architecture Behavioral of SR_FF is

begin

process(s,r,clk)

begin

if(rising_edge(clk))then

if(s='0' and r='0')then

Q<=Q;

elsif(s='1' and r='0')then

Q<='1';

elsif(s='0' and r='1')then

Q<='0';

else

Q<='Z';

end if;

end if;

end process;

end Behavioral;

(OR)

entity SR_FF is

4
 Port ( CLK,S,R : in STD_LOGIC; Q : inout STD_LOGIC:=’0’);

end SR_FF;

architecture Behavioral of SR_FF is

begin

process(s,r,clk)

begin

if(rising_edge(clk))then

q<=s and ((not r) and q);

end if;

end process;

end Behavioral;

TEST BENCH
ENTITY sr_ff_tb_vhd IS

END sr_ff_tb_vhd;

ARCHITECTURE behavior OF sr_ff_tb_vhd IS

COMPONENT SR_FF

PORT( S : IN std_logic; R : IN std_logic; CLK : IN std_logic; Q : OUT std_logic );

END COMPONENT;

--Inputs

SIGNAL S : std_logic := '0';

SIGNAL R : std_logic := '0';

SIGNAL CLK : std_logic := '1';

--Outputs

SIGNAL Q : std_logic;

BEGIN

uut: SR_FF PORT MAP(

S => S,

R => R,

5
 CLK => CLK,

Q => Q

);

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

wait for 80 ns;

s<='0';r<='1';

wait for 80 ns;

s<='1';r<='0';

wait for 80 ns;

s<='0';r<='0';

wait for 80 ns;

s<='0';r<='1';

wait;

END PROCESS;

END;

JK FLIP-FLOP
VHDL CODE

6
entity JK_FF is

Port ( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC);

end JK_FF;

architecture Behavioral of JK_FF is

signal qtmp:std_logic:='0';

begin

process(j,k,clk)

begin

if(rising_edge(clk))then

if(j='0' and k='0')then

qtmp<=qtmp;

elsif(j='1' and k='0')then

qtmp<='1';

elsif(j='0' and k='1')then

qtmp<='0';

else

qtmp<=not qtmp;

end if;

end if;

end process;

q<=qtmp;

end Behavioral;

TEST BENCH
ENTITY jk_ff_tb_vhd IS

END jk_ff_tb_vhd;

ARCHITECTURE behavior OF jk_ff_tb_vhd IS

COMPONENT JK_FF

PORT( j : IN std_logic; k : IN std_logic;

7
 clk : IN std_logic; q : OUT std_logic );

END COMPONENT;

SIGNAL j : std_logic := '0';

SIGNAL k : std_logic := '0';

SIGNAL clk : std_logic := '1';

SIGNAL q : std_logic;

BEGIN

uut: JK_FF PORT MAP(

j => j,

k => k,

clk => clk,

q => q );

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

wait for 80 ns;

j<='0'; k<='1';

wait for 80 ns;

j<='1';k<='1';

wait for 80 ns;

j<='1';k<='0';

wait for 80 ns;

j<='0';k<='0';

wait for 80 ns;

j<='0';k<='1';

wait;

END PROCESS;

END;

8
 T FLIP-FLOP
VHDL CODE
entity T_FF is

Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC );

end T_FF;

architecture Behavioral of T_FF is

signal qtmp:std_logic:='0';

begin

process(t,clk)

begin

if(rising_edge(clk))then

if(t='0')then

qtmp<=qtmp;

else

qtmp<=not qtmp;

end if;

end if;

end process;

q<=qtmp;

end Behavioral;

9
TEST BENCH
ENTITY t_ff_tb_vhd IS

END t_ff_tb_vhd;

ARCHITECTURE behavior OF t_ff_tb_vhd IS

COMPONENT T_FF

PORT( t : IN std_logic; clk : IN std_logic; q : OUT std_logic );

END COMPONENT;

SIGNAL t : std_logic := '0';

SIGNAL clk : std_logic := '1';

SIGNAL q : std_logic;

BEGIN

uut: T_FF PORT MAP(

t => t,

clk => clk,

q => q

);

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

wait for 80 ns;

t<='1';

wait for 80 ns;

t<='0';

wait for 80 ns;

t<='1';

wait for 80 ns;

t<='0';

wait;

10
END PROCESS;

END;

T FLIP-FLOP VHDL CODE (considering q as inout port)

entity T_FF is

Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q :in out STD_LOGIC :=’0’ );

end T_FF;

architecture Behavioral of T_FF is

begin

process(t,clk)

begin

if(rising_edge(clk))then

if(t='0')then

q<=q;

else

q<= not q;

end if;

end if;

end process;

end Behavioral;

T FLIP-FLOP VHDL CODE (considering qtmp as variable)

entity T_FF is

Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC );

11
end T_FF;

architecture Behavioral of T_FF is

begin

process(t,clk)

variable qtmp:std_logic:='0';

begin

if(rising_edge(clk))then

if(t='0')then

qtmp:=qtmp;

else

qtmp:=not qtmp;

end if;

end if;

q<=qtmp; (variable is valid only within process)

end process;

end Behavioral;

NOTE: Draw logic symbol, logic ckt, truth table for D, SR, JK, T flip-flops.

3-BIT SYNCHRONOUS BINARY UP COUNTER

VHDL CODE

entity SYN3_UP is

Port ( clk : in STD_LOGIC; rst : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (2 downto 0) );

end SYN3_UP;

architecture Behavioral of SYN3_UP is

signal qtmp:STD_LOGIC_VECTOR (2 downto 0);

12
begin

process(clk,rst)

begin

if(rst='1')then

qtmp<="000";

else

if(falling_edge(clk))then falling_edge(clk) or clk=’0’ and clk’event

qtmp<=qtmp+1;

end if;

end if;

end process;

q<=qtmp;

end Behavioral;

TEST BENCH

ENTITY syn3_up_tb_vhd IS

END syn3_up_tb_vhd;

ARCHITECTURE behavior OF syn3_up_tb_vhd IS

COMPONENT SYN3_UP

PORT( clk : IN std_logic; rst : IN std_logic;

q : OUT std_logic_vector(2 downto 0) );

END COMPONENT;

SIGNAL clk : std_logic := '1';

SIGNAL rst : std_logic := '1'; --INITIAL VALUE ‘1’

SIGNAL q : std_logic_vector(2 downto 0);

BEGIN

uut: SYN3_UP PORT MAP(

13
 clk => clk,

rst => rst,

q => q

);

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

wait for 30 ns;

rst<='0';

wait;

END PROCESS;

END;

VHDL CODE (considering qtmp as variable)

entity SYN3_UP is

Port ( clk : in STD_LOGIC; rst : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (2 downto 0) );

end SYN3_UP;

architecture Behavioral of SYN3_UP is

begin

14
process(clk,rst)

variable qtmp:STD_LOGIC_VECTOR (2 downto 0);

begin

if(rst='1')then

qtmp:="000";

else

if(falling_edge(clk))then

qtmp:=qtmp+1;

end if;

end if;

q<=qtmp;

end process;

end Behavioral;

4-BIT SYNCHRONOUS DOWN COUNTER

VHDL CODE

entity SYN4_DOWN is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (3 downto 0));

end SYN4_DOWN;

architecture Behavioral of SYN4_DOWN is

SIGNAL qtmp:STD_LOGIC_VECTOR (3 downto 0);

begin

process(clk,rst)

begin

if(rst='1')then

15
qtmp<="0000";

else

if(falling_edge(clk))then

qtmp<=qtmp-1;

end if;

end if;

end process;

q<=qtmp;

end Behavioral;

TEST BENCH

Refer 3-bit synchronous binary up counter test bench (change q : (3 downto 0) )

DECADE / BCD / MOD-10 SYNCHRONOUS COUNTER

VHDL CODE

entity BCD_SYN is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (3 downto 0));

end BCD_SYN;

16
architecture Behavioral of BCD_SYN is

SIGNAL qtmp:STD_LOGIC_VECTOR (3 downto 0);

begin

process(clk,rst)

begin

if(rst='1')then

qtmp<="0000";

else

if(falling_edge(clk))then

if(qtmp<9)then

qtmp<=qtmp+1;

else

qtmp<="0000";

end if;

end if;

end if;

end process;

q<=qtmp;

end Behavioral;

TEST BENCH

Refer 3-bit synchronous binary up counter test bench (change q : (3 downto 0) )

17
 3-BIT SYNCHRONOUS UP/DOWN COUNTER
VHDL CODE

entity SYN3_UP_DOWN is

Port ( clk : in STD_LOGIC; rst : in STD_LOGIC;

up_downbar : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0));

end SYN3_UP_DOWN;

architecture Behavioral of SYN3_UP_DOWN is

signal qtmp:std_logic_vector (2 downto 0);

begin

process(clk,rst,up_downbar)

begin

if(rst='1')then

qtmp<="000";

else

if(falling_edge(clk))then

if(up_downbar='1')then

qtmp<=qtmp+1;

else

qtmp<=qtmp-1;

end if;

18
end if;

end if;

end process;

q<=qtmp;

end Behavioral;

TEST BENCH

ENTITY syn3_up_down_tb_vhd IS

END syn3_up_down_tb_vhd;

ARCHITECTURE behavior OF syn3_up_down_tb_vhd IS

COMPONENT SYN3_UP_DOWN

PORT(clk : IN std_logic; rst : IN std_logic; up_downbar : IN std_logic;

q : OUT std_logic_vector(2 downto 0) );

END COMPONENT;

SIGNAL clk : std_logic := '1';

SIGNAL rst : std_logic := '1';

SIGNAL up_downbar : std_logic := '0';

SIGNAL q : std_logic_vector(2 downto 0);

BEGIN

uut: SYN3_UP_DOWN PORT MAP(

clk => clk, rst => rst,

up_downbar => up_downbar,

q => q

);

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

19
wait for 30 ns;

rst<='0';

wait for 310 ns;

up_downbar<='1';

wait;

END PROCESS;

END;

3-BIT ASYNCHRONOUS UP COUNTER

VHDL CODE (component)

entity T_FF is

Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC :=’0’ );

end T_FF;

architecture Behavioral of T_FF is

begin

process(t,clk)

begin

if(falling_edge(clk))then

if(t='0')then

q<=q;

20
else

q<=not q;

end if;

end if;

end process;

end Behavioral; (no need to write test bench for component)

VHDL CODE (counter)

entity ASYN3_UP is

Port ( t : in STD_LOGIC_VECTOR (2 downto 0);

clk : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (2 downto 0):="000");

end ASYN3_UP;

architecture structural of ASYN3_UP is

component t_ff

Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC:=’0’ );

end component;

begin

u1:t_ff port map(t(0),clk,q(0));

u2:t_ff port map(t(1),q(0),q(1));

u3:t_ff port map(t(2),q(1),q(2));

end structural;

TEST BENCH(counter)

ENTITY asyn3_up_tb_vhd IS

END asyn3_up_tb_vhd;

ARCHITECTURE behavior OF asyn3_up_tb_vhd IS

COMPONENT ASYN3_UP

21
PORT(t : in STD_LOGIC_VECTOR (2 downto 0);

clk : IN std_logic; q : INOUT std_logic_vector(2 downto 0) );

END COMPONENT;

SIGNAL t : std_logic_vector(2 downto 0) := “111”; (always t = ‘1’)

SIGNAL clk : std_logic := '1';

SIGNAL q : std_logic_vector(2 downto 0);

BEGIN

uut: ASYN3_UP PORT MAP( t => t,

clk => clk,

q => q

);

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

wait;

END PROCESS;

END;

NOTE: for all counters draw state diagram and logic diagram

(use negative edge triggered flip-flops for counters)

22
 FREQUENCY DIVIDER(DIVIDE BY 8)
VHDL CODE

entity frequency_divider_by8 is

port(clk : in STD_LOGIC; out_clk : out STD_LOGIC );

end frequency_divider_by8;

architecture behavioral of frequency_divider_by8 is

SIGNAL q : std_logic_vector (2 downto 0) := "000";

begin

process (clk)

begin

if (falling_edge (clk)) then

q<= q + 1;

end if;

out_clk <= q(2);

end process ;

end behavioral;

TEST BENCH

ENTITY frequency_divide_by8_tb_vhd IS

END frequency_divide_by8_tb_vhd;

ARCHITECTURE behavior OF frequency_divide_by8_tb_vhd IS

COMPONENT frequency_divider_by8

PORT(clk : IN std_logic; out_clk : OUT std_logic );

END COMPONENT;

SIGNAL clk : std_logic := '1';

SIGNAL out_clk : std_logic;

BEGIN

23
uut: frequency_divider_by8 PORT MAP(clk => clk, out_clk => out_clk );

clk<=not clk after 25 ns;

tb : PROCESS

BEGIN

wait;

END PROCESS; END;

FREQUENCY DIVIDER(DIVIDE BY 4)
VHDL CODE

entity frequency_divider_by4 is

port(clk : in STD_LOGIC; out_clk : out STD_LOGIC );

end frequency_divider_by4;

architecture behavioral of frequency_divider_by4 is

SIGNAL q : std_logic_vector (1 downto 0) := "00";

begin

process (clk)

begin

if (falling_edge (clk)) then

q<= q + 1;

end if;

out_clk <= q(1);

end process ;

end behavioral;

24
NOTE: for divide by 8 freq divider draw 3-bit asynchronous counter logic diag.

for divide by 4 freq divider draw 2-bit asynchronous counter logic diag.

8-BIT SISO RIGHT SHIFT REGISTER

VHDL CODE
entity SISO_RIGHT_8bit is
Port ( clk : in STD_LOGIC; serin : in STD_LOGIC; serout : out STD_LOGIC);
end SISO_RIGHT_8bit;
architecture Behavioral of SISO_RIGHT_8bit is
signal tmp:std_logic_vector(7 downto 0):="11100010";
begin
process(clk)
begin
if(rising_edge(clk))then
for i in 0 to 6 loop
tmp(i)<=tmp(i+1);
end loop;
tmp(7)<=serin;
end if;
end process;

25
serout<=tmp(0);
end Behavioral;
TEST BENCH
ENTITY SISO_RIGHT_8bit_tb_vhd IS
END SISO_RIGHT_8bit_tb_vhd;
ARCHITECTURE behavior OF SISO_RIGHT_8bit_tb_vhd IS
COMPONENT SISO_RIGHT_8bit
PORT(clk : IN std_logic; serin : IN std_logic; serout : OUT std_logic );
END COMPONENT;
SIGNAL clk : std_logic := '1';
SIGNAL serin : std_logic := '0';
SIGNAL serout : std_logic;
BEGIN
uut: SISO_RIGHT_8bit PORT MAP(clk => clk, serin => serin, serout => serout);
clk<=not clk after 25 ns;
tb : PROCESS
BEGIN
serin<='1';
wait for 50 ns;
serin<='0';
wait for 50 ns;
serin<='0';
wait for 50 ns;
serin<='1';

26
wait;
END PROCESS;
END;

8-BIT SISO LEFT SHIFT REGISTER

VHDL CODE
entity SISO_LEFT_8bit is
Port ( clk : in STD_LOGIC;
serin : in STD_LOGIC;
serout : out STD_LOGIC);
end SISO_LEFT_8bit;
architecture Behavioral of SISO_LEFT_8bit is
signal tmp:std_logic_vector(7 downto 0):="11100010";
begin
process(clk)
begin
if(rising_edge(clk))then
serout<=tmp(7);
for i in 0 to 6 loop

27
tmp(7-i)<=tmp(6-i);
end loop;
tmp(0)<=serin;
end if;
end process;
end Behavioral;
TEST BENCH
Refer 8-bit SISO right shift register test bench (no changes)

4-BIT SIPO LEFT SHIFT REGISTER

VHDL CODE
entity sipo_left_4bit is
Port ( serin : in STD_LOGIC; clk : in STD_LOGIC;
pout : out STD_LOGIC_VECTOR (3 downto 0));
end sipo_left_4bit;
architecture Behavioral of sipo_left_4bit is
signal tmp:STD_LOGIC_VECTOR (3 downto 0):="0000";
begin
process(clk)
begin
if(rising_edge(clk))then
tmp<=tmp(2 downto 0)& serin;
end if;
end process;

28
pout<=tmp;
end Behavioral;
TEST BENCH
ENTITY sipo_left_4bit_tb_vhd IS
END sipo_left_4bit_tb_vhd;
ARCHITECTURE behavior OF sipo_left_4bit_tb_vhd IS
COMPONENT sipo_left_4bit
PORT(serin : IN std_logic; clk : IN std_logic;
pout : OUT std_logic_vector(3 downto 0) );
END COMPONENT;
SIGNAL serin : std_logic := '1';
SIGNAL clk : std_logic := '1';
SIGNAL pout : std_logic_vector(3 downto 0);
BEGIN
uut: sipo PORT MAP(serin => serin,clk => clk, pout => pout );
clk<=not clk after 25 ns;
tb : PROCESS
BEGIN
wait for 500 ns;
serin<='0';
wait;
END PROCESS; END;

29
 4-BIT PISO RIGHT SHIFT REGISTER
VHDL CODE
entity piso_right_4bit is

Port ( clk : in STD_LOGIC;

loadbar_shift : in STD_LOGIC;

pin : in STD_LOGIC_VECTOR (3 downto 0);

sout : out STD_LOGIC);

end piso_right_4bit;

architecture Behavioral of piso_right_4bit is

signal tmp:std_logic_vector(3 downto 0):="0000";

begin

process(clk,loadbar_shift,pin)

begin

if(rising_edge(clk))then

if(loadbar_shift='0')then

tmp<=pin;

else

sout<=tmp(0);

tmp<='0'&tmp(3 downto 1);

30
end if;

end if;

end process;

end Behavioral;

TEST BENCH
ENTITY piso_right_4bit _tb_vhd IS
END piso_right_4bit _tb_vhd;
ARCHITECTURE behavior OF piso_right_4bit _tb_vhd IS
COMPONENT pis
PORT(clk : IN std_logic; loadbar_shift : IN std_logic;
pin : IN std_logic_vector(3 downto 0); sout : OUT std_logic );
END COMPONENT;
SIGNAL clk : std_logic := '1';
SIGNAL loadbar_shift : std_logic := '0';
SIGNAL pin : std_logic_vector(3 downto 0) := "1111";
SIGNAL sout : std_logic;
BEGIN
uut: pis PORT MAP(clk => clk, loadbar_shift => loadbar_shift, pin => pin,
sout => sout );
clk<=not clk after 25 ns;
tb : PROCESS
BEGIN
wait for 70 ns;
loadbar_shift<='1';
wait for 400 ns;
31
loadbar_shift<='0';
pin<="1011";
wait for 70 ns;
loadbar_shift<='1';
wait;
END PROCESS;

NOTE: for all registers draw logic diag.

JK to T flip-flop conversion
VHDL CODE
entity JK2T is
Port ( t : in STD_LOGIC;
j : inout STD_LOGIC;
k : inout STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC:='0');
end JK2T;
architecture Behavioral of JK2T is
begin

32
process(t,clk,j,k)
begin
if(clk'event and clk='1')then
j<=t;
k<=t;
if(j='0' and k='0')then
q<=q;
elsif(j='1' and k='1')then
q<=not q;
end if;
end if;
end process;
end Behavioral;
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY JK2T_TB_vhd IS
END JK2T_TB_vhd;
ARCHITECTURE behavior OF JK2T_TB_vhd IS
- Component Declaration for the Unit Under Test (UUT)
COMPONENT JK2T
PORT(t : IN std_logic;clk : IN std_logic; j : INOUT std_logic; k : INOUT std_logic;

33
 q : INOUT std_logic);
END COMPONENT;
--Inputs
SIGNAL t : std_logic := '0';
SIGNAL clk : std_logic := '0';
--BiDirs
SIGNAL j : std_logic;
SIGNAL k : std_logic;
SIGNAL q : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: JK2T PORT MAP(
t => t,
j => j,
k => k,
clk => clk,
q => q);
clk<=not clk after 50 ns;
tb : PROCESS
BEGIN
t<='1';
wait for 100 ns;
t<='0';
wait for 100 ns;

34
t<='1';
wait;
END PROCESS;
END;

JK to D flip-flop conversion
VHDL CODE
entity JK2D is
Port ( d : in STD_LOGIC;
j : inout STD_LOGIC;
k : inout STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC:='0');
end JK2D;
architecture Behavioral of JK2D is
begin
process(d,clk,j,k,q)

35
begin
j<=d; k<=not d;
if(clk'event and clk='1')then
if((j='0' and k='1')or (j='1' and k='0'))then
q<=d;
end if;
end if;
end process;
end Behavioral;
TEST BENCH
ENTITY JK2D_TB_vhd IS
END JK2D_TB_vhd;
ARCHITECTURE behavior OF JK2D_TB_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT JK2D
PORT(d : IN std_logic; clk : IN std_logic; j : INOUT std_logic;
k : INOUT std_logic; q : INOUT std_logic);
END COMPONENT;
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
--BiDirs
SIGNAL j : std_logic;
SIGNAL k : std_logic;

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SIGNAL q : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: JK2D PORT MAP(d => d,j => j,k => k,clk => clk,q => q);
clk<=not clk after 50 ns;
tb : PROCESS
BEGIN
d<='1';
wait for 100 ns;
d<='0';
wait for 100 ns;
d<='1';
wait;
END PROCESS;
END;

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