Behavioral Modeling

• It is a powerful tool to describe systems for which

the digital logic structures are not known.
• This shows how the outputs behave according to
changes in the inputs.
• Behavioral statements can be used to generate
both combinational logic and sequential logic.
• In VHDL, the behavioral statements are written
with in process and in Verilog, the statements are
written with in always or initial.
 Behavioral Modeling (VHDL)
• The behavior of the entity is expressed using sequentially
executed, procedural code, which is very similar in syntax and
semantics to that of a high level programming languages such
as C or Pascal.
• Process statement is the primary mechanism used to model
the behavior of an entity.
• Process statement has a declarative part (before the keyword
begin) and a statement part (between the keywords begin and
end process).
• The statements appearing within the process statement are
sequential statements and are executed sequentially
• The final output depends on the order of the statements,
unlike concurrent statements where the order is
inconsequential .
• All processes in an architecture behave concurrently
 VHDL

process (sensitivity list)

<declarations>
begin
<sequential statements>;
end process;
 Verilog

always@ (sensitivity list)

begin
< statements>;
end
 Sequential Statements
If statement in VHDL:
If condition1 then
If condition then sequence_of_statements;
sequence_of_statements elsif condition2 then
end if; sequence_of_statements;
elsif condition3 then
sequence_of_statements;
else
If condition then sequence_of_statements;
sequence_of_statements end if;
else
sequence_of_statements
end if;
 If statement in Verilog
If (condition1)
If (condition)
begin
begin
sequence_of_statements;
sequence_of_statements;
end
end else if (condition2)
begin
sequence_of_statements;
end
If (condition) else if (condition3)
begin begin
sequence_of_statements; sequence_of_statements;
end end
else else
begin begin
sequence_of_statements; sequence_of_statements;
end end
 multiplexer
entity mux is
Port ( s,a,b : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
architecture Behavioral of mux is
begin
process(s,a,b)
begin
if s='0' then
y<= a;
elsif s='1' then
y<= b;
end if;
end process;
end Behavioral;
 multiplexer
entity mux is
Port ( s,a,b : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
architecture Behavioral of mux is
begin
process(s)
begin
if s='0' then
y<= a;
elsif s='1' then
y<= b;
end if;
end process;
end Behavioral;
 multiplexer
entity mux is
Port ( e,s,a,b : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
architecture Behavioral of mux is
begin
process(e,s,a,b)
begin
if e='0' then
if s='0' then
y<= a;
elsif s='1' then
y<= b;
end if;
end if;
end process;
end Behavioral;
 multiplexer
module multiplexer(s,a,b, y);
input s,a,b;
output y;
reg y;
always@(s,a,b)
begin
if (s==0)
y=a;
else
y=b;
end
endmodule
 multiplexer
module multiplexer(s,a,b, y);
input s,a,b;
output y;
reg y;
always@(s,a,b)
begin
if (s)
y=b;
else
y=a;
end
endmodule
 multiplexer
module mux(a, b,e, s, y);
input a,e;
input b;
input s;
output y;
reg y;
always@(a,b,s,e)
begin
if (e==0)
if (s==0)
y=a;
else
y=b;
end
endmodule
 D-FF
entity df is
Port ( d : in std_logic;
clk : in std_logic;
q : inout std_logic;
qb : out std_logic);
end df;
architecture Behavioral of df is
begin
process(clk,d)
begin
if clk'event and clk='1'then
q<=d;
qb<=not q;
end if;
end process;
end Behavioral;
waveforms
 D-f
entity df is
Port ( d,clk : in std_logic;
q : inout std_logic;
qb : out std_logic);
end df;
architecture Behavioral of df is
Begin
process(clk)
begin
if rising_edge (clk) then
q<=d;
end if;
end process;
qb<= not q;
end Behavioral;
waveforms
 T-FF
entity togglef is
Port ( t,clk : in std_logic;
q : inout std_logic;
qb : out std_logic);
end togglef;
architecture Behavioral of togglef is
begin
process(clk)
begin
if clk'event and clk='1' then
if t='0‘ then
q<=q;
else
q<=not q;
end if;
end if;
end process;
qb<= not q;
end Behavioral;
waveforms
 T-FF
entity tff is
Port ( t,clk : in std_logic;
q : inout std_logic;
qb : out std_logic);
end tff;
architecture Behavioral of tff is
begin
process(clk)
variable s:std_logic:='0';
begin
if rising_edge (clk) then
if t='0' then s:=s;
elsif t='1'then s:=not s;
end if;
end if;
q<=s;
end process;
qb<=not q;
end Behavioral ;
waveforms
 T-FF
entity tff is
Port ( t,clk,clr : in std_logic;
q : inout std_logic;
qb : out std_logic);
end tff;
architecture Behavioral of tff is
begin
process(clk,clr)
begin
if clr='0' then q<='0';
elsif rising_edge (clk) then
if t='0' then q<=q;
elsif t='1'then q<= not q;
end if;
end if;
end process;
qb<= not q;
end behavioral;
waveforms
 T-FF
entity tff is
Port ( t,clk,clr : in std_logic;
q : out std_logic;
qb : out std_logic);
end tff;
architecture Behavioral of tff is
begin
process(clk,clr)
Variable s:std_logic;
begin
if clr='0' then s:='0';
elsif rising_edge (clk) then
if t='0' then s:=s;
elsif t='1'then s:= not s;
end if;
end if;
q<= s;
qb<= not s;
end process;
end behavioral;
waveform
 T-FF
entity tff is
Port ( t,clk,clr : in std_logic;
q : inout std_logic;
qb : out std_logic);
end tff;
architecture Behavioral of tff is
begin
process(clk,clr)
begin
if clr='0' then q<='0';
elsif rising_edge (clk) then
q<=t xor q;

end if;

end process;
qb<= not q;
end behavioral;
 D-FF
module dataf(d,clk, q, qb);
input d,clk;
output q,qb;
reg q;
always@(posedge(clk))
begin
if (clk)
q=d;
end
assign qb=~q;
endmodule
 D-FF
module dataf(d,clk, q, qb);
input d,clk;
output q,qb;
reg q,qb;
always@(posedge(clk))
begin
if (clk)
q=d;
qb=~q;
end
endmodule
 D-FF
module dataf(d,clk,q,qb);
input d,clk;
output q,qb;
reg q,qb;
always@(posedge(clk))
begin
q=d;
qb=~q;
end
endmodule
 T-FF
module tff(t,clk, q,qb);
input t,clk;
output q,qb;
reg q;
initial q=0;
always@(posedge clk)
begin
if (clk)
if (t==0)
q=q;
else if (t==1)
q=~q;
end
assign qb=~q;
endmodule
Simulation
 T-FF
module tff(t,clk, q,qb);
input t,clk;
output q,qb;
reg q;
initial q=0;
always@(posedge clk)
begin
if (t==0)
q=q;
else if (t==1)
q=~q;
end
assign qb=~q;
endmodule
 T-FF
module tff(t,clr,clk, q,qb);
input t,clr,clk;
output q,qb;
reg q;
always@(posedge clk,clr)
begin
if (clr==0)
q=0;
else if (clk)
if (t==0)
q=q;
else if (t==1)
q=~q;
end
assign qb=~q;
endmodule
 T-FF
module tff(t,clr,clk, q,qb);
input t,clr,clk;
output q,qb;
reg q;
always@(posedge clk,clr)
begin
if (clr==0)
q=0;
else if (t==0)
q=q;
else if (t==1)
q=~q;
end
assign qb=~q;
endmodule
waveforms
 Mod-5 counter
entity mod5cntr is
Port ( clk,clr : in std_logic;
q : out std_logic_vector(2 downto 0));
end mod5cntr;
architecture Behavioral of mod5cntr is
begin
process(clk,clr)
variable s:std_logic_vector(2 downto 0);
begin
if clr='0'then s:="000";
elsif clk'event and clk='0' then
if s<"100" then s:=s+1;
else s:="000";
end if;
end if;
q<=s;
end process;
end Behavioral;
 Up-counter
module upcnt(clr,clk, q);
input clr,clk;
output [1:0] q;
reg [1:0]q;
always@(clr,posedge clk)
begin
if (clr==0)
q=00;
else if (clk)
q=q+1;
end
endmodule
 CASE statement

case condition is
when choice1=>statements;
when choice2=>statements;
when choice3=>statements;
when others=>statements;
end case;
 Case statement in verilog
case (condition)
choice1: begin
statements;
end
choice2: begin statements; end
choice3: begin statements; end
default: begin statements; end
endcase
 Mux(4:1)
entity mux4to1 is
Port ( i : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux4to1;
architecture Behavioral of mux4to1 is
begin
process(s,i)
begin
case s is
when "00"=>y<=i(0);
when "01"=>y<=i(1);
when "10"=>y<=i(2);
when “11”=>y<=i(3);
end case;
end process;
end Behavioral;
 Mux(4:1)
entity mux4to1 is
Port ( i : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
e : in std_logic;
y : out std_logic);
end mux4to1;
architecture Behavioral of mux4to1 is
begin
process(s,i,e)
begin
if e='0' then
case s is
when "00"=>y<=i(0);
when "01"=>y<=i(1);
when "10"=>y<=i(2);
when others=>y<=i(3);
end case;
else y<='Z';
end if;
end process;
end Behavioral;
 Multiplexer(4:1)
module multi4to1(i, s, y);
input [3:0] i;
input [1:0] s;
output y;
reg y;
always@(i,s)
begin
case (s)
2'b00: y=i[0];
2'b01: y=i[1];
2'b10: y=i[2];
2’b11: y=i[3];
endcase
end
endmodule
 Multiplexer(4 to1)
module multi4to1(i, s, e, y);
input [3:0] i;
input [1:0] s;
input e;
output y;
reg y;
always@(i,s,e)
begin
if (e==0)
case (s)
2'b00:y=i[0];
2'b01:y=i[1];
2'b10:y=i[2];
default:y=i[3];
endcase
else y=1'bz;
end
endmodule
entity jkf is
JKFF
Port ( j,k,clk,clr : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jkf;
architecture Behavioral of jkf is
Begin
process(clk,clr)
variable p :std_logic_vector(1 downto 0);
variable y:std_logic;
begin
p:=j&k;
if clr='0' then y:='0';
elsif rising_edge (clk) then
case p is
when "00"=>y:=y;
when "01"=>y:='0';
when "10"=>y:='1';
when "11"=>y:=not y;
when others=>null;
end case;
end if;
q<=y;
qb<= not y;
end process;
end Behavioral;
entity usr is
Universal Shift Register
Port ( clk,clr,si : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
q : out STD_LOGIC_VECTOR (3 downto 0));
end usr;
architecture Behavioral of usr is
Begin
process(clk,clr)
variable s:std_logic_vector(3 downto 0);
begin
if clr='0' then s:=(others=>'0');
elsif clk'event and clk='1' then
case sel is
when "00"=> s:=s;
when "01"=> s:=d;
when "10"=> s:=si&s(3 downto 1);
when "11"=> s:=s(2 downto 0)&si;
when others=>null;
end case;
end if;
q<=s;
end process;
end Behavioral;
State Diagram
 VHDL code for state diagram
entity statediagram is
Port ( clk,clr : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (1 downto 0));
end statediagram;
architecture Behavioral of statediagram is
begin
process(clk,clr)
variable s:std_logic_vector(1 downto 0);
begin
if clr='0' then s:="00";
elsif clk'event and clk='1' then
case s is
when "00" => s:="01";
when "01" => s:="10";
when "10" => s:="11";
when "11" => s:="00";
when others=>null;
end case;
end if;
q<=s;
end process;
end Behavioral;
HDL code for the following state diagram
 LOOPS
(a) FOR LOOP: Eg: Factorial of 5

SYNTAX:
PROCESS ( )
PROCESS ( ) BEGIN
BEGIN fact <=1;
FOR identifier IN range LOOP FOR i IN 1 to 5
LOOP
:
fact <=fact*i;
sequential statements; END LOOP;
:
END LOOP; END PROCESS;
END PROCESS;
(b) WHILE LOOP
Eg: Factorial of 5

SYNTAX: PROCESS ( )
PROCESS ( )
BEGIN
BEGIN fact <=1;
WHILE (condition) LOOP i<=1;
: WHILE(i<=5)
sequential statements; LOOP
:
fact <=fact*i;
END LOOP;
i<=i+1;
END PROCESS; END LOOP;

END PROCESS;
 Loops in Verilog

FOR loop:
for(initial value, condition,
increment/decrement)
begin
statements;
end
 While Loop

While (condition)
begin
statements;
end