Instruction Sets Should Be Free: The Case For RISC-V

Krste Asanović
David A. Patterson

Electrical Engineering and Computer Sciences

Technical Report No. UCB/EECS-2014-146

August 6, 2014
 Copyright © 2014, by the author(s).
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Custom systems-on-a-chip (SoCs), where the processors open source software. For example, it would enable a
and caches are a small part of the chip, are becoming real free open market of processor designs, which
ubiquitous; it is rare today to find an electronics product patents on ISA quirks prevent. This could lead to:
at any scale that does not include an on-chip processor. • Greater innovation via free-market competition from
Thus, many more companies are designing chips that many more designers, including open vs. proprietary
include processors than in the past. Given that the implementations of the ISA.
industry has been revolutionized by open standards and • Shared open core designs, which would mean
open source software—with networking protocols like shorter time to market, lower cost from reuse, fewer
TCP/IP and operating systems (OS) like Linux—why is errors given many more eyeballs3, and transparency
one of the most important interfaces proprietary? that would make it hard, for example, for
The Case for a Free, Open ISA government agencies to add secret trap doors.
While instruction set architectures (ISAs) may be • Processors becoming affordable for more devices,
proprietary for historical or business reasons, there is no which helps expand the Internet of Things (IoTs),
good technical reason for the lack of free, open ISAs: which could cost as little as $1.
• It’s not an error of omission. Companies with The Case for RISC as the Free, Open ISA Style
successful ISAs like ARM, IBM, and Intel have For an ISA to be embraced by an open-source
patents on quirks of their ISAs, which prevent others community, we believe it needs a proven commercial
from using them without licenses.1 Negotiations take record. The first question, then, is which style of ISA has
6-24 months and they can cost $1M-$10M, which a history of success. There hasn’t been a successful stack
rules out academia and others with small volumes.2 ISA in 30 years. Except for parts of the DSP market,
An ARM license doesn’t even let you design an VLIWs have failed: Multiflow went belly up and Itanium
ARM core; you just get to use their designs. (Only was a bust despite billions of dollars invested by HP and
≈15 big companies have licenses that allow new Intel. It’s been decades since any new CISC ISA has
ARM cores.) Even “OpenPOWER” is an oxymoron; been successful. The surviving CISCs translate from
you must pay IBM to use its ISA. While business complex ISAs to easier-to-execute ISAs, which makes
sound, licenses stifle competition and innovation by great sense for executing a valuable legacy code-base. A
stopping many from designing and sharing their new ISA by definition won’t have any legacy code, so
ISA-compatible cores. the extra hardware cost and energy cost of translation are
• Nor is it because the companies do most of the hard to justify; why not just use an easy-to-execute ISA
software development. Despite the value of the in the first place? RISC-style load-store ISAs date back
software ecosystems that grow around popular ISAs, at least 50 years to Seymour Cray’s CDC 6600. While
outsiders build almost all of the software for them. the 80x86 won the PC wars, RISC dominates the tablets
• Neither do companies exclusively have the and smart phones of the PostPC Era; in 2013 more than
experience needed to design a competent ISA. While 10B ARMs were shipped, as compared to 0.3B 80x86s.
it’s a lot of work, many today can design ISAs. Repeating what we said in 19804, we propose that RISC
• Nor are the most popular ISAs wonderful ISAs. is the best choice for an (free, open) ISA.
80x86 and ARM aren’t considered ISA exemplars. Moreover, a new RISC ISA can be better than its
• Neither can only companies verify ISA compatibility. predecessors by learning from their mistakes:
Open organizations developed mechanisms to ensure • Leaving out too much: No load/store byte or
compatibility with hardware standards long ago, load/store half word in the initial Alpha ISA, and no
such as IEEE 754 floating point, Ethernet, and PCIe. floating-point load/store double in MIPS I.
If not, open IT standards would not be so popular. • Including too much: The shift option for ARM
• Finally, proprietary ISAs are not guaranteed to last. instructions and register windows in SPARC.
If a company dies, it takes its ISAs with it; DEC’s • Allowing current microarchitectural designs to
demise also terminated the Alpha and VAX ISAs. affect the ISA: Delayed branch in MIPS and SPARC,
Note that an ISA is really an interface specification, and and floating-point trap barriers in Alpha.
not an implementation. There are three types of To match embedded market needs, RISCs even offered
implementations of an ISA: solutions to the code size issue: ARM Thumb and
1. Private closed source, analogous to Apple iOS. MIPS16 added 16-bit formats to offer code smaller than
2. Licensed open source, like Wind River VxWorks. 80x86. Thus, we believe there is widespread agreement
3. Free, open source that users can change and share, on the general outline of a good RISC ISA.
like Linux. The Case for Using an Existing RISC Free, Open ISA
Proprietary ISAs in practice allow the first two types of The good news is that there are already three RISC
cores, but you need a free, open ISA to enable all three. free, open ISAs5:
We conclude that the industry would benefit from • SPARC V8 - To its credit, Sun Microsystems made
viable freely open ISAs just as it has benefited from free SPARC V8 an IEEE standard in 1994.
1  
• OpenRISC - This GNU open-source effort started in Address Software

Base+Ext

Quad FP
Compact
2000, with the 64-bit ISA being completed in 2011.

128-bit

QEMU
ISA

LLVM
32-bit
64-bit

Linux
Code

GCC
• RISC-V - In 2010, partly inspired by ARM's IP res-
trictions together with the lack of 64-bit addresses
SPARC V8 ✓ ✓ ✓ ✓ ✓ ✓
and overall baroqueness of ARM v7, we and our ✓ ✓ ✓ ✓ ✓ ✓
OpenRISC
grad students Andrew Waterman and Yunsup Lee RISC-V ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
developed RISC-V6 (pronounced "RISC 5") for our
research and classes, and made it BSD open source. The Case for RISC-V as the RISC Free, Open ISA
As it takes years to get the details right—the gestation Our community should rally around a single ISA to
period for OpenRISC was 11 years and RISC-V was 4 test whether a free, open ISA can work. Only RISC-V
years—it seems wiser to start with an existing ISA than meets all four requirements. RISC-V is also 10 to 20
to form committees and start from scratch. RISC ISAs years younger, so we had the chance to learn from and
tend to be similar, so any one might be a good candidate. fix the mistakes of previous RISC ISAs—e.g., SPARC
Given ISAs can live for decades, let’s first project and OpenRISC have delayed branches—which is why
the future IT landscape to see what features might be RISC-V is so simple and clean (see Tables 4 and 5 and
important to help rank the choices. Three platforms will www.riscv.org). In addition to the other ISAs missing
likely dominate: 1) IoTs – billions of cheap devices with most requirements, a concern is that the 64-bit address
IP addresses and Internet access; 2) Personal mobile version of SPARC (V9) is proprietary, and that
devices, such as smart phones and tablets today; OpenRISC may have lost momentum.
3) Warehouse-Scale Computers (WSCs). While we RISC-V has plenty of momentum. Table 1 lists other
could have distinct ISAs for each platform, life would be groups designing RISC-V SoCs. Thanks in part to the
simpler if we could use a single ISA design everywhere. highly productive, open-source hardware design system
This landscape suggests four key requirements: Chisel9, Berkeley has 8 silicon chips already and more in
1. Base-plus-extension ISA.7 To improve efficiency and progress. Table 2 shows one 64-bit RISC-V core that is
to reduce costs, SoCs add custom application-specific half the area, half the power, and faster than a 32-bit
accelerators. To match the needs of SoCs while ARM core with a similar pipeline in the same process.
maintaining a stable software base, a free, open ISA Although it’s hard to set aside biases, we believe that
should have: i) a small core set of instructions that RISC-V is the best and safest choice for a free, open
compilers and OS’s can depend upon; ii) standard RISC ISA. Thus, we will hold workshops and tutorials10
but optional extensions for common ISA additions to to expand the RISC-V community and, inspired by
help customize the SoC to the application; and Table 3, plan to start a non-profit foundation to certify
iii) space for entirely new opcodes to invoke the implementations and to maintain and evolve the ISA.
application-specific accelerators. Conclusion
2. Compact instruction set encoding. Smaller code is The case is even clearer for an open ISA than for an
desirable given the cost sensitivity of IoTs and the open OS, as ISAs change very slowly, whereas
resulting desire for smaller memory. algorithmic innovations and new application demands
3. Quadruple-precision (QP) as well as SP and DP force continual OS evolution. It is also an interface
floating point. Some applications running in WSCs standard like TCP/IP, thus simpler to maintain and
today process such large data sets that they already evolve than an OS.
rely on software libraries for QP arithmetic. Open ISAs have been tried before, but they never
4. 128-bit addressing as well as 32-bit and 64-bit. The became popular due to the lack of demand. The low cost
limited memory size of IoTs means 32-bit addressing and power of IoTs, the desire for a WSC alternative to
will be important for decades to come, while 64-bit the 80x86, and the fact that cores are a small but
addressing is the de facto standard in anything larger. ubiquitous fraction of all SoCs combine to supply that
Although the WSC industry won’t need 2128 bytes, missing demand. RISC-V is aimed at SoCs, with a base
it’s plausible that within a decade WSCs might need that should never change given the longevity of the basic
more than 264 bytes (16 exabytes) to address all of RISC ideas; a standard set of optional extensions that
their solid-state non-volatile storage. As address size will evolve slowly; and unique instructions per SoC that
is the one ISA mistake from which it is hard to never need to be reused. While the first RISC-V
recover8, it’s wise to plan for bigger addresses now. beachhead may be IoTs or perhaps WSCs, our goal is
The table below scores the 3 free open ISAs using these grander: just as Linux has become the standard OS for
4 criteria, plus a listing of critical compiler and OS ports. most computing devices, we envision RISC-V becoming
the standard ISA for all computing devices.

2  
References  
1
MIPS letter (2002). http://brej.org/yellow_star/letter.pdf.  

Dhrystone Performance

(DMIPS/MHz/mm2)
2
Demerjian, C. (2013). “A long look at how ARM licenses

Frequency (GHz)

Dynamic Power
Area Efficiency
(16 KB caches)
(DMIPS/MHz)
chips: Part 1 of 2,” semiaccurate.com/2013/08/07/a-long-look-

Width (bits)

(mW/MHz)
(no caches)
Area mm2

Area mm2
at-how-arm-licenses-chips/.

ISA
3
Raymond, E. (1999). The Cathedral and the Bazaar.
Knowledge, Technology & Policy, 12(3), 23-49.
4
Patterson, D. & D. Ditzel. (1980) "The Case for the Reduced
Instruction Set Computer." SIGARCH Computer Architecture
News 8.6, 25-33.
5
We recently learned about the new Open Core Foundation, ARM 32 >1 1.57 0.27 0.53 3.0 <0.080
which is planning a 64-bit open core for 2016 based on SH-4.
6
Waterman, A. et al. (2014). The RISC-V Instruction Set RISC-V 64 >1 1.72 0.14 0.39 4.4 0.034
Manual, Volume I: User-Level ISA, Version 2.0. EECS R/A 2 1 1.1 0.5 0.7 1.5 ≥0.4
Technical Report No. UCB/EECS-2014-54, UC Berkeley.
7 Table 2. Comparison of a 32-bit ARM core (Cortex-A5) to a
Estrin, G. (1960) “Organization of computer systems: the
fixed plus variable structure computer.” Western Joint IRE- 64-bit RISC-V core (Rocket) built in the same TSMC process
AIEE-ACM Computer Conference, 33-40. (40GPLUS). Third row is ratio of RISC-V Rocket to ARM
8
Bell, G., & W. Strecker. (1976) "Computer structures: What Cortex-A5. Both use single-instruction-issue, in-order
have we learned from the PDP-11?," 3rd ISCA, 1-14. pipelines, yet the RISC-V core is faster, smaller, and uses less
10
Bachrach, J., et al. (2012) "Chisel: constructing hardware in power. This data is from the ARM website and the paper
a Scala embedded language." Proc. 49th DAC, 1216-1225. “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V
8
The first RISC-V workshop will be held January 14-15, 2015 Processor with Vector Accelerators” by Y. Lee et al that will
in Monterey, CA. https://www.regonline.com/riscvworkshop. appear in the 40th European Solid-State Circuits Conference,
 
September 22-24, 2014.
Org Cores Description
Development of a complete range of Name Year Description
processors, ranging from micro-controllers Provides support for the Apache
to server/HPC grade processors. They Apache
community of open-source software
began with the IBM Power ISA, but Software 1999
projects, which provide software
switched a year later to RISC-V for both Foundation
products for the public good.
technical and licensing reasons. The 6 Works to secure freedom for
IIT distinct Indian processors and associated Free computer users by promoting the
6
Madras SoC components are designed to offer Software 1985 development and use of free software
viable, open source alternatives to Foundation and documentation — particularly the
proprietary commercial processors. All GNU operating system.
implementations will be provided as
A vendor and technology-neutral
patent/royalty-free, BSD-licensed open
industry consortium, currently with
source in keeping with the RISC-V
over 400 member organizations. It
philosophy (rise.cse.iitm.ac.in/shakti.html)
was formed in 1996 when X/Open
merged with the Open Software
The lowRISC project (lowrisc.org) is Open Foundation. Services provided
based in Cambridge (UK) and led by one 1996
Group include strategy, management,
of the founders of Raspberry Pi, which is a innovation and research, standards,
Low- popular $35 computer. Their goal is to certification, and test development.
1
RISC produce open source RISC-V-based SoCs, The Open Group is most famous as
and they have plans for volume silicon the certifying body for UNIX
manufacture and low-cost development trademark.
boards.
Table 3. Example non-profit software foundations that
The EDA company Bluespec maintain and evolve open source projects for decades. We
(bluespec.com) in the US has customers presume to match the longevity of such software projects, we
interested in an open ISA, so they are will need a similar organization to maintain and evolve a free,
Blue-
1 doing RISC-V designs in the Bluespec open ISA.
spec
synthesis toolset and have ported the GDB
debugger and the GNU soft-float ABI to
RISC-V
 
 
Table 1. RISC-V projects beyond UC Berkeley.
3  
Category Name Format RV32I Base +RV64 +RV128
Loads Load Byte I LB rd,rs1,imm
Load Halfword I LH rd,rs1,imm
Load Word I,Cx LW rd,rs1,imm LD rd,rs1,imm LQ rd,rs2,imm
Load Byte Unsigned I LBU rd,rs1,imm
Load Half Unsigned I LHU rd,rs1,imm LWU rd,rs1,imm LDU rd,rs1,imm
Stores Store Byte S SB rs1,rs2,imm
Store Halfword S SH rs1,rs2,imm
Store Word S,Cx SW rs1,rs2,imm SD rs1,rs2,imm SQ rs1,rs2,imm
Arithmetic ADD R,Cx ADD rd,rs1,rs2 ADDW rd,rs1,rs2 ADDD rd,rs1,rs2
ADD Immediate I,Cx ADDI rd,rs1,imm ADDIW rd,rs1,imm ADDID rd,rs1,imm
SUBtract R,Cx SUB rd,rs1,rs2 SUBW rd,rs1,rs2 SUBD rd,rs1,rs2
Load Upper Imm U LUI rd,imm
Add Upper Imm to PC U AUIPC rd,imm
Logical XOR R XOR rd,rs1,rs2
XOR Immediate I XORI rd,rs1,imm
OR R,Cx OR rd,rs1,rs2
OR Immediate I ORI rd,rs1,imm
AND R,Cx AND rd,rs1,rs2
AND Immediate I ANDI rd,rs1,imm
Shifts Shift Left R SLL rd,rs1,rs2 SLLW rd,rs1,rs2 SLLD rd,rs1,rs2
Shift Left Immediate I,Cx SLLI rd,rs1,shamt SLLIW rd,rs1,shamt SLLID rd,rs1,shamt
Shift Right R SRL rd,rs1,rs2 SRLW rd,rs1,rs2 SRLD rd,rs1,rs2
Shift Right Immediate I SRLI rd,rs1,shamt SRLIW rd,rs1,shamt SRLID rd,rs1,shamt
Shift Right Arithmetic R SRA rd,rs1,rs2 SRAW rd,rs1,rs2 SRAD rd,rs1,rs2
Shift Right Arith Imm I SRAI rd,rs1,shamt SRAIW rd,rs1,shamt SRAID rd,rs1,shamt
Compare Set < R SLT rd,rs1,rs2
Set < Immediate I SLTI rd,rs1,imm
Set < Unsigned R SLTU rd,rs1,rs2
Set < Unsigned Imm I SLTIU rd,rs1,imm
Branches Branch = SB,Cx BEQ rs1,rs2,imm
Branch ≠ SB,Cx BNE rs1,rs2,imm
Branch < SB BLT rs1,rs2,imm
Branch ≥ SB BGE rs1,rs2,imm
Branch < Unsigned SB BLTU rs1,rs2,imm
Branch ≥ Unsigned SB BGEU rs1,rs2,imm
Jump & Link J&L UJ,Cx JAL rd,imm
Jump & Link Register UJ,Cx JALR rd,rs1,imm
Synch Synch threads I FENCE
Synch Instr & Data I FENCE.I
System System CALL I SCALL
System BREAK I SBREAK
Counters ReaD CYCLE I RDCYCLE rd
ReaD CYCLE upper Half I RDCYCLEH rd
ReaD TIME I RDTIME rd
ReaD TIME upper Half I RDTIMEH rd
ReaD INSTR RETired I RDINSTRET rd
ReaD INSTR upper Half I RDINSTRETH rd
32-bit Formats 16-bit Formats

R CI1
R4 CI2
I CJ
S CI3
SB CB
U CR
UJ

Table 4. RISC-V Integer Base Instructions (RV32I/64I/128I) and instruction formats. The base has 40 classic RISC
integer instructions, plus 10 miscellaneous instructions for synchronization, system calls, and counters. All RISC-V
implementations must include these base instructions, and we call the 32-bit version RV32I. The 64-bit and 128-bit
versions (RV64I and RV128I) expand all the registers to those widths and add 10 instructions for new data transfer
and shift instructions of the wider formats. It also shows the optional compressed instruction extension: those 12
instructions with Cx formats, which are 16 bits long. There are other optional instruction extensions defined so far:
Multiply-Divide, SP/DP/QP Floating Point, and Atomic. To learn more, see www.riscv.org
4  
Category Name Format RV32M (Multiply-Divide) +RV64 +RV128
Multiply MULtiply R MUL rd,rs1,rs2 MULW rd,rs1,rs2 MULD rd,rs1,rs2
MULtiply upper Half R MULH rd,rs1,rs2
MULtiply Half Sign/Uns R MULHSU rd,rs1,rs2
MULtiply upper Half Uns R MULHU rd,rs1,rs2
Divide DIVide R DIV rd,rs1,rs2 DIVW rd,rs1,rs2 DIVD rd,rs1,rs2
DIVide Unsigned R DIVU rd,rs1,rs2
Remainder REMainder R REM rd,rs1,rs2 REMW rd,rs1,rs2 REMD rd,rs1,rs2
REMainder Unsigned R REMU rd,rs1,rs2 REMUW rd,rs1,rs2 REMUD rd,rs1,rs2
Category Name Format RV32{F,D,Q} (SP,DP,QP Fl. Pt.) +RV64 +RV128
Load Load I FL{W,D,Q} rd,rs1,imm
Store Store S FS{W,D,Q} rs1,rs2,imm
Arithmetic ADD R FADD.{S,D,Q} rd,rs1,rs2
SUBtract R FSUB.{S,D,Q} rd,rs1,rs2
MULtiply R FMUL.{S,D,Q} rd,rs1,rs2
DIVide R FDIV.{S,D,Q} rd,rs1,rs2
SQuare RooT R FSQRT.{S,D,Q} rd,rs1
Mul-Add Multiply-ADD R4 FMADD.{S,D,Q} rd,rs1,rs2,rs3
Multiply-SUBtract R4 FMSUB.{S,D,Q} rd,rs1,rs2,rs3
Negative Multiply-SUBtract R4 FNMSUB.{S,D,Q} rd,rs1,rs2,rs3
Negative Multiply-ADD R4 FNMADD.{S,D,Q} rd,rs1,rs2,rs3
Move Move from Integer R FMV.X.S rd,rs1 FMV.X.D rd,rs1 FMV.X.Q rd,rs1
Move to Integer R FMV.S.X rd,rs1 FMV.D.X rd,rs1 FMV.Q.X rd,rs1
Sign Inject SiGN source R FSGNJ.{S,D,Q} rd,rs1,rs2
Negative SiGN source R FSGNJN.{S,D,Q} rd,rs1,rs2
Xor SiGN source R FSGNJX.{S,D,Q} rd,rs1,rs2
Min/Max MINimum R FMIN.{S,D,Q} rd,rs1,rs2
MAXimum R FMAX.{S,D,Q} rd,rs1,rs2
Compare Compare Float = R FEQ.{S,D,Q} rd,rs1,rs2
Compare Float < R FLT.{S,D,Q} rd,rs1,rs2
Compare Float ≤ R FLE.{S,D,Q} rd,rs1,rs2
Convert Convert from Int R FCVT.W.{S,D,Q} rd,rs1 FCVT.L.{S,D,Q} rd,rs1 FCVT.T.{S,D,Q} rd,rs1
Convert from Int Unsigned R FCVT.WU.{S,D,Q} rd,rs1 FCVT.LU.{S,D,Q} rd,rs1 FCVT.TU.{S,D,Q} rd,rs1
Convert to Int R FCVT.{S,D,Q}.W rd,rs1 FCVT.{S,D,Q}.L rd,rs1 FCVT.{S,D,Q}.T rd,rs1
Convert to Int Unsigned R FCVT.{S,D,Q}.WU rd,rs1 FCVT.{S,D,Q}.LU rd,rs1 FCVT.{S,D,Q}.TU rd,rs1
Categorization Classify Type R FCLASS.{S,D,Q} rd,rs1
Configuration Read Status R FRCSR rd
Read Rounding Mode R FRRM rd
Read Flags R FRFLAGS rd
Swap Status Reg R FSCSR rd,rs1
Swap Rounding Mode R FSRM rd,rs1
Swap Flags R FSFLAGS rd,rs1
Swap Rounding Mode Imm I FSRMI rd,imm
Swap Flags Imm I FSFLAGSI rd,imm
Category Name Format RV32A (Atomic) +RV64 +RV128
Load Load Reserved R LR.W rd,rs1 LR.D rd,rs1 LR.Q rd,rs1
Store Store Conditional R SC.W rd,rs1,rs2 SC.D rd,rs1,rs2 SC.Q rd,rs1,rs2
Swap SWAP R AMOSWAP.W rd,rs1,rs2 AMOSWAP.D rd,rs1,rs2 AMOSWAP.Q rd,rs1,rs2
Add ADD R AMOADD.W rd,rs1,rs2 AMOADD.D rd,rs1,rs2 AMOADD.Q rd,rs1,rs2
Logical XOR R AMOXOR.W rd,rs1,rs2 AMOXOR.D rd,rs1,rs2 AMOXOR.Q rd,rs1,rs2
AND R AMOAND.W rd,rs1,rs2 AMOAND.D rd,rs1,rs2 AMOAND.Q rd,rs1,rs2
OR R AMOOR.W rd,rs1,rs2 AMOOR.D rd,rs1,rs2 AMOOR.Q rd,rs1,rs2
Min/Max MINimum R AMOMIN.W rd,rs1,rs2 AMOMIN.D rd,rs1,rs2 AMOMIN.Q rd,rs1,rs2
MAXimum R AMOMAX.W rd,rs1,rs2 AMOMAX.D rd,rs1,rs2 AMOMAX.Q rd,rs1,rs2
MINimum Unsigned R AMOMINU.W rd,rs1,rs2 AMOMINU.D rd,rs1,rs2 AMOMINU.Q rd,rs1,rs2
MAXimum Unsigned R AMOMAXU.W rd,rs1,rs2 AMOMAXU.D rd,rs1,rs2 AMOMAXU.Q rd,rs1,rs2
Table 5. RISC-V Optional Extensions: Multiply-Divide, SP/DP/QP Fl. Pt., and Atomic. It further demonstrates the
base-plus-extension nature of RISC-V, which has optional extensions of: 10 multiply-divide instructions (RV32M); 25
floating-point instructions each for SP, DP, or QP (RV32S, RV32D, RV32Q); and 11 optional atomic instructions
(RV32A). Just as when expanding from RV32I to RV64I and RV128I, for each address-size option we need to add a
few more instructions for the wider data: 4 wider multiples and divides; 6 moves and converts for floating point; and
11 wider versions of the atomic instructions. To learn more, see www.riscv.org.

5