Baker Ch.

6 MOSFET Operation Introduction to VLSI

 Chapter 6
– MOSFET Operation
• Capacitance
– Accumulation
– Depletion
– Inversion
• IV Characteristics
– Linear
– Saturation
– Spice Models
• Short Channel
– LDD
– Scaling
– Hot Carriers
– Oxide Breakdown
– DIBL
– Body Effect
– Gate Tunneling

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 1
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 Capacitance - Accumulation  DESCRIPTION

– NFET, Vgs<0 ATTRACTS + HOLES
– MAJORITY CARRIERS AT SURFACE

– GATE TO BULK CAPACITANCE

• POLY GATE
• P+ HOLES AT SURFACE
• CGB= e (LEFF) (WDRAWN) / tOX

– GATE TO SOURCE/DRAIN CAP

• POLY GATE
• N- ELECTRONS AT SURFACE
• CGS = e (LDIFF (WDRAWN) / tOX

– SUBSTRATE RESISTANCE
• CANNOT NEGLECT

– WHAT IS NORMAL BIASING?

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 2
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 Capacitance - Depletion  DESCRIPTION

– NFET, Vgs BETWEEN RANGES
– NEITHER CARRIER AT SURFACE
– IMMOBILE IONS LEFT
– GATE TO CHANNEL CAPACITANCE
• POLY GATE
• SOME N- ELECTRONS
• APPROX C=e A / tox

– DEPL TO BULK CAPACITANCE

• SOME N- ELECTRONS SURFACE
• NO ANALYTICAL EQUATION

– GATE TO SOURCE/DRAIN CAP

Bottom Plate of Capacitor • POLY GATE
is moving “down”, further • N+ ELECTRONS AT SURFACE
Into the substrate • CGS = e (LDIFF (WDRAWN) / tOX

– WHAT IS OPERATING POINT?

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 3
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 Capacitance - Inversion  DESCRIPTION

– NFET, Vgs>Vtn
– N- ELECTRONS AT SURFACE

– GATE TO CHANNEL CAPACITANCE

• POLY GATE
• N- ELECTRONS
• C=e A / tox

– GATE TO SOURCE/DRAIN CAP

• POLY GATE
• N+ ELECTRONS AT SURFACE
• CGS = e (LDIFF (WDRAWN) / tOX

– WHAT IS OPERATING POINT?

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 4
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 CV CURVE  DESCRIPTION
– KEEP IN MIND OPERATING POINT
Holes being Holes being Electrons being – ACCUMULATION != GOOD CAP
accumulated repelled attracted • SERIES RESISTANCE TO TAP
– CAN USE MOSFET AS CAP
• SHORT SOURCE TO DRAIN
• IF VGATE CHANGES, VARACTOR
– SHOULD UNDERSTAND EACH CAP

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 5
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 IV TERMINLOGY

ID DRAIN CURRENT
 IMPLIES DRAIN TO SOURCE (IDS)
WHERE ELSE WOULD CURRENT GO FROM-TO?

IDLIN IDS IN LINEAR REGION

IDSAT IDS IN SATURATION REGION
mn MOBILITY OF ELECTRONS
W WIDTH OF CHANNEL
L LENGTH OF CHANNEL (CT-CT DIRECTION)
COX GATE OXIDE CAPACITANCE
VGS GATE TO SOURCE POTENTIAL
Vtn TRANSISTOR THRESHOLD FOR NFET
VDS DRAIN TO SOURCE POTENTIAL
VDS-SAT SATURATION VDS
VEFF VGS – VTN, HOW FAR ABOVE THRESHOLD IS THE GATE

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 6
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 IV VS. VDS CURVE  DESCRIPTION

– LINEAR REGION
• CHANNEL IS INVERTED
• V=IR IS LINEAR REGION

– SATURATION REGION
• CURRENT IS CONSTANT
FROM • NO DEPENDENCE NO VDS
MARTIN
– TRANISTION REGION
• NEED FULL EQUATION

Three regions of operation:

•Linear or Triode Region Vds << Veff channel inverted
•Saturation or Active Region Vds > Veff channel pinched off
•Transition region Vdg ~ Vt or Vds ~ Veff beginning of pinch off

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 7
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 IDS vs. VDS (SATURATION)  DESCRIPTION

– IDS vs. VDS, VARY VGS
• AS VGS INCR, R DECR
• VDsat, WHERE PINCHOFF OCCURS
• VGD=VT PINCHOFF

– TRANSCONDUCTANCE PARM
• KPN=mNCOX=mN eOX/tOX ~ 120uA/V2
• KPP=mPCOX=mP eOX/tOX ~ 40uA/V2

– MOBILITY DIFFERENCES
• mN=650 cm2/ V sec
• mP=250 cm2/ V sec

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 8
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 IDS vs. VGS (BODY EFFECT)  DESCRIPTION

– IDS vs. VGS, VARY VSB
• DETERMINES Vt
• BODY BIAS EFFECT
– BODY BIAS
• AS VSB INC, e- GO TO SOURCE
• DEPL DEPTH INCR
• HARDER TO INVERT SURFACE
– LOG IDS
• SHOWS Ioff LEAKAGE

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 9
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 IV CURVE SUMMARY  DESCRIPTION

IDS VS. VDS, VARY VGS
– LINEAR, SATURATION REGIONS
– DOES NOT SHOW Vt
– MAY SHOW SHORT CH EFFECTS

IDS VS. VGS, VARY VSB

– SHOWS Vt
– SHOWS BODY EFFECT

IDS VS. VGS, LOG SCALE

– DOES NOT SHOWS Vt
– SHOWS OFF-STATE CURRENT
– SHOWS SSLP

SHORT CHANNEL EFFECTS (SCE)

– Leff IS SMALLER THAN Ldrawn
– USE LDD TO MITIGATE IMPACT
– DRAIN ENGINEERING

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 10
 Baker Ch. 6 MOSFET Operation Introduction to VLSI

 IDS vs. VGS EXAMPLES  DESCRIPTION

S8 NFET 7.0/0.15 30C Vt VARIES WITH PROCESS
1.4E-03
– SHAPE OF CURVE CHANGES
ff (0.682)
– Vt DERIVED AT MAX INFLECTION
1.2E-03

tt (0.709)
1.0E-03
wfr (0.700)
• SMALL OFFSET OF VDS APPLIED
8.0E-04
LOG SCALE SHOWS Ioff
Ids

ss (0.735)
6.0E-04

4.0E-04

2.0E-04

0.0E+00
0.00 0.50 1.00 1.50 2.00 2.50
Vgs
S8 NFET 7.0/0.15 TT 30C S8 NFET 7.0/0.15 30C
1.E+00
6.0E-03 1.E-010.00 0.50 1.00 1.50 2.00 2.50

1.E-02
5.0E-03
tt (0.709)
1.E-03
Vds =0.1
4.0E-03 1.E-04

3.0E-03 1.E-05
1.E-06
Ids

2.0E-03
Ids

1.E-07
1.0E-03 1.E-08
1.E-09
0.0E+00
1.E-10
-1.0E-03 1.E-11
1.E-12
-2.0E-03
0.00 0.50 1.00 1.50 2.00 2.50
1.E-13 Ioff
1.E-14
Vgs
Vgs

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 11