EC-572 LSI/VLSI Design

Basic MOSFET Overview

By Dr. Shivam Verma

Department of Electronics Engineering, IIT
BHU, Varanasi

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 ECE 431 – Basic VLSI Design

MOSFET Operation

• Outline

• MOSFET Operation

- Device Physics
- MOSFET Structure
- IV Characteristics
- Scaling
- Capacitance

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 MOSFET Operation

• MOSFET Operation (p-type substrate)

- in order to access the channel created by inversion, we add two

doped regions at either end of the MOS structure

- these doped regions are of the minority carrier type (i.e., n-type)

- current can flow between these terminals if an inversion is created in the p-type silicon by VG

- since we are controlling the flow of current with a 3rd terminal, this becomes a “transistor”

- since we use an E-field to control the flow, this becomes the MOS Field Effect Transistor

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 MOSFET Operation

• Terminal Definition

Gate : The terminal attached to the metal of the MOS structure.

Source : One of the doped regions on either side of the MOS structure.
Defined as the terminal at the lower potential (vs. the Drain)

Drain : One of the doped regions on either side of the MOS structure.
Defined as the terminal at the higher potential (vs. the Source)

Body : The substrate

NOTE: we often don’t show the Body

connection

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 MOSFET Operation

• MOSFET Dimensions

Length : the length of the channel. This is defined as the distance between the Source
and Drain diffusion regions

Width : the width of the channel. Notice that the metal, oxide, source, and drain
each run this distance

tox : the thickness of the oxide between the metal and semiconductor

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 MOSFET Operation

• MOSFET Materials

Metal : Polysilicon. This is a silicon that has a heavy concentration of charge

carriers. This is put on using Chemical Vapor Deposition (CVD). It is
naturally conductive so it acts like a metal.

Oxide : Silicon-Oxide (SiO2). This is an oxide that is grown by exposing the Silicon to
oxygen and then adding heat. The oxide will grow upwards on the Silicon
surface

Semiconductor : Silicon is the most widely used semiconductor.

P-type Silicon : Silicon doped with Boron

N-type Silicon : Silicon doped with either Phosphorus or Arsenic

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 MOSFET Operation

• MOSFET Type

- we can create a MOSFET using either a p-type or n-type substrate. We then can move current
between the source and drain using the minority carriers in inversion to form the conduction channel

- we describe the type of MOSFET by describing what material is used to form the channel

N-Channel MOSFET P-Channel MOSFET

- p-type Substrate - n-type Substrate

- n-type Source/Drain - p-type Source/Drain
- current carried in n-type channel - current carried in p-type channel

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 MOSFET Operation

• Enhancement vs. Depletion MOSFETS

Enhancement Type : when a MOSFET has no conduction channel at VG=0v

: also called enhancement-mode
: we apply a voltage at the gate to turn ON the channel
: this is used most frequently and what we will use to learn VLSI

Depletion Type : when a MOSFET does have a conducting channel at VG=0v

: also called depletion-mode
: we apply a voltage at the gate to turn OFF the channel
: we won’t use this type of transistor for now

Note: We will learn VLSI circuits using enhancement-type, n-channel MOSFETS.

All of the principles apply directly to Depletion-type MOSFETs as well as
p-channel MOSFETs.

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 MOSFET Operation

• MOSFET Symbols

- there are multiple symbols for enhancement-type MOSFETs that can be used

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 MOSFET Operation

• Terminal Voltages

- all voltages in a MOSFET are defined relative to the Source terminal

VGS : Gate to Source Voltage

VDS : Drain to Source Voltage

VBS : Body to Source Voltage

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 MOSFET Operation Under Bias

• MOSFET under Bias (Depletion)

- let’s begin with an n-channel, enhancement-type MOSFET

- we bias the Source, Drain, and Body to 0v

- we apply a small positive voltage to the gate, VGS > 0 (small)

- this creates a depletion region beneath the Gate, Source, and Drain that is void of all charge carriers

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 MOSFET Operation Under Bias

• MOSFET under Bias (Inversion)

- as VGS gets larger, it will form an inversion layer beneath the Gate oxide by attracting the minority
carriers in the substrate to the oxide-Si surface.

- when the surface potential of the gate reaches the bulk Fermi potential, s = − F
the surface inversion will be established and an n-channel will form

- this channel forms a path between the Source and Drain

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 Threshold Voltage

• MOSFET under Bias (Inversion)

- as VGS gets larger, it will form an inversion layer beneath the Gate oxide by attracting the minority
carriers in the substrate to the oxide-Si surface.

- when the surface potential of the gate reaches the bulk Fermi potential, s = − F
the surface inversion will be established and an n-channel will form

- this channel forms a path between the Source and Drain

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 Threshold Voltage

• MOSFET under Bias (Inversion)

- we are very interested when an inversion channel forms because it represents when the
transistor is ON

- we define the Gate-Source voltage (VGS) necessary to cause inversion the Threshold Voltage (VT0)

when VGS < VT0 there is no channel so no current can flow between
the Source and Drain terminals

when VGS > VT0 an inversion channel is formed so current can flow between
the Source and Drain terminals

NOTE: We are only establishing the channel for current to flow between the Drain and Source.
We still have not provided the necessary VDS voltage in order to induce the current.

- just as in the MOS inversion, increasing VGS beyond VTO does not increase the surface potential
or depletion region depth beyond their values at the onset of inversion.

It does however increase the concentration of charge carriers in the inversion channel.

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 Threshold Voltage

• Threshold Voltage with Non-Zero Substrate Bias cont…

- the following plot shows an example of threshold dependence on substrate bias for an
enhancement-type, n-channel MOSFET

VT = VT 0 +   ( − 2 F + VSB − − 2 F )

- the threshold voltage increases with Substrate bias. This means as noise gets on the substrate, it
takes more energy to create the channel in the MOSFET. This is a BAD thing… Page
 MOSFET I-V Characteristics

• MOSFET I-V Characteristics

- we have seen how the Gate-to-Source voltage (VGS) induces a channel between the Source and
Drain for current to flow through

- this current is denoted IDS

- remember that this current doesn't flow unless a potential exists between VD and VS

- the voltage that controls the current flow is denoted as VDS

- once again, we start by applying a small voltage and watching how IDS responds

- notice that now we actually have two control variables that effect the current flow, VGS and VDS

- this is typical operating behavior for a 3-terminal device or transistor

- we can use an enhancement n-channel MOSFET to understand the IV characteristics and then
directly apply them to p-channel and depletion-type devices

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Cutoff Region

- when VGS < VT, there is no channel formed between the Drain and Source and hence IDS=0 A

- this region is called the Cutoff Region

- this region of operation is when the Transistor is OFF

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Linear Region

- When VGS > VT, a channel is formed. IDS is dependant on the VDS voltage

- When VDS = 0v, no current flows

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Linear Region

- If VGS > VT and VDS > 0, then a current will flow from the Drain to Source (IDS)

- the MOSFET operates like a voltage controlled resistor which yields a linear relationship
between the applied voltage (VDS) and the resulting current (IDS)

- for this reason, this mode of operation is called the Linear Region

- this region is also sometimes called the triode region (we'll use the term "linear")

- VDS can increase up to a point where the current ceases to increase linearly (saturation)

- we denote the highest voltage that VDS can reach and still yield a linear increase in current
as the saturation voltage or VDSAT

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Linear Region

- when a voltage is applied at VD, its positive charge

pushes the majority charge carriers (holes) that
exist at the edge of the depletion region further
from the Drain.

- as the depletion region increases, it becomes more

difficult for the Gate voltage to induce an inversion layer.
This results in the inversion layer depth decreasing
near the drain.

- as VD increases further, it eventually causes the

inversion layer to be pinched-off and prevents the
current flow to increase any further.

- this point is defined as the saturation voltage (VDSAT)

- from this, we can define the linear region as:

VGS>VT

0 < VDS < VDSAT

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Linear Region

- the Drain to Source current (IDS) is given by the expression:

I DS linear =
u n  Cox W
2 L

  2  (VGS − VT 0 )  VDS − VDS
2

A note on electron mobility (un):
- where:
un relates the drift velocity to the
un = electron surface mobility (units in cm2/V·s) applied E-field
Cox = Unit Oxide Capacitance (units in F/cm2)
W = width of the gate Drift velocity is the average velocity
L = length of the gate that an electron can attain due to an
E-field.

We are interested in Drift Velocity

- remember this expression is only valid when : because it tells us how fast the electron
can get from the Source to the Drain.
VGS>VT
Since current is defined as I=∆Q/ ∆t, un
relates how much charge can move
0 < VDS < VDSAT in a given area per-time and per E-field

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Linear Region

- what is linear about this equation?

I DS linear =
u n  Cox W
2 L

  2  (VGS − VT 0 )  VDS − VDS
2


- most of the parameters are constants during evaluation. They are sometimes lumped into single
parameters
k ' = u n  Cox I DS linear =
2 L

  2  (VGS − VT 0 )  VDS − VDS
k' W 2


 
W
k = u n  Cox  I DS linear =
k
 2  (VGS − VT 0 )  VDS − VDS
2
or L 2

- Notice that W and L are parameters that the designers have control over. Most of the other
parameters are defined by the fabrication process and are out of the control of the IC designer.

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Linear Region

- what is linear about this equation?

I DS linear =
k
2

 2  (VGS − VT 0 )  VDS − VDS
2


For a fixed VGS, VDS2 has a smaller effect on IDS

then at low values of VDS since it is
IDS depends on VDS not multiplied by anything

- the -VDS2 term alters the function shape in the

linear region. As it becomes large enough
to significantly decrease IDS in this function,
the transistor enters saturation and this
expression is no longer valid.

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Linear Region

- since we know what the current will not decrease as VDS increases past VDSAT, we can use
this expression to define VDSAT:

I DS linear =
k
2

 2  (VGS − VT 0 )  VDS − VDS
2


- when VDS>(VGS-VT), then IDS in this expression

begins to decrease

- we can then define VDSAT = (VGS-VT)

- so now we have the formal limits on the linear

region and the validity of this expression:
Linear Region : VGS>VT

0 < VDS < (VGS-VT)

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : Saturation Region

- a MOSFET is defined as being in saturation when:

Saturation Region : VGS > VT

VDS > (VGS-VT)

- an increase in VDS does not increase IDS because the channel is pinched-off

- However, an increase in VGS DOES increase IDS by increasing the channel depth and hence
the amount of current that can be conducted.

- measurements on MOSFETS have shown that the dependence of IDS on VGS tends to
remain approximately constant around the peak value reached for VDS=VDSAT

- a substitution of VDS=(VGS-VT0) yields: I DS sat =

k
2

 2  (VGS − VT 0 )  (VGS − VT 0 ) − (VGS − VT 0 )
2

=  (VGS − VT 0 )
k 2
I DS sat
2

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 MOSFET I-V Characteristics

• MOSFET I-V Characteristics : IV Curves

- now we have 1st order expressions for all three regions of operation for the MOSFET

Region Conditions IDS

I DS cutoff = 0
Cutoff VGS < VT

I DS linear =
k
2

 2  (VGS − VT 0 )  VDS − VDS
2

Linear VGS > VT
VDS < (VGS-VT)
 (VGS − VT 0 )
k
I DS sat =
2

2
Saturation VGS > VT
VDS > (VGS-VT)

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 MOSFET I-V 2nd Order Effects

• Channel Length Modulation

- the 1st order IV equations derived earlier are not 100% accurate. They are sufficient for 1st
order (gut-feel) hand calculations

- we can modify these IV equations to include other effects that alter the IV characteristics of a
MOSFET

- Channel Length Modulation refers to additional IDS current that exists in the saturation mode
that is not modeled by the 1st order IV equations

- when the channel is pinched off in saturation

by a distance ΔL, a depletion region is created
next to the Drain that is ΔL wide

- given enough energy, electrons in the inversion

layer can move through this depletion region
and into the Drain thus adding additional
current to IDS

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 MOSFET I-V 2nd Order Effects

• Channel Length Modulation

- we can model this additional saturation current by multiplying the IDS expression by:

(1 +  VDS )

- λ is called the channel length modulation coefficient and is determined via empirical methods

- this term alters the IDSSAT expression to be:

 (VGS − VT 0 )  (1 +   VDS )
k
I DS sat =
2

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 MOSFET I-V 2nd Order Effects

• Substrate Bias Effect

- another effect that the 1st order IV equations don't model is substrate bias

- we have assumed that the Silicon substrate is at the same potential as the Source of the MOSFET

- if this is not the case, then the Threshold Voltage may increase and take more energy to induce
a channel

- we've already seen how we can model the change in threshold voltage due to substrate bias:

VT = VT 0 +   ( − 2 F + VSB − − 2 F )

- for the IV equations to accurately model the substrate bias effect, we must use VT instead of VT0

I DS linear =
k
2

 2  (VGS − VT )  VDS − VDS
2

 (VGS − VT )  (1 +   VDS )
k
I DS sat =
2

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 Scaling Theory

• What is Scaling?

- Moving VLSI designs to new fabrication processes

- Shrinking the size of the circuitry

1961 2001 2006

First Planar Integrated Circuit Pentium 4 Processor Itanium 2 Dual Processor
Two Transistors 42 Million Transistors 1.7 Billion Transistors

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 Scaling Theory

• Why do we Scale?

1) Improve Performance
• More complex systems

2) Increase Transistor Density

• Reduce cost per transistor & size of system 300mm wafer

3) Reduce Power
• Smaller transistors require less supply voltage

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 Scaling Theory

• Scaling Predictions

- In 1965, Gordon Moore of Intel predicted the exponential growth of

the number of transistors on an IC.

- Transistor count will doubled every 2-3 years

- Predicting >65,000 transistors in 1975

Moore’s Prediction
(1965)

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 Scaling Theory

• More than just a prediction

- Transistor count has doubled every 26 months for the past 30 years

- Today this trend is used to target future process performance and prepare necessary infrastructure
(Design Tools, Test, Manufacturing, Engineering Skills, etc…)

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 Scaling Theory

• Timeline of Major Events

2006

Intel Ships 1st Billion Transistor uP

1971

1968 Intel Introduces the 4004, 1st single chip uP

(2300 transistors)

Noyce and Moore Form Intel

1958

First Integrated Circuit (Noyce/Fairchild & Kilby/Texas Instruments)

1947

First Transistor (Bell Labs)

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 Scaling Theory

• How much can we shrink?

- Chip Area (A)

A 
1
1
S

( 1S )( 1S )
X Y
1
1 A 
S

Chip Area for a Circuit (A) scales following : 1

S2
Note: In addition, the die sizes have increased steadily, allowing
more transistors per die

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 Full Scaling

• Full Scaling (Constant-Field)

- Reduce physical size of structures by 30% in the subsequent process

W = Width of Gate
L = Length of Gate
tox = thickness of Oxide
xj = depth of doping

- Reduce power supplies and thresholds by 30%

- we define: S ≡ Scaling Factor > 1

- Historically, S has come in between 1.2 and 1.5

for the past 30 years

- sometimes we use √2 = 1.4 for easy math

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 Full Scaling

• Full Scaling (Constant Field)

- The following quantities are altered during fabrication

- we use a prime (‘) to denote the new scaled quantity

Before After
Quantity Scaling Scaling
Channel Length L L’ = L/S
Channel Width W W’ = W/S
Gate Oxide Thickness tox tox’ = tox/S
Junction depth xj xj’ = xj/S
Power Supply Voltage VDD VDD’ = VDD/S
Threshold Voltage VT0 VT0’ = VT0/S
Doping Densities NA NA’ = NA•S

- Note that the doping concentration has to be increased to keep achieve the desired Fermi level
movement due to doping since the overall size of the junction is reduced Page
 Full Scaling

• Scaling Effect on Device Characteristics : Linear Region

 ox  ox  ox +
- by scaling tox, we change Cox : Cox' = '
= =S = S  Cox
t tox tox
ox
S
ID VDS
-
W W
k = u n  Cox  k ' = u n  Cox'  = S  k
L L

- The voltages VGS, VTO, and VDS also scale down by S, which creates a1/S2 in this expression:

I DS linear =
k
2

 2  (VGS − VT 0 )  VDS − VDS
2
 I DS
'

linear
=
S k 1
2 S

 2 2  (VGS − VT 0 )  VDS − VDS
2


- which results in: I DS linear

'
I DS =
linear
S
IDSlin scales down by S, this is what we wanted!!!

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 Full Scaling

• Scaling Effect on Device Characteristics : Saturation Region

- again, k effects IDS

+
ID VDS
S k 1
=  (VGS − VT 0 )  I DS ( )
k
=   −
2 ' 2
I DS SAT VGS VT0
2 SAT
2 S2 -

- which gives I DS SAT

'
I DS =
SAT
S

IDSsat scales down by S, this is what we wanted!!!

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 Full Scaling

• Scaling Effect on Device Characteristics : Power

- Power in the MOSFET can be described as:

+
ID VDS
P = I DS  VDS
-

- both quantities scale by 1/S

I DS VDS P
P' =  = 2
S S S

Power scales down by S2, this is great!!!

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 Full Scaling

• Scaling Effect on Device Characteristics : Power Density

- Power Density is defined as the power consumed per area

+
ID VDS
- this is an important quantity because it shows how much heat
is generated in a small area, which can cause reliability problems -
P
PDensity =
Area

- Power scales by 1/S2

- Area scales by 1/S2 (because W and L both scale by S and Area=W∙L)

- this means that the scaling cancels out and the Power Density remains constant

This is OK, but can lead to problems when IC’s get larger in size
and the net power consumption increase

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 Constant-Voltage Scaling

• Constant-Voltage Scaling

- sometimes it is impractical to scale the voltages

- this can be due to:

1) existing I/O interface levels

2) existing platform power supplies
3) complexity of integrating multiple
power supplies on chip

- Constant-Voltage Scaling refers to scaling the physical quantities (W,L,tox,xj,NA) but

leaving the voltages un-scaled (VT0, VGS, VDS)

- while this has some system advantages, it can lead to some unwanted increases in
MOSFET characteristics

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 Constant-Voltage Scaling

• Scaling Effect on Device Characteristics : Linear Region

- we’ve seen that scaling tox, W, and L causes:

+
k'= S  k
ID VDS
- if the voltages (VGS, VT0, and VDS) aren’t scaled, then the IDS expression -
in the linear region becomes:
'
I DS linear
S k
2

 2  (VGS − VT 0 )  VDS − VDS
2


- which results in: '

I DS linear
= S  I DS linear

IDSlin actually increases by S when we get smaller,

this is NOT what we wanted!!!

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 Constant-Voltage Scaling

• Scaling Effect on Device Characteristics : Saturation Region

- this is also true in the saturation region:

+
ID VDS
S k
=  (VGS − VT 0 )
' 2
I DS SAT
2 -

- which results in: '

I DS SAT
= S  I DS SAT

IDSSAT also increases by S when we get smaller,

this is NOT what we wanted!!!

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 Constant-Voltage Scaling

• Scaling Effect on Device Characteristics : Power

- Instantaneous Power in the MOSFET can be described as:

+
ID VDS
P = I DS  VDS
-

- but in Constant-Voltage Scaling, IDS increases by S and VDS remains constant

P ' = S  I DS  VDS = S  P

Power increases by S as we get smaller,

this is not what we wanted!!!

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 Constant-Voltage Scaling

• Scaling Effect on Device Characteristics : Power Density

- Power Density is defined as the power consumed per area

+
ID VDS
- we’ve seen that Power increases by S in Constant-Voltage Scaling
-
- but area is still scaling by 1/S2

S P
'
PDensity = = S3  P
 Area 
 
 2 
S

- This is a very bad thing because a lot of heat is being generated in a small area

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 Scaling Choices

• So Which One Do We Choose?

- Full Scaling is great, but sometimes impractical.

- Constant Voltage can actually be worse from a performance standpoint

Full Constant-V
Quantity Scaling Scaling
Cox' S S
IDS' 1/S S
Power' 1/S2 S
Power Density' 1 S3

- We actually see a hybrid approach. Dimensions tend to shrink each new generation. Then the
voltages steadily creep in subsequent designs until they are in balance. Then the dimensions
will shrink again.

- Why scale if it is such a pain?

.
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 Scaling Trends

• How Does Scaling Effect AC Performance?

- Assume Full Scaling

- Resistance (R) R 
+
Ids
( 1S )
VDD
VDD
- I ds R 
( 1S )

Device Resistance (R) remains constant : 1

OK

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 Scaling Trends

• How Does Scaling Effect AC Performance?

- Total Gate Capacitance (C)

C 

W L
tox
C  ( 1S )  ( 1S )
( 1S )

Gate Capacitance (C) scales following : 1

S

Good!

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 Scaling Trends

• How Does Scaling Effect AC Performance?

- Gate Delay ()

 
Gate
Source Drain

R C
 ( S)
 1 1

R
Vi Vo
C Gate Delay () scales following : 1/S

Good!

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 Scaling Trends

• How Does Scaling Effect AC Performance?

- Clock Frequency ()

f 
Gate
Source Drain

1

1

f
( )
1
S

Clock Frequency (f) scales following : S

Good!

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 Scaling Trends

• How Does Scaling Effect AC Performance?

- Dynamic Power Consumption (P)

P 
VDD

Ip
C V 2  f
( S ) ( S ) (S )
2
P  1  1

In

Dynamic Power (P) scales following : 1

S2

Great!!!

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 Does Scaling Work?

• How accurate are the predictions?

- For three decades, the scaling predictions have tracked well

10
10
6
Feature Size (m)

1.5
1
1 0.8
0.6
0.35
0.25
0.18
0.13
0.09
0.1

1965 1970 1975 1980 1985 1990 1995 2000 2005

Year

Feature Sizes have been reduced by >30%

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 Does Scaling Work?

• How accurate are the predictions?

Transistor Count has increased exponentially

1,000,000,000

100,000,000
Pentium 4
10,000
Pentium III
10,000,000 Pentium II
Pentium Pro
Transistors

Pentium
Intel486
1,000,000 1,000 4004

Intel386 8008
80286
100,000 8080

Clock Speed (MHz)

8086 100 8086

10,000 8080 80286

8008 Intel386
4004
1,000 10 Intel486

Pentium

Pentium Pro/II/III

1 Pentium 4
1970 1975 1980 1985 1990 1995 2000

Year

1970 1975 1980 1985 1990 1995 2000 2005

Year

Clock Rates have improved >43%

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 Can We Keep Scaling?

• Why not just keep scaling?

- If it was easy, we wouldn’t have jobs!

- each time we get smaller, a couple new major problems arise.

- Over the years, we have a list of issues

that we call “Small Geometry Effects” that
have posed a barrier to future scaling.

- But until now, all of the problems have been

solved with creative engineering and we
continue on to the next process.

- You will need to solve the problems

in the next generation of process
sizes.

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 Small Geometry Challenges

Subthreshold Leakage

- we’ve stated that when VGS<VT, there is no inversion in the channel and hence, no
charge carriers to carry current from the Drain to Source

- this transition from no-inversion to inversion doesn’t happen instantaneously

- there is a small amount of current that does flow when VGS<VT.

- we call this current Subthreshold leakage current.

- as devices get smaller, this current has become a non-negligible quantity.

I ds

1 mA Saturation Vds = 1.8

Sub- Region
- current in this region follows the relationship: 100 A
threshold
10 A Region
Vgs −Vt −Vds
  1 A
I ds = I ds 0e nvT
1 − e
vT
 100 nA
 
 
10 nA
Sub-
1 nA threshold
100 pA Slope
10 pA Vt

0 0.3 0.6 0.9 1.2 1.5 1.8

Vgs

- lowering the VT0 makes this problem worse

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 MOSFET Capacitance

• MOSFET Capacitance

- We have looked at device physics of the MOS structure

- We have also looked at the DC I-V characteristics of the MOS Transistors

- We have not looked at AC performance

- Capacitance is the dominating imaginary component on-chip

(i.e., we don't really have inductance)

- the Capacitances of a MOSFET are considered parasitic

- "parasitic" means unwanted or unintentional. They are unavoidable and a result of fabricating
the devices using physical materials.

- we can use the capacitances of the MOSFET to estimate factors such as rise time, delay,
fan-out, and propagation delay

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 MOSFET Capacitance

• MOSFET Capacitance

- Capacitance = Charge / Volt = (C/V)

- as we've seen, the charge in a semiconductor is a complex, 3-dimensional, distribution due to the
materials, doping, and applied E-field

- we develop simple approximations for the MOSFET capacitances for use in hand calculations

- we define each of the following lumped capacitance

for an AC model of the transistors

- each capacitance will have multiple contributions and

different values depending on the state of
the transistor (i.e., cutoff, linear, saturation)

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 MOSFET Capacitance

• MOSFET Dimensions

- We need to define the geometric parameters present in the MOSFET structure

Mask Length

- we draw a gate length during

fabrication

- we call this the Drawn Length, LM

- in reality, the diffusion regions extend

slightly under the gate by a distance, LD

- this is called overlap

- the actual gate length (L) is given by:

L = LM − 2  LD

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 MOSFET Capacitance

• MOSFET Dimensions

W = Channel Width
tox = Oxide thickness
xj = diffusion region depth
Y = diffusion region length

• Channel-Stop Implants

- in order to prevent the n+ diffusion regions

from adjacent MOSFETS from influencing
each other, we use "channel-stop implants"

- this is a heavily doped region of opposite

typed material (i.e., p+ for an n-type)

- these electrically isolate each transistor

from each other

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 MOSFET Capacitance

• MOSFET Capacitance

- We group the various capacitances into two groups

1) Oxide Capacitances - capacitance due to the Gate oxide

2) Junction Capacitances - capacitance due to the Source/Drain diffusion regions

Oxide Capacitances

Junctions Capacitances

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 Oxide-Related Capacitance

• Oxide-Capacitance

- Oxide Capacitance refers to capacitance which uses the gate oxide as the insulator between
the parallel plates of the capacitor

- as a result, these capacitances always use the Gate as one of the terminals of the capacitor

- we are concerned with the following capacitances:

Cgb = Gate to Body capacitance

Cgd = Gate to Drain capacitance
Cgs = Gate to Source capacitance

- again, each of these values will differ depending on the mode of operation of the MOSFET

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 Oxide-Related Capacitance

• Overlap Capacitance

- capacitance from the Gate to the Source/Drain due to the overlap region (LD)

- this creates: C gs (overlap ) = Cox  W  LD

C gd (overlap ) = Cox  W  LD

- where Cox is the unit-area capacitance (i.e., multiply by area to find total capacitance, F/m2 or F/um2)
 ox
Cox =
tox
- NOTE : this capacitance does NOT depend on the external bias of the MOSFET since the Gate
and the Source/Drain do not have their carrier density altered during bias.

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 Oxide-Related Capacitance

• Gate-to-Channel Capacitance

- the gate-to-channel configuration results in 3 capacitances (Cgb, Cgs, Cgb)

- these capacitances change as a result of external bias since in effect, the "bottom plate" of the
capacitor is being moved around during depletion/inversion

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 Oxide-Related Capacitance (Cut-Off)

• Gate to Source Capacitance (Cgs) : Cut-Off

- During Cut-off, there is no channel beneath the Gate.

- since there is no channel that links the Gate to the Source (i.e., no ΔQ),
there is no Gate-to-Channel capacitance.
No "bottom plate" in the channel region to
connect to the Source n+ conductor

- this leaves the overlap capacitance as the only component to Cgs in cut-off:

C gs( cut −off ) = Cox  W  LD

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 Oxide-Related Capacitance (Cut-Off)

• Gate to Drain Capacitance (Cgd) : Cut-Off

- Just as Cgs, during Cut-off, there is no channel beneath the Gate.

- since there is no channel that links the Gate to the Drain (i.e., no ΔQ),
there is no Gate-to-Channel capacitance.
No "bottom plate" in the channel region to
connect to the Drain n+ conductor

- this leaves the overlap capacitance as the only component to Cgd in cut-off:

C gd ( cut −off ) = Cox  W  LD

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 Oxide-Related Capacitance (Cut-Off)

• Gate to Body Capacitance (Cgb) : Cut-Off

- There is a capacitor between the Gate and Body

- The bottom plate is the conductor formed by the p-type silicon since it has majority
charge carriers and acts as a conductor

- we can describe the Gate-to-Body Capacitance as:

C gb( cut −off ) = Cox  W  L

- remember that L = (LM-2·LD)

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 Oxide-Related Capacitance (Linear)

• Gate to Source Capacitance (Cgs) : Linear Region

- When operating in the linear region, a channel is present in the substrate.

- this can be thought of as a conductor (or metal plate) that contacts the Source and Drain

- this results in a capacitance between the Gate and the Source/Drain

- we split this capacitance between the Source and Drain for simplicity

- the Gate-to-Channel contribution to CGS is (1/2)CoxWL

- the total CGS capacitance in the linear region includes the overlap capacitance:

1
C gs( linear ) =  Cox  W  L + Cox  W  LD
2
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 Oxide-Related Capacitance (Linear)

• Gate to Drain Capacitance (Cgd) : Linear Region

- The Gate-to-Drain Capacitance is identical to the Gate-to-Source Capacitance in the Linear region:

1
C gd ( linear ) =  Cox  W  L + Cox  W  LD
2

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 Oxide-Related Capacitance (Linear)

• Gate to Body Capacitance (Cgb) : Linear Region

- Since the channel (inversion layer) looks like a metal plate to the gate, the Gate can't actually
see the substrate anymore

- this means that the capacitance between the Gate and Body is zero when a channel is present

C gb( linear ) = 0

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 Oxide-Related Capacitance (Saturation)

• Gate to Source Capacitance (Cgs, Cgd, Cgb) : Saturation Region

- When operating in the saturation region, the channel is pinched off

- We can make the assumptions that:

1) There is no longer a link between the Gate and Drain

2) Roughly 2/3 of the channel is still present linking the Gate to the Source (2L/3)
3) The pinched off channel still effectively shields the gate from the body

- from these approximations, we can describe the capacitances in the saturation region
2
C gs( sat ) =  Cox  W  L + Cox  W  LD
3
C gd ( sat ) = Cox  W  LD

C gb( sat ) = 0
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 Oxide-Related Capacitance (Summary)

• Summary of Oxide-Related Capacitance

Cut-off Linear saturation

1 2
C gs( cut −off ) = Cox  W  LD C gs( linear ) =  Cox  W  L + Cox  W  LD C gs( sat ) =  Cox  W  L + Cox  W  LD
2 3

C gd ( cut −off ) = Cox  W  LD 1 C gd ( sat ) = Cox  W  LD

C gd ( linear ) =  Cox  W  L + Cox  W  LD
2

C gb( cut −off ) = Cox  W  L C gb( linear ) = 0 C gb( sat ) = 0

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 Oxide-Related Capacitance (Total)

• Total of Oxide-Related Capacitance

- if we assume that these three capacitances are in parallel, then their total values add:

Coxide = C gs + C gd + C gb

- the lowest oxide-related capacitance that is present is in the saturation region:

 Cox  W  L + 2  Cox  W  LD = 0.66  Cox  W  (L + 3  LD )

2
Coxide(min) =
3

- the largest oxide-related capacitance that is present is in the cut-off & the linear regions:

Coxide(max) = Cox  W  (L + 2  LD )

- for quick hand-calculations, we can use the largest oxide capacitance to find a worst-case value
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 Junction Capacitance

• Junction Capacitance

- Junction Capacitance refers to capacitance between the diffusion regions of the Source & Drain
to the doped substrate surrounding them.

- they are called "junction" because these capacitances are due to the PN junctions that are formed
between the two materials

- we are concerned with the following junction capacitances:

Csb = Source to Body capacitance

Cdb = Drain to Body capacitance

- these capacitances are highly dependant on the bias voltages since the effective distance between
plates is the depth of the built in depletion region that forms at the PN junction

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 Junction Capacitance

• Junction Capacitance

- the Source and Drain regions will have similar geometries so we will start by describing
the PN junctions for only one region

- Consider the numbers in the following figures illustrating the PN junctions that exist

- Let's start with an N-type MOSFET and identify all of PN junctions

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 Junction Capacitance

• Junction Capacitance

- remember that the MOSFET is surrounded by a channel-stop implant to prevent the diffusion
regions from coupling to other MOSFETs.

- This implant is heavily doped (p+), usually 10·NA.

- These areas are also called sidewalls

- remember that the diffusion regions are heavily doped (n+)

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 Junction Capacitance

• Junction Capacitance

1) n+ / p junction = diffusion region to substrate beneath gate

2) n+ / p+ junction = diffusion region to channel-stop implant in back (sidewall)

3) n+ / p+ junction = diffusion region to channel-stop implant on side (sidewall)

4) n+ / p+ junction = diffusion region to channel-stop implant in front (sidewall)

5) n+ / p junction = diffusion region to substrate underneath

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 Junction Capacitance

• Junction Capacitance

- the capacitance will be proportional to the area of the junction

1) Area = W·xj

2) Area = Y·xj

3) Area = W·xj

4) Area = Y·xj

5) Area = W·Y

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79

MOSFET Capacitances Junction Capacitance Geometry

The Geometry
Y

xj
G
D
W

Junction between p substrate and n+ drain (Bottom)

Area: W(Y+xj) = AD

Junction between p+ channel stop and n+ drain

(Sidewalls)
Area: xj(W+2Y) = xj PD

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 Junction Capacitance

• Junction Capacitance

- first we need to express the capacitance for an abrupt, PN junction under reverse-bias

- we begin with finding the depletion region thickness

- this is similar to the expression for depletion thickness of a MOS structure, except that the
region will protrude into both materials instead of just the semiconductor as before.
N A  ND
- as a result, the carrier concentration of both materials is now described:
NA + ND
- the depletion thickness is given by:

2   Si N A + N D
xd pn =   (0 − V )
q N A  ND

- where the built in junction potential is given by:

kB T  N A  ND 
0 =  ln  2


q  ni 
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 Junction Capacitance

• Junction Capacitance

- the depletion-region charge (Qj) can be written as:

 N N 
Q j = A  q   A D   xd pn
 N A + ND 

- substituting xdpn and rearranging terms, we get:

 N N 
Q j = A  2   Si  q   A D   (0 − V )
 N A + ND 

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 Junction Capacitance

• Junction Capacitance

- the capacitance of the junction is defined as:

dQ j
Cj =
dV

- we can differentiate our expression for junction charge with respect to voltage to get
the capacitance as a function of junction voltage:

 
Cj =
dQ j
=
d  A  2    q   N A  N D 
  (0 − V ) 
 Si N +N 
dV dV
  A D  

 Si  q  N A  N D 
C j (V ) = A      (0 − V )
2  N A + ND 

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 Junction Capacitance

• Junction Capacitance

- from this expression, we can define the zero-bias junction capacitance per unit area:

 Si  q  N A  N D  1
C j0 =    
2  N A + N D  0

- putting this back into a more generic expression for Cj(V), we get:

A  C j0
C j (V ) =
V
1−
0

- remember that we are assuming an "abrupt" PN junction

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 Junction Capacitance

• Junction Capacitance

- since the total capacitance depends on the external bias voltage, it can be a complicated
to find the equivalent capacitance when the bias voltage is a transient.

- we need to make an assumption to simplify the expression.

- let's assume that the voltage change across the junction is linear. Then we can find the equivalent
or average capacitance using:

Q Q j (V2 ) − Q j (V1 )
Ceq = =
V V2 − V1

2V

  C j (V )  dV
1
Ceq =
V2 − V1 V1

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 Junction Capacitance

• Junction Capacitance

- substituting in our expression for Cj(V), we get:

2  A  C j 0  0  V2 V1 
Ceq = −  1− − 1− 
(V2 − V1 )  0 0 

- which we can simplify even further by defining a dimensionless coefficient Keq

Ceq = A  C j 0  K eq

K eq = −
2  0
(V2 −V )
( 0 − V2 − 0 − V1 )
1

- where Keq is the voltage equivalence factor (0<Keq<1):

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 Junction Capacitance

• Junction Capacitance

- How do we use this?

- for a given diffusion region, we calculate Ceq for each of the 5 PN junctions

- note that there really are only two different regions (n+ / p and n+ / p+)

- the sidewalls (2,3,4) will have their own zero-bias junction capacitance since
they have a unique carrier concentration (i.e., n+ / p+).

- the inner and bottom junctions (1,5) will have their own zero-bias junction
capacitance since they have a unique carrier concentration (i.e., n+ / p).

- when solving for the sidewall contribution, you can add the areas for 2,3,4 and
solve once

- when solving for the inner and bottom junction contributions, you can add the
areas for 1 and 5 and solve once

- since this is a reverse biased PN junction the voltages for V1 and V2 are actually
negative when plugged into the Keq expression

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 Junction Capacitance

• Junction Capacitance

- What's the difference between the Source and Drain?

- If the Source is grounded, then there is no voltage change across it. This means
its capacitance is simply the zero-bias capacitance

- you will still need to calculate the sidewall and inner/bottom Cj0 capacitances separately

- the drain typically sees a voltage change (VDS). However, one good thing is that
typically the source voltage is 0v, so the expression simplifies somewhat

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 Junction Capacitance

• Junction Capacitance

- Doesn't this take a lot of time?

- Yes! And remember that we have made a lot of assumptions along the way

- For this reason, we typically rely on computer models of the capacitance

- We do the hand calculations to get a gut feel for what factors affect capacitance

- Gut Feel makes for good designers because design is about balancing trade-offs

- If you don’t have Gut Feel and rely totally on simulators, you will struggle when asked to
innovate and trouble-shoot.

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