VLSI DESIGN

by
Dr.Dibyendu Roy
Ph.D (IIT Kharagpur)
 Transistor Types
 Bipolar transistors
 npn or pnp silicon structure
 Small current into very thin base layer controls large
currents between emitter and collector
 Base currents limit integration density

 Metal Oxide Semiconductor Field Effect Transistors

 nMOS and pMOS MOSFETS
 Voltage applied to insulated gate controls current between
source and drain
 Low power allows very high integration
 First patent in the ’20s in USA and Germany
 Not widely used until the ’60s or ’70s
 MOS Transistors
• Four terminal device: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors (body is also called the substrate)
– SiO2 (oxide) is a “good” insulator (separates the gate from the body
– Called metal–oxide–semiconductor (MOS) capacitor, even though gate is
mostly made of poly-crystalline silicon (polysilicon)

Source Gate Drain

Polysilicon Source Gate Drain
Polysilicon
SiO 2
SiO2

n+ n+
p+ p+
p bulk Si
n bulk Si

NMOS PMOS
 NMOS Operation
• Body is commonly tied to ground (0 V)
• Drain is at a higher voltage than Source
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body “diodes” are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
 NMOS Operation Cont.
• When the gate is at a high voltage: Positive charge on gate
of MOS capacitor
– Negative charge is attracted to body under the gate
– Inverts a channel under gate to “n-type” (N-channel, hence
called the NMOS) if the gate voltage is above a threshold voltage
(VT)
– Now current can flow through “n-type” silicon from source
through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
 PMOS Transistor
• Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Drain is at a lower voltage than the Source
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO 2

p+ p+
n bulk Si
 Power Supply Voltage
• GND = 0 V
• In 1980’s, VDD = 5V
• VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
• Effective power supply voltage can be lower
due
to IR drop across the power grid.
 Digression: Silicon Semiconductors

• Modern electronic chips are built mostly on silicon substrates

• Silicon is a Group IV semiconducting material
• crystal lattice: covalent bonds hold each atom to four neighbours.

Si Si Si

Si Si Si

Si Si Si

http://onlineheavytheory.net/silicon.html
 Dopants
• Silicon is a semiconductor at room temperature
• Pure silicon has few free carriers and conducts poorly
• Adding dopants increases the conductivity drastically
• Dopant from Group V (e.g. As, P): extra electron (n-type)
• Dopant from Group III (e.g. B, Al): missing electron, called
hole (p-type)

Si Si Si Si Si Si
- +
+ -
Si As Si Si B Si

Si Si Si Si Si Si
 p-n Junctions
• First semiconductor (two terminal) devices
• A junction between p-type and n-type
semiconductor forms a diode.
• Current flows only in one direction
p-type n-type

anode cathode
 VLSI DESIGN

In this course you will learn the

following

Basic MOS Structure

Types of MOSFET
MOSFET I-V Modelling
VLSI DESIGN FLOW
System architecture

Functional specification
Functional verification

Logic design
Logic verification

Circuit design
Circuit verification

Physical design
Physical verification

Fabrication
Packaging and Testing
 VLSI DESIGN

1. Why VLSI? 3. Why CMOS ?

ans:- ans:-
• Small Physical size•Best switching speed
•Low power
•Higher speed
•Low area
•Lower power •Easy scaling to less
•Low cost device
•Low Feb cost

2. Why Si (than Germanium)?

ans:-
•Wide band gap
•Sustained high temperature
•Can be oxidized easily.
 Gate

Source Drain
Metal
Oxide
n+ + + + + + + + n+
+ + + + + +

+ +
Substrate (P –type)

Accumulation [VGS<0]
VGS-Ve -
 Gate
Source Drain
Metal
Oxide
n+ n+

+ + +

Depletion [0<VGS<Vt]
VGS-Ve +
 Inversion

Gate
Source Drain
Metal
Oxide
n+ - - - - - - - n+
- - - - - -
[VGS>Vt]
- -
VGS-Ve ++
MOSFET I-Vs

ECE 663
 Operation of a transistor
VSG > 0
n type operation

VSG
Gate VSD
Insulator
Source Drain
More Channel
electrons
Substrate

Positive gate bias attracts electrons into channel

Channel now becomes more conductive
VLSI DESIGN
 VLSI DESIGN
MOSFETs are divided into two types viz. p-MOSFET and n-MOSFET
depending upon its type of source and drain.

The combination of a n-MOSFET and a p-MOSFET (as shown in figure 3.21)

is called cMOSFET which is the mostly used as MOSFET transistor. We will
look at it in more detail later.
 VLSI DESIGN
Symbols
D D

B B
G G

S S

p Channel MOSFET n Channel MOSFET

 VLSI DESIGN

The output characteristics plotted for few fixed values of for p-MOSFET and
n-MOSFET are shown next :

The transfer characteristics of both p-MOSFET and n-MOSFET are plotted

for a fixed value of as shown next :
VLSI DESIGN
Current FLOW and PINCHOFF
of mosfet
 VLSI DESIGN
Analysis: Saturation (C)
Pinch-off

VDS (sat)  VGS  VT

Substitute for VDS(sat) in equation for IDS to get IDS(sat)

W   VDS2 
I DS  n  COx  (VGS  VT )VDS  
L  W   2 (VGS  VDS ) 
2
2 
I DS ( sat)  n  COx  (VGS  VT )  
L  2 
n  W 
  COx VGS  VT 
2

2 L
 constant
 What’s Pinch off?

V0G V0G VG VG

0 0 0 VD

Now add in the drain voltage to drive a current. Initially you get an
increasing current with increasing drain bias

When you reach VDsat = VG – VT, inversion is disabled at the drain end
(pinch-off), but the source end is still inverted
The charges still flow, just that you can’t draw more current
with higher drain bias, and the current saturates
V0G V0G

0 0

VC (Y=0) = Vs=
0
VC (Y=L) = VDs
Getting the inverter output

ON

Gain

OFF
ECE 663
 ID
gD  0
VD V
G

I D
 nCi VG  VT 
w
gm 
VG V L
D

What’s the gain here?

ECE 663
Resistive load inverter
Resistive load inverter
Resistive load inverter
Resistive load inverter
 Resistive load inverter
Resistive load inverter
Resistive load inverter
CMOS INVERTER
CMOS INVERTER
CMOS INVERTER
CMOS INVERTER
CMOS INVERTER
CMOS INVERTER
CMOS INVERTER
CMOS INVERTER
CMOS INVERTER

2
 CMOS INVERTER

Also calculate the power rating of the MOS Transistor with load
resistance.