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Ece3002 Vlsi System Deign Cocob 2019

This document describes a VLSI System Design course. The course has 3 hours of lectures and 2 hours of practical sessions per week over 4 credits. The objectives are to understand MOS device characteristics, CMOS logic styles, fabrication processes, and use EDA tools to design combinational and sequential circuits. The course outcomes include understanding MOS transistors, designing CMOS logic gates, calculating power and delay, understanding fabrication impacts, and designing circuits using EDA tools. The course is divided into 8 modules covering topics such as MOS transistors, CMOS logic, circuit characterization, fabrication, and sub-system design. Student learning is evaluated through tests, assignments, and challenging experiments using EDA tools.

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Debasis Chandra
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246 views3 pages

Ece3002 Vlsi System Deign Cocob 2019

This document describes a VLSI System Design course. The course has 3 hours of lectures and 2 hours of practical sessions per week over 4 credits. The objectives are to understand MOS device characteristics, CMOS logic styles, fabrication processes, and use EDA tools to design combinational and sequential circuits. The course outcomes include understanding MOS transistors, designing CMOS logic gates, calculating power and delay, understanding fabrication impacts, and designing circuits using EDA tools. The course is divided into 8 modules covering topics such as MOS transistors, CMOS logic, circuit characterization, fabrication, and sub-system design. Student learning is evaluated through tests, assignments, and challenging experiments using EDA tools.

Uploaded by

Debasis Chandra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Course Code Course Title L T P J C

ECE3002 VLSI SYSTEM DESIGN 3 0 2 0 4


Prerequisite: ECE2003 Digital Logic Design

Course Objectives:
1. To understand MOS device characteristics and to implement simple gates using CMOS
logic style with delay and power constraints
2. To understand the CMOS fabrication process styles including layout design rules
3. To design combinational and sequential circuits using different logic styles
4. To use modern EDA tools to simulate and synthesize VLSI circuits
Expected Course Outcome:
1. Clear understanding fundamental concepts of MOS transistors
2. Ability to design simple logic gates using CMOS logic style
3. Ability to calculate power and delay of simple CMOS circuits
4. Understanding of fabrication processes and their impact on the circuit performance
5. Ability to design and validate combinational and sequential circuits using different logic
styles
6. Ability to design VLSI circuits at sub-system abstraction level
7. Ability to use modern EDA tools to design VLSI circuits

Student Learning Outcomes (SLO): 2,5,14

Module:1 MOS Transistor Theory: 5 hours SLO: 2


I-V Characteristics, C-V Characteristics, Non ideal I-V effects of MOS Transistors

Module:2 CMOS Logic: 5 hours SLO: 2


Basic gates, Compound Gates, Transmission Gates based combinational and sequential logic
design

Module:3 CMOS Circuit characterization and 8 hours SLO: 2


Performance Estimation :
DC transfer Characteristics of CMOS inverter, Circuit characterization and performance
estimation: Delay estimation, Logical effort and Transistor Sizing. Power Dissipation: Static &
Dynamic Power Dissipation.

Module:4 CMOS Fabrication and Layout: 5 hours SLO: 5


CMOS Process Technology N-well, P-well process, Stick diagram for Boolean functions using
Euler Theorem, Layout Design Rule

Module:5 CMOS Combinational Circuit Design: 7 hours SLO: 5


Static CMOS, Ratioed Logic, Cascode voltage Switch Logic, Dynamic circuits, Pass Transistor
Circuits
Module:6 CMOS Sequential Circuit Design: 7 hours SLO: 5

Conventional CMOS Latches and Flip Flops, Pulsed Latches, Resettable and Enabled Latches and
Flip Flops

Module:7 Sub System Design: 6 hours SLO: 5

Single bit Adder, Carry look ahead adder, Carry propagate Adder, Magnitude Comparator, Barrel
Shifter, Signed and unsigned multiplier.

Module:8 Contemproray Issues 2 hours

Total Lecture Hours: 45 hours

Text Books:
1. Neil H.Weste, Harris, A. Banerjee, “CMOS VLSI Design, A circuits and System Perspective”,
2014, Fourth Edition, Pearson Education, Noida, India.

Reference Books:
1. Jan M. Rabaey, Anantha Chadrakasan, BorivojeNikolic, “Digital Integrated Circuits: A
Design Perspective”, 2014, Third Edition, Prentice Hall India, New Jersey, US.
2. Yogesh Chauhan, Darsen Duane Lu, Vanugopalan Sriramkumar, Sourabh Khandelwal, Juan
Duarte, NavidPayvadosi, Ai Niknejad, Chenming Hu, “FinFETModeling for IC Simulation
and Design”, 2015, Academic Press, Elsevier.

Mode of Evaluation: Continuous Assessment Test –I (CAT-I), Continuous Assessment Test –II
(CAT-II), Digital Assignments/ Quiz / Completion of MOOC, Final Assessment Test (FAT).

Sl.No. List of Challenging Experiemnts (Indicative): SLO:14


1 i. Cadence EDA Tool Demo & Hands on - Schematic 8 hours
ii. Basic Cell structure (NMOS & PMOS) using conventional MOS
iii. Verification with different corners
iv. Design and Analysis of CMOS circuits
(Analysis: Power, Delay, NM, PDP)
(Design: Sizing)
2 i. Cadence EDA Tool Demo & Hands on – Layout & Post Layout Simulation 8 hours
ii. Basic Cell layout (CMOS)
iii. Fingering and folding
iv. Standard cell design for different technology node
3 i. Adder Design using conventional CMOS 8 hours
ii. Multiplier using conventional CMOS
iii. Memory design (SRAM /DRAM /CAM).
iv. Level converters (Optional)
4 i. ALU Design using conventional CMOS 6 hours
ii. Simple Processor Design using conventional CMOS
Total Laboratory Hours: 30 hours

Mode of Evaluation: Continuous Assessment of Challenging experiments / Final Assessment Test (FAT).
CO – SLO Mapping

Theory:

Module CO SLO

1 CO_01 2
2 CO_02 2

3 CO_03 2
4 CO_04 5

5 CO_05 5
6 CO_05 5

7 CO_06 5

Laboratory:

CO-07 - SLO 14

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