8 7 6 5 4 3 2 1

D
D

I210-AS/IS REFERENCE DESIGN

SERDES-SFP
REFERENCE DESIGN
C C

EXTERNAL INTERFACES PROVIDED:

B - PCIE V2.1 (2.5GT/S) GEN1 X1 B
- SERIALIZER-DESERIALIZER (SERDES) TO SUPPORT 1000BASE-SX/LX (OPTICAL FIBER - IEEE802.3)
- SERIALIZER-DESERIALIZER (SERDES) TO SUPPORT 1000BASE-KX (802.3AP)
AND 1000BASE-BX (PICMIG 3.1) FOR GIGABIT BACKPLANE APPLICATIONS
- SGMII (SERIAL-GMII SPECIFICATION) INTERFACE FOR SFP (SFP MSA INF-8074I)/EXTERNAL PHY CONNECTIONS
- NC-SI (DMTF NC-SI OVER RMII) OR LEGACY SMBUS OR NC-SI OVER MCTP OVER PCI-E
OR SMBUS FOR MANAGEABILITY CONNECTION TO BMC
- IEEE 1149.1 JTAG

A A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 1
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

REVISION CONTROL
R1.90 INITIAL RELEASE (INTEL PUBLIC)
D
D

TABLE OF CONTENTS
1. TITLE PG
2. TOC
C 3. PCI-E & NC-SI I/O C

4. SERDES-SFP LED
5. SUPPORT CIRCUITS
6. POWER SUPPLY TREE
7. POWER SUPPLY & I210 REGULATOR
8. POWER MUX
9. SVR 12V-4V
10.SVR BUCK-BOOST
11.NC-SI PHY
B 12.NC-SI MDI & CLK B

13.TEST I/O & LED

A A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 2
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PCIE_NC-SI_SMB
D
D

V3P3_LAN V12P0_PE_MAIN V3P3_PE_AUX

1 C40 C52
1 22.00UF 1

R121
R122

R107
R108
1
10UF
1 1 1 1 F4 1206LF
F3 6.3V
2
V3P3_LAN 2 X5R
2 2 2 2
2 2 0603LF

10.0K
10.0K
10.0K
10.0K

PE_V3P3_NC
R111

R102
R68

R71

R67

C R132 0 C
1 1 NCSI_ARB_IN IN 13A2>
NCSI_ARB_OUT OUT 13A1<
2 2 R66 0 PE_V12
100K
100K

EU2
10.0K

10.0K
10.0K

I210_AS

24 PE_RP PE_TP 21 PET_P C33 0.1UF PER0_P J1

23 PE_RN PE_TN 20 PET_N 1 22 PER0_N
C341 0.1UF FCONN36_PCI_EXPRESSX1
26 PE_CLKP 2 R105
1 33
2 NCSI_CLK_IN A1 B1
25 NC_SI_CLK_IN IN 12A2> 13A2> PRSNT1A_N 12V1
PE_CLKN 3 A2 B2
NC_SI_CRS_DV 12V3 12V2
NC_SI_TX_EN 7 NCSI_TX_EN IN 11B1> 13A2> A3 12V4 RSVD1 B3
17 PE_RST_N A4 GND35 GND1 B4
16 PE_WAKE_N NC_SI_ARB_IN 43 NCSI_CRS_DV OUT 11B4< 13A2< NC A5 JTAG2 SMCLK B5 SMCLK
NC_SI_ARB_OUT 44 NC A6 JTAG3 SMDAT B6 SMDAT
34 SMB_CLK NC_SI_TXD0 9 NCSI_TXD_0 11B4> 13A2>
NC A7 JTAG4 GND2 B7
NC_SI_TXD1 8 NCSI_TXD_1 IN
11B4> 13A2>
NC A8 JTAG5 3_3V1 B8
36 SMB_DATA IN A9 3_3V2 JTAG1 B9 NC
35 NC_SI_RXD0 6 NCSI_RXD_0 OUT 11B4< 13A2< A10 3_3V3 3_3VAUX B10 PE_V3P3_AUX
SMB_ALRT_N 5 NCSI_RXD_1 A11 B11
NC_SI_RXD1 OUT 11B4< 13A2< PERST* WAKE_N
KEY
B A12 GND36 RSVD2 B12 B
R127 1 1 1 R37 A13 REFCLKP GND3 B13

10.0K
10.0K
A14 REFCLKN B14

10.0K
PETP[0]
2 2 2
A15 GND37 PETN[0] B15
A16 PERP[0] GND4 B16
A17 PERN[0] PRSNT2_N B17
A18 GND38 GND5 B18
R44
PE_CLK_N
PE_CLK_P

13B2> IN PE_RST_N
13B2< OUT PE_WAKE_N
PET0_N
PET0_P
NOTE: PE_(T/R)_N/P INTENTIONALLY SWAPPED FOR ROUTING
13A4< SMBALRT_N R9 1 20
OUT
13A4< SMBD R731 2 0
BI
A 13A4< SMBCLK R741 2 0 A
BI
EMPTY

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 3
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

V3P3_LAN_SUPPORT
SFP_LED_SDP
V3P3_SFP
D
R70 0 D
1 2
1/2W EMPTY * INTERNAL PULL UP
1 R69 1 1 SERDES I2C EXT PU OPTIONAL.
0 L4 L5
3.3UH 3.3UH DS12
2 1/2W

2
2 2 RED

R137

R140
R141
R142
R145
2 Q7 SFP_PWR
SDP0 - SFP_MOD_ABS
SDP1 - SFP_TX_DIS S 1 1
SDP2 - SFP_TX_FAULT C72 C73 1 1 1 1 1

1
SDP3 - SFP_PWR 4.7UF 4.7UF

2
10.0K
SFP_PWR 1

330
R92
10.0K
10.0K
10.0K
10.0K
D FET_P 2 2
2
2 2 2 2
G
3

1
ADD CAGE C18025-003 * *
J22
SCONN20_SFP
NOTE: KX/SFP DATA FLOW DIRECTION. 11 VEER_11 VEER_10 10
C 12 RD- 9 C
13 RS1
RD+
14 RX_LOS 8
VEER_14
EU2 RS0 7
I210_AS VCCR 15 VCCR_15

R146

R147
VCCT 16 VCCT_16 MOD-ABS 6
SDP0 63 SET_P 53 SFP_TD_P 17 5 1 1
13B4< BI SDP0 VEET_17 SCL
SDP1 61 SET_N 52 SFP_TD_N SDA 4
13B4< 13A1> BI SDP1/PCIE_DIS 18 TD+ 3 2
TX_DISABLE
13B4< BI SDP2 62 SDP2 SER_P 50 SFP_RD_P 19 TD-
TX_FAULT 2 0 2 0
13B4< BI SDP3 60 SDP3 SER_N 49 SFP_RD_N 20 1
VEET_20 VEET_1

31 LED0 57 CHASSIS GND

30 I2C_DAT G1 G11
LED1 CGND_1 CGND_11
33 LED2 I2C_CLK 55 G2 CGND_2 CGND_12 G12
G3 CGND_3 CGND_13 G13
R65 R64 G4 CGND_4 CGND_14 G14
1 1 58 NC_58 SRDS_SIG_DET 54 G5 CGND_5 CGND_15 G15
G6 CGND_6 CGND_16 G16
G7 CGND_7 CGND_17 G17
160 2 2160 G8 CGND_8 CGND_18 G18
B G9 CGND_9 CGND_19 G19 B
G10 CGND_10 CGND_20 G20

SDA OUT 13A4<

SCL OUT 13A4<
SIG_DET OUT 13A4<
DS11
1
R139
LED_DUAL_4P
SDP LED AT SFP CAGE 2 470
GREEN
LED0->IF LINKED AT 100BASE-TX THEN LOW. 3 1

LED2->IF LINKED AT 1000BASE-T THEN LOW. 4 2

A LED1->IF LINK UP THEN LOW. YELLOW
V3P3_SFP A
BLINK HIGH FOR ACTIVITY.
DS10
R58 R136
1 2 2 1 1 2
160 GREEN 160

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 4
HILLSBORO, OR 97124
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

SUPPORT CIRCUITS
D
D

Y3 V3P3_LAN
25.000MHZ
V3P3_LAN Y1_P2 2 1 Y1_P1
V3P3_LAN 1
C20 1
C30
27.0PF 27.0PF R103 R97 V3P3_LAN
1588 OPTION 1 R51 1 1

3.3K

3.3K
R96 1 <1PPM OSC COG R78 R76 COG

33K
2 2
3.3K Y4 1 0 1 0 2
2 2
EMPTY
2 25.000MHZ
OSC_10PIN_TXCO U7
2 2
8
7
6

EU2 NONE C25

8
1
PLACE NEAR IC I210_AS
0.1UF
DNC_7
DNC_6
E/D

VCC
9 VCC 5 LAN_CLK_IN 46 5 D
OUT R771 2 XTAL_IN XTAL1
0 XTAL_OUT 45 XTAL2 6 C 2
C C24 1 C83 1 C
1

0.01UF 10 4
1 J13 JTCK 19 15 R164
1 33
2 1 2
DNC_10 GND R94 1 2 JTAG_CLK NVM_CS_N S_N Q
EMPTY
R841 23.3K JTDI 29 R168
1 33
2
15.0PF

JTAG_TDI NVM_SI 12 3
DNC_3
DNC_1

DNC_2

2 W_N
23.3K 33
EMPTY R169
2 2 R1061 JTDO 4 JTAG_TDO NVM_SO 14 1 2
2

GND
R991 23.3K JTMS 18 JTAG_TMS NVM_SK 13 R170
1 33
2 HOLD_N
EMPTY 3.3K
1
2
3

RSET 48 SOCKET_SST25VF040b SOICLF

EMPTY RSET

4
IC
R85 1 2 DEV_OFF_N 28 DEV_OFF_N
R1041 3.3K
2 LAN_PWR_GOOD 1 LAN_PWR_GOOD
3.3K
MISO OUT 13A4<
SS OUT 13A4<

33K
SCLK

R20
13A4<
1 R75 OUT
13B2> IN 4.99K 1 MOSI IN 13A3<
1%

EMPTY
DEV_OFF PU IS OPTIONAL. 2 PLACE NEAR IC
NOT REQUIRED WHEN CONNECTED TO GPIO NVM_SK=JTAG MODE CAD NOTE: KEEP SPI TRACES SHORT FOR 70MHZ SIGNALING
2
JTAG_MAIN->PU(INT)
JTAG_RSVD->PD (R20)

1
B 1 B
J14 SI-PU_SEC-ENA
SI-PD_SEC-DIS
2

2
1

3.3K
R59
2 INSTALLING J14 DISABLES SECURITY AND THE INVM LOCK
BY PULLING DOWN NVM_SI (PIN 12) DURING POWER_UP.
FOR INFORMATION SEE DATA SHEET: 3.3.1.2
FLASH DETECTION, NVM VALIDITY FIELD, AND NON-SECURE MODE

A A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 5
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

POWER SUPPLY TREE

THESE POWER SUPPLIES ARE EXAMPLES.
D POWER SUPPLIES SHOULD BE OPTIMIZED
BY SYSTEM POWER DESIGNER FOR EACH PLATFORM. D

C PE_V12P0 C
MAIN
V3P3
ENABLE

I210-SVR
3.3V 1.5V
0.9V
LAN SHEET 8

LTC3533
TPD54620 V3P3 BUCK/BOOST
SWITCHING REGULATOR
REGULATOR DIODE OR FOR 3.3V
SHEET 9
FOR 12V TO 4V SHEET 11
SHEET 10
3.3V
PE_V3P3
B MAIN SUPPORT B

NOT USED IN PE_V3P3

THIS DESIGN AUX

A A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 6
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D
POWER SUPPLY & I210 REGULATOR D

THICK TRACES = PLANE

V3P3_LAN
V3P3_LAN
C V1P5_LAN V0P9_LAN C
J15
V0P9_LAN V1P5_LAN 1 C111

1
1 1 1 1 1 1
47UF C101 C75 C79 C104 C113
6.3V
2
EU2
0805LF 10UF 0.1UF 0.1UF 0.1UF 0.1UF EMPTY
*

2
2 2 2 2 2 2
C78 *
1
10UF 1 C88
NC_22 22 RSVD_22_NCI210_AS
10UF
51 VDD1P5_51 2 2
47 VDD1P5_47 V1P5_LAN
42
*
VDD0P9_42
32 VDD0P9_32 VDD1P5_39 39
11 VDD0P9_11 J16

1
59 VDD0P9_59 VDD0P9_38 38 1 1 1 1 1
1C77 1
C97 C95 C110 C82 C89
27 VDD3P3_27 CTOP 40 CTOP 47UF
2
B 10 VDD3P3_10 CBOT 37 0.1UF B
C26 EMPTY 10UF 20.1UF 20.1UF 20.1UF
EMPTY

2
64 VDD3P3_64 2
0.039UF 2 2
41 VDD3P3_41
X7R
NC_56 56 RSVD_56_NC E_PAD_GND 65 CAD NOTE:
1
C90 KEEP CLOSE TO IC
10UF V0P9_LAN
2 *
1
J17

1
1C98 1 1
C115 1
C76 1
C102 C103 1
47UF C105
0.1UF 2
EMPTY 10UF 0.1UF 0.1UF 0.1UF 2 EMPTY

2
2 2 2 2 2

*LOCALIZED AND DISTRIBUTED BULK CAPACITANCE RANGE ~15UF

A A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 7
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D POWER MUX (AUX / MAIN SWITCH) D

INPUTS TO V3P3 DIODE OR

EXTERNAL SATA POWER V3P3_NC
5V_USB TPS54620_OUTPUT V3P3_OR
J10 ~4.3V TYP
CONN15_E33878_001
VCC3_1 1 CR2

1
VCC3_2 2 1
J25 V3P3_OR
VCC3_3 3
GND_4 4 2 MBRS540LT3
5 EMPTY
GND_5
F1

2
GND_6 6 CR4
7 V5P0_CONN_UNFUSED IC
1 2 2 1 J12

1
VCC_7 1
VCC_8 8
VCC_9 9 MBRS540LT3
GND_10 10 V12P0_NC CR3 2
EMPTY

2
GND_11 11 2 1
GND_12 12
C MBRS540LT3 C
12V_13 13
1 C32 C80 C99
14
12V_14
15 1 C3
12V_15 10UF 100UF 180UF 180UF
20% 20%
20% 6.3V 6.3V
2 2 EMPTY EMPTY
1812LF 7343LF 7343LF
V3P3_PE_AUX

1 1 1 1 R25 U4 IDEAL DIODE

C13 R32
1

1
J11 C14 100K
LTC4352

10UF 10UF 100K

2
2 2
EMPTY
2 VCC VIN 1 1 R23
EMPTY 2 2
3
C62
2

UV
0.1UF 8.2K
2 S1
B 4 0V CPO 10 1 2 4
B
12 U3
7 REV
SOURCE
GATE 11 3
NTGS4141N
1 C10 8 G

1 R30 1
OUT G

R28 0.1UF
5
100K 100K 9 GND
STATUS
D1 D2 D3 D4
2
EMPTY
2 2 EPAD FAULT 6 1 2 5 6
13

A A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 8
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D
TPS54620 SWITCHING REGULATOR D

VIN-MIN = 11.0V
VIN-MAX = 13.0V VOUT-MIN = 4.22V
V12P0_PE_MAIN
VOUT-MAX = 4.46V
C PLACEMENT NOTE:: C
PLACE ALL CAPS CLOSE TO ASSOCIATED PINS
PLACE 0.1 UF CAP CLOSE TO VIN PIN EU3
TPS54620
1 C49 1 C47 1 C48 1 C45
22.00UF 22.00UF 22.00UF 0.1UF 4 PVIN_4 BOOT 13 TPS54620_BOOT TPS54620_OUTPUT
5 PVIN_5 1
1206LF 1206LF 1206LF C46
J23
1

1 6 VIN 0.1UF
1 R154 2 2 2 2 PH_11 11
196.00K PH_12 12
2 1% 10 EN 2 L1
2 1 2
2

ENABLES CONVERTER FOR VIN ~8V OR GREATER VSENSE 7

14 PWRGD 10UH
1 R101
37.40K C42
TPS54620_SS 9 SS/TR GND_2 2 1%
TPS54620_EN TPS54620_RT 1 RT/CLK GND_3 3 2 150.0PF
TPS54620_COMP 8 COMP PWRPAD 15 C108 C87 C22 C85
R157 1.0UF 22UF 22UF 22UF
1 30.10K TPS54620_VSENSE
1% ~3.5MS STARTUP-TIME 1
C114 1 R116 1 1 R158 1210LF 1210LF 1210LF
B 2 0.01UF 100K C106 1.15K B
1%
1% 1 R109
2 820.00PF 2 8.45K
2 2 1%
1 2
C35
0.047UF
2

A A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 9
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D
LTC3533 BUCK/BOOST REGULATOR FOR 3.3V D

R98 C41 L3 C39 R91

1 2 1 2 1 2 1 2

2.20 1000PF 6.8UH IND 1000PF 2.20 V3P3_POWER V3P3_LAN

V3P3_OR

3.3V ENABLE V3P3_OR LTC3533

J5
U8

7
EMPTY
1 2

SW1

SW2

1
C C

2
4
R112 R115

2
1
11 PVIN PVOUT 9
7.68K U9
1.0M R155
1% SENSE RANGE: 1.95V-2.12V 10 8 1 2

CONN4
VIN VOUT
2
1 TPS3803-01D 4 1 0 1/2W J7
NC VDD
5 SENSE RESET_N 3 EN_3.3V 12 RUN/SS FB 13 R87 1206LF
2 GND 0

1
3
2
1 RT VC 14
1 1
R150 C31 R93
BURST 2 1
1 1 R113 C51 C50 1 2 1 2
340K
12.1K

PGND_5

PGND_6
C44 0.1UF 0.01UF 8.2K 1%

SGND
1% 1000PF C96

PAD
2 2 2

2
0.1UF 2
C94
J6 V3P3_LAN_SUPPORT
1 C29 470PF 1 EMPTY
2

3
5
6
15
10UF R95
1 2

2
2
33.2K 6.800PF R149
2 1 2

1% 0 1/2W

2
4
1 1
1206LF
B R159 B

CONN4
1
390K
1 R86 1C37 C36 J8
C112 2 200K 10UF
1% 2
0.1UF 2 1206LF
2

1
3
222.00UF

VOLTAGE BOOST REQUIRED TO COMPENSATE FOR

VOLTAGE DROP FROM DIODE OR CIRCUIT.
MANY DESIGNS MAY NOT REQUIRE A BOOST CIRCUIT. VOUT_MIN = 3.18V
VOUT_MAX = 3.41V
A A
I3533-MAX = 1.5A

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 10
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

NC-SI TEST INTERFACE

TEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGN V3P3_LAN_SUPPORT

D CONNECT NS-SI INTERFACE TO A MANAGEMENT CONTROLLER

100MBPS ISO_EN ENABLE FX D
WHEN USING BASE-T OPTION DEPOPULATE NC-SI PHY, PG12-13
V3P3_LAN_SUPPORT R124 R120

2
R123 10.0K 10.0K
10.0K EMPTY EMPTY

1
10MBPS ISO_DIS
DISABLE FX MODE

2
R16 R1 R126

2
10.0K R125 R119
10.0K 10.0K 10.0K
10.0K U2 EMPTY

1
XI
KS8721 V3P3_LAN_SUPPORT
46 XI XO 45 NC
NCSI_MDIO 1 MDIO FXSD_FXEN 34 FIBER_EN
NC2 MDC
RXC 10
C 25 INT_N_PHYAD0 RXDV_CRSDV_PCS_LPBK 9 NCSI_TX_EN OUT 13A2> 3B2< C
3 RXD3_PHYAD RXER_ISO 11 ISOLATE

2
4 RXD2_PHYAD2 R33 R31
3A2< 13A2> OUT NCSI_TXD_1 5 RXD1_PHYAD3 LED0_TEST 26 NCSI_LINK_ACT OUT 12B1< 10.0K
NCSI_TXD_0 6 RXD0_PHYAD4 LED1_SPD100_NFEF 27 NCSI_SPD100 10.0K

1
3A2< 13A2> OUT OUT 12B1<
12B4<> IN NCSI_RX_N 32 RXN LED2 28 DUPLEX FULL DUPLEX
12B4<> IN NCSI_RX_P 33 RXP LED3_NWAYEN 29 AUTONEG_EN
37 REXT ENABLE AUTONEG
TXN 40 NCSI_TX_N OUT 12B4<> BTB
TXER 14 TXER TXP 41 NCSI_TX_P OUT 12B4<>
12A2> IN NCSI_PHY_CLK 15 TXC_REFCLK
13A2< 3B2> IN NCSI_CRS_DV 16 TXEN COL_RMII 21 NCSI_EN NCSI MODE EN BTB EN
NCSI_RXD_0 17 TXD0 CRS_RMII_BTB 22 NCSI_BTB

2
13A2< 3A2>
13A2< 3A2>
IN NCSI_RXD_1 18 TXD1 R45 R48
IN 19 13
TXD2 VDDC 10.0K 10.0K
20 TXD3 VDDIO_1 24

1
VDDIO_0 7
30 47
R118

R130

PD_N VDDPLL
R43

R49

VDDRCV 38
2

48 RST_N VDDRX 31
2

VDDTX 42
1
1

NCSI MODE DIS BTB DIS

1

1
1%

2
6.49K

10.0K

10.0K

10.0K

B R46 R47 B
GND=GND 10.0K 10.0K

1
EMPTY EMPTY
V3P3_LAN_SUPPORT

V2P5_NCSI

R5 V3P3_LAN_SUPPORT
2

22.60K
1%
1

TSR > 50 US FB3 FB1

1 2 V2P5_NCSI_PLL 1 2 V2P5_NCSI_C
1
2

600 600 C12 1 1

1 1 1
R27 C2 1 1
C60 C53 1
C56 C65
10.0K 0.1UF C59 C66 10UF C11 10UF
1

2
10UF 10UF 10UF 0.1UF 0.1UF
EMPTY 2 2 EMPTY 10UF 2 EMPTY 2 2
2 2 2

A A
1

R29
0
EMPTY
2

NC-SI PHY SUPPLIES

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 11
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

NC-SI TEST INTERFACE

ELM BASE-T OPTION DEPOPULATE NC-SI PHY, PG12-13. USE NC-SI HEADER TO PLATFORM.
D TEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGN D
CONNECT NS-SI INTERFACE TO A MANAGEMENT CONTROLLER
NCSI_SPD100 IN 11B1>
V2P5_NCSI V3P3_LAN_SUPPORT
NCSI_LINK_ACT 11B1>
NCSI_TX_P DS9 IN
GREEN
CLOSE TO PHY RJ45

600
R3

FB2
R8 1 2 1 2 JA1
1% 130 CONN12_1840426_3

1
11B1> BI 49.9

2
11B1>
C54 1 TRP1+
BI 11 TRD1+

2
0.1UF
R15 R40 0 TRCT1
1% 1 2 12
CH-A

1
2 49.9
10
NCSI_TX_N TRP1-
TRD1-
C C
4 TRD2+ TRP2+
R36 0 TRCT2
1 2 6 CH-B
NCSI_RX_P 5
TRP2-
TRD2-
DS8
49.9 1
2
3 TRD3+ TRP3+
R21 1 R2 2
LED_DUAL_4P

CLOSE TO PHY 1% C17 130 GREEN 1 TRCT3

1

11B4< BI 0.1UF
2 1 1 3 2
11B4< 1 C1 TRD3-
TRP3-
BI 49.9
2

0.1UF
R24 2 4
C19 1% 2 TRD4+ TRP4+
0.1UF 8
1

NCSI_RX_N 2 YELLOW
7 TRCT4

B 9 B
TRD4- TRP4-

V3P3_LAN_SUPPORT C1 C2

R22

13

14
V3P3_LAN_SUPPORT 50MHZ NC-SI CLOCK
2

Y1 10.0K +-50 PPM

OSC U5 CLOSE TO SOURCE
50MHZ R41
1

ICS553 Q0 2 1 2 NCSI_PHY_CLK OUT 11B4<

1 3 5 ICLK Q1 3
OE OUT
Q2 6 33
8 OE Q3 7 R129
C4 1 1 2 NCSI_CLK_IN OUT 13A2>
0.01UF VDD=V3P3_LAN_SUPPORT; GND=GND; 3B2<
GND=GND 33
VDD=V3P3_LAN_SUPPORT
R128
J9
EMPTY
2 1 1 2 1 2
C5 V3P3_LAN_SUPPORT
33

2
0.01UF
A 2 AS CLOSE TO THE DEVICE A
1
AS POSIBLE
C15
0.01UF
2

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 12
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

TEST CONNECTORS I/O

TEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGN
D LED FUNCTION INTENTIONALLY INVERTED (LED OFF - NORMAL)
D
V3P3_LAN_SUPPORT * SDP PU-OPTIONAL V3P3_PE_AUX
PU EMPTY WHEN NOT USED OR WHEN USED WITH GPIO

R26

R39

R34

R17
1 1 1 1 2 2
* * * * 2
R42
330 S 2
Q1 S Q3 S Q4 Q2

10.0K

10.0K

10.0K

10.0K
2 2 2 2 S S
1

1
D FET_P 1 FET_P 1 Q5
2

G D FET_P 1
DS2

3 G D FET_P S
RED

3 G D D FET_P
LAN_PWR 3 G G
3 Q6
FET_P
1

D
G
J18
CONN8

R6 2
J21

330
R142

R122

R102

R112
C C

330
8 7

R7
SDP0

330

330

330

330
4B4<> IN
13A1> 4B4<> IN SDP1 6 5
CONN8

1
SDP2 4 3

1
4B4<> IN
4B4<> IN SDP3 2 1 PE_WAKE_N 8 7 PE_RESET LED
3A4> IN PE_WAKE LED
2
DS4 2
DS5 2
DS6 2
DS1

2
3A4< OUT PE_RST_N 6 5
SDP1-DEV-OFF OPT RED AMBER YELLOW GREEN 13A1> LAN_PWR_GOOD 4 3

DS3

DS7
OUT

BLUE

BLUE
5B4< OUT DEV_OFF_N 2 1
SDP3-PE-DIS OPT
1 1 1 1
TIME-SYNCH_I/O-J18

1
DEV_OFF_N
PLACE JUMPER
V3P3_LAN_SUPPORT PULL_DOWN_TO
DISABLE
R165
2 NC-SI_I/0
J19 330 PLATFORM MGMT HEADER
V3P3_PE_AUX
1

CONN8 V3P3_LAN_SUPPORT
2

B 4A1> SCL 8 7 1R167 J4 V12P0_PE_MAIN B

DS13

IN
BLUE

4A1> IN SDA 6 5 SIG_DET_LED

3A4> IN SMBALRT_N 4 3 0 SCONN30_E95855001
4A1> IN SIG_DET 2 1 2
V3P3_LAN_SUPPORT
1

2 3B2< 12A2> OUT NCSI_CLK_IN 1 IO1 IO2 2 1R166 R134

3 IO3 IO4 4 0
S Q8 R61 V3P3_LAN_SUPPORT 11B4<
11B4<
3B2>
3A2>
IN
IN
NCSI_CRS_DV
NCSI_RXD_0 5 IO5 IO6 6 0
1 11B4< 3A2> IN NCSI_RXD_1 7 IO7 IO8 8 2
10.0K J20 3A2< 11B4> NCSI_TXD_0 9 IO9 IO10 10 EMPTY
1 OUT 11 12
D FET_P SCONN10_966926_5
3A2< 11B4> OUT NCSI_TXD_1 IO11 IO12
G 2 3B2< 11B1> OUT NCSI_TX_EN 13 IO13 IO14 14
V3P3_LAN_SUPPORT 3 JRST_N 1 2 JTMS 3B2< OUT NCSI_ARB_IN 15 IO15 IO16 16 NCSI_ARB_OUT
IN 3B2>
OUT OUT IN LINK_ACT 17 IO17 IO18 18 SDP1 OUT 4B4<>
IN JTDO 3 4 19 IO19 IO20 20 FM_LAN0_DISABLE_N 13B4<
JTDI 5 6 JTCK 21 IO21 IO22 22
1 PLACE NEAR SPI OUT OUT 23 IO23 IO24 24
R79 7 8 25 IO25 IO26 26 LAN_PWR_GOOD 13B2>
33K
EMPTY J2 9 10 27
29
IO27
IO29
IO28
IO30
28
30
RST_RSMRST_N
OUT
2 CONN10 NC NC
3A4<> IN SMBCLK 1 2
3A4<> IN SMBD 3 4
5B1> IN MISO 5 6
5B1> IN SCLK 7 8 MOSI IN 5B1<
A 5B1> IN SS 9 10 A
JTAG TEST INTERFACE.
ARDVARK
I2C/SPI TEST INTERFACE
1. SCL
2. GND
3. SDA
4. NC/+5V
5. MISO
6. NC/+5V
7. SCLK
8. MOSI
9. SS
10. GND UNKNOWN

LAN ACCESS DIVISION TITLE SIZE CODE DOCUMENT NUMBER REV DATE SHEET
2111 N.E. 25th AVENUE
HILLSBORO, OR 97124 I210-AS/IS REFERENCE SCHEMATIC B 490116 1.90 2012-09-28 13
8 7 6 5 4 3 2 1