AGENDA

• Embedded Systems
• µP vs µC

• Processor Architecture

• Memories

• I/O

• BUSES

• LAB

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 Why Learn ES
– Lot of hype

–Everybody else is doing it

–My friends got a job in ES,hence....

–Desktop would die soon

–My brother in US told me to learn it ....

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 Embedded Systems Defined ?

• No formal definition
• Generally accepted to be a type of computer designed to
solve a specific problem or task
• A combination of hardware and software, and perhaps
additional mechanical or other parts, designed to
perform a dedicated function.
• In some cases, embedded systems are part of a larger
system or product
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App1 App2 APP3

OS App1 App2 APP3

HARDWARE HARDWARE

Typical embedded system

General purpose
computer System
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Embedded Market

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 Design Consideration

S/W
Cost
Reliability

develop
ment
Size
time
Embedded
Systems

Memory
Flexibility Requreme
nt
Performa
Power
nce

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 General Framework
• Embedded systems typically use a processor combined with other hardware and
software to solve a specific computing problem.

• The processors range from simple (by today’s standards) 8-bit microcontrollers to the
worlds fastest and most sophisticated 64-bit microprocessors.

• Embedded system software ranges from a small executive to a large real-time

operating system (RTOS) with a graphical user interface (GUI).

• Embedded systems range from large computers such as an air traffic control system
to small computers.

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Embedded System looks like . .

CPU
Memory chips

Serial Interface
Digital I/O
Analog I/O
LAN Interface
I/O controller
chips

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 CPUs
• CPUs can be
– Microprocessors or Micro controllers

• Any CPU can be studied by knowing following features of CPU

– Clock speed, Address bus size, Data bus size, Register size
– Register set, Instruction set, Address spaces, Endian type
– Interrupt support, DMA support
– Instruction and Data cache
– Memory management
– Protection features (user/supervisor modes)

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 Micro Processors
• Micro Processor is the Integration of a number of useful function in a
single IC Package

• These functions are

– Execute the stored set of instructions to carry out user defined task

– Ability to access external memory chips for both read and write data from
and to the memory

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 Microprocessor Vs Microcontroller
• Contains ALU, GP Registers, SP, In addition in built ROM, RAM, IO
PC, Clock timing circuit and devices, Timers
interrupts

• Requires more H/W, increase in Requires less H/W, reduces PCB size
PCB size & increases reliability

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 Microcontroller Defined

• Very similar to a Microprocessor

• It typically includes a CPU, memory, and other peripherals.

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 Classification of Microcontrollers
• μc are classified into :
– 8 bit μc e.g.: AVR 8515, Intel 8051, Motorola HC05
– 16 bit μc e.g.: Siemens 80167, Intel 80C196
– 32 bit μc e.g.:MCF5272, Power PC 8xxx
– 64 bit μc e.g.: Texas 64xxx series

• The number of bits indicate the internal data bus of a μc. It shows how
many bits of data the μc can process simultaneously.

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 Processor Architecture

Princeton Harvard

Contains 2 separate memory spaces-

• Single Main Memory holding both code & data
program and Data

Complex memory Structure

• Simple memory structure

CPU Code and Data code CPU data

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 RISC vs CISC – Architecture
RISC CISC

Fixed width instructions Variable length instruction

Few formats of instructions Several formats of instructions

Load/Store Architecture Memory values can be used as

operands in instructions

Large Register bank Small Register Bank

Instructions are pipelinable Cannot pipeline instructions

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 RISC vs CISC - Organization

RISC CISC

Hardwired instruction decode Microcode ROMS instruction

decoder

Single cycle execution of instruction Multi cycle execution on instruction

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 RISC vs CISC - Organization

RISC CISC

Hardwired instruction decode Microcode ROMS instruction

decoder

Single cycle execution of instruction Multi cycle execution on instruction

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 RISC CISC
Feature Low Power RISC PC/Desktop CISC

Power A few hundreds of milliwatts Many watts

Compute Speed 200-520 Mega Hz 2-5 Giga Hz

Memory Management

Cost Dollars Tens to hundreds of Dollars

Environmental High Temp, Low EM Needs Fans, FCC/CE

Emissions approval an issue

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 Life cycle of an instruction
• As the instruction moves through the processor it goes through the
following stages.
– Fetch : Instruction fetched from the address stored in the program counter.
– Decode : Instruction decoded and registers read
– Execute : in the ALU
– Write back : Results written back to registers or memory.

• Note : each stage takes one clock cycle

• The Instruction execution requires 4 clock cycles

Fetch Decode Execute Writeback

Cycle 1 Cycle 2 Cycle 3 Cycle 4

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 Non Pipelined Example

1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns

F1 D1 E1 W1

F2 D2 E2 W2

Instruction 1 Instruction 2
• 2 instructions take 4ns each

• A stage is used once every 4ns

• The resultant throughput is 4 cycles per instruction (CPI)

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 Pipeline Example
• Each stage is utilized 1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns
at every clock cycle. F1 D1 E1 W1

F2 D2 E2 W2

F3 D3 E3 W3
• 5 Instructions are F4 D4 E4 W4
executed in 8ns F5 D5 E5 W5

F6 D6 E6

F7 D7
• Resultant throughput F8
is 1 instruction per
cycle Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5

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 Big Endian Little Endian
• Stores the most significant part Stores the least significant part
first
first e.g.: Intel
• e.g.: Motorola
e.g.: consider data 0x4567 at
location 0x5050

45
67
67
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45
 Memory Mapped IO IO Mapped IO
• IO devices are treated as like IO devices are separately
interfaced
memory Separate instruction set
• Memory related instructions available
should be used to access IO

memory memory
Input
Input CPU
CPU memory
output
output
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 Memory

RAM Hybrid ROM

DRAM SRAM NVRAM FLASH EEPROM EPROM PROM Masked

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 Types of RAM
• Static RAM (SRAM) and Dynamic RAM (DRAM)
• SRAM retains its contents as long as electrical power is applied to the chip.
If the power is turned off or lost temporarily, its contents will be lost
forever.
• DRAM has an extremely short data lifetime - typically about four
milliseconds. This is true even when power is applied constantly.
• When deciding which type of RAM to use, a system designer must consider
access time and cost.
• Many embedded systems include both types.

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 Types of ROM
• Masked ROM - hardwired devices that contained a preprogrammed set of
data or instructions. The primary advantage of a masked ROM is its low
production cost.

• PROM (programmable ROM) - Known as one-time programmable (OTP)

devices. The device programmer writes data to the device one word at a
time by applying an electrical charge to the input pins of the chip.

• EPROM (erasable-and-programmable ROM) – Similar to PROM. However,

EPROMs can be erased and reprogrammed. To erase an EPROM, simply
expose the device to a strong source of ultraviolet light. An essential part of
the software development and testing process.

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 Hybrid Memories
• EEPROM(electrically-erasable-and-programmable) - the erase operation is
accomplished electrically. Any byte within an EEPROM may be erased and
rewritten.
• Flash memory devices are
– High density, low cost, nonvolatile, fast (to read, but not to write), and
electrically reprogrammable.
– These advantages are overwhelming and, as a direct result, the use of
flash memory has increased dramatically in embedded systems.
– Flash devices can only be erased one sector at a time, not byte-by-byte.

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 Hybrid Memories
• NVRAM (non-volatile RAM) - An NVRAM is usually just an SRAM with a
battery backup.
– An NVRAM is usually just an SRAM with a battery backup.
– When the power is turned on, the NVRAM operates just like any other
SRAM.
– When the power is turned off, the NVRAM draws just enough power
from the battery to retain its data.
– NVRAM is fairly common in embedded systems, typically limited to the
storage of a few hundred bytes of system-critical information

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 General components of a Microcontroller
• CPU – Heart of the controller. Composed of registers, ALU, instruction decoder and
the control circuitry.
• On Chip Memory – Used to store information

Memory

RAM (Volatile)
ROM(Non Volatile)
1.SRAM
1.PROM
2.DRAM
2.UV-EPROM
3.NV-RAM
3.EEPROM
4.FLASH
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 General components of a Microcontroller
• I/O Ports
– Used to interface with the peripheral devices and the controller.
– Analog I/O and Digital I/O

• Timer/Counter
– For keeping Time and/or calculating the amount of time between
events
– For counting the events
– Baud rate generation

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 FLASH MEMORY
• Flash is believed to be close to perfect memory

• Advantages
– Fast read speeds
– Long-term data retention at much lower cost

• Drawbacks
– Doesn’t allow random bytes to be updated on the fly
– Limitations on number of times it can be re-written

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 Types of Flash Memory
NOR NAND

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 NOR vs NAND
The parallel interconnection of the • The arrangement of these cells is
memory cells helps account for
their fast random read significantly more compact than in
accessibility. NOR.
• The select gates allow higher
programming and erase voltages
to be used without disturbing the
charge stored in unselected cells.
• fast programming and erase times
• Poor random read performance

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 Flash memory read characteristics

• Relatively long initial read delays

• More severe in NAND due to read of redundant region

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 Flash memory write characteristics

• Fast write time for NAND memory

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 The winner is . . .
• NOR provides faster reads and allows random byte access

• NAND writes and erases data faster, costs less per Mb and uses less power
than NOR.

• If the ROM (here flash) is rarely updated, then NOR is obvious choice

• If data is being logged to a flash disk then NAND is the right memory

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vivekn@cdac.in
vivekn@cdac.in
 Bus Mechanisms
• UART/ USART
• SPI – 4 Mbps
• I2C – 1 to 2 Mbps
• CAN – few Mbps
• PCI – 32 / 64 – 133 Mhz
• USB
• Firewire
• Ethernet
• Parallel port (IEEE 1284)

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 How to choose a bus
• Bandwidth

• Presence of I/O controllers

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DEVELOPMENT ENVIRONMENT

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 Host - Target Development Environment
• The distinguishing feature of embedded software development is host-target
development environment

• All the development tools like Editors, compilers and linkers are available on the host
machine

• Typical host machines are Windows 95/98, NT and Unix workstations where the
above development tools are available

• Application programs will be written on the host, get compiled, linked and get the
executable file

• Target systems are the ones where compiled and linked code is executed

• Target systems being a microprocessor based boards does not offer any development
environment themselves, so an host machine is required
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 Cross Compilers
• Another distinguishing feature of embedded software development is cross
compilers

• Cross compilers are the ones, which runs on a machine based on one type of
CPU and produces a machine instructions for a different kind of CPU

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 Downloading
• Downloading is the process of loading the executable image prepared on
the host system on to a target board
• There are various methods to download the code to a target machine. They
are:
– Serial ports
– EPROM/FLASH
– Floppy disks
– Ethernet
– Across a common Bus

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 Debug Monitor
• Debug monitor is a software that resides in a ROM or EPROM of a target
board during the development process
• When a target board is powered on, the debug monitor program runs and
provides facilities for downloading and debugging the application program
• The debug features provided by the debug monitor are very low level ones
• Once application program is debugged and ready, then the debug monitor
could be replaced by the application program, so that whenever system is
powered on, application program runs directly
• In some cases both debug monitor and application program will reside in
the ROM. First control goes to debug monitor which will pass control to the
application program

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 ASSEMBLY
What’s Right With Assembly Language?
• Speed. ALP’s are generally the fastest programs around.
• Space. ALP’s are often the smallest.
• Knowledge. Your knowledge of assembly language will help you write better
programs, even when using HLLs.

What’s Wrong With Assembly Language?

• Assembly is hard to learn & write.
• Assembly language programming is time consuming.
• Improved compiler technology has eliminated the need for assembly language.
• Assembly language is not portable.

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 LAB

• avr-gcc
• avr-as
• avr-ld

• EXPLORE . . .. .

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C-DAC Hyderabad
Brief History

⚫AVR basic architecture was conceived by two students at

the Norwegian Institute of Technology (NTH) Alf-Egil
Bogen and Vegard Wollan.

⚫The acronym AVR has been reported to stand for Advanced

Virtual RISC, but it has also been rumored to stand for the
initials of the chip's designers: Alf and Vegard [RISC].

⚫Atmel says that the name AVR is not an acronym and does
not stand for anything in particular.
TheDevice
AVR is Overview
a Harvard architecture machine with programs and data stored
separately.

Three Basic Families

➢ TinyAvr

✓ 1-8 kB program memory

✓ 8-32-pin package
✓ Limited peripheral set

➢ megaAVRs
✓ 4-256 kB program memory
✓ 28-100-pin package
✓ Extended instruction set
✓ Extensive peripheral set

➢ Application specific AVRs

➢ megaAVRs with special features such as LCD controller, USB controller
 Features in atmega8
Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
– 8K Bytes of In-System Reprogrammable Flash
– Endurance: 10,000 Write/Erase Cycles
– 512K Bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
– 1K Bytes Internal SRAM
⚫ Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare
Modes
– One 16-bit Timer/Counters with Separate Prescaler, Compare
Mode and Capture Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– Output Compare Modulator
– 6-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USARTs
– On-chip Analog Comparator
– Master/Slave SPI Serial Interface
– Programmable Watchdog– On-chip Analog Comparator
 AVR Family Architecture
⚫ RISC Processor Status and Control
Program
⚫ Harvard Program Counter Test Register
Flash Interrupt
Architecture
General Unit
⚫ 32 X 8 general Instruction Purpose
Register SPI
Register
purpose registers Unit
⚫ On-chip UART
Instruction
programmable Decoder ALU
Timer/
timer Counter
⚫ SLEEP and
PWM
POWER DOWN Data
modes SRAM Watchdog
Timer

EEPROM Analog
Comparator

I/O lines
 Flash in Atmega8
• Since all AVR instructions are 16 or 32
bits wide, the Flash is organized as 4K
x 16.

• For software security, the Flash

Program memory space is divided
into two sections, Boot Program
section and Application Program
section.

• Constant tables can be allocated

within the entire program memory
address space (LPM instruction).
SRAM-1K
 Registers

Program Counter (PC) [16 bit ]

Status Register (SREG) [8 bit ]

Sack Pointer (SP) [16 bit ] [SPH, SPL]

General Purpose Register ( R0 – R32) [8 bit]

X , Y , Z Register [16 bit ]

 status register

⚫The micro controller operates based on the Status Register (SREG) and other
internal registers or components. Most important is the Status Register
which holds information on the last instruction and its result and Interrupt
enable status.

⚫ The SREG holds 8 Flags:

 x, y and z registers

•The register r28 -r31 have some additional function to their

general purpose usage.

•These register are 16 bit address pointer for indirect addressing

of the data space .
General purpose register file
 Stack Pointer

The Stack is mainly used for storing temporary data, for storing
local variables and for storing return addresses after interrupts
and subroutine calls.

The Stack Pointer Register always points to the top of the Stack.
Avr instruction set
 Branch instruction…..
• The advantage of rjmp over jmp is that rjmp only needs 1
word of code space, while jmp needs 2 words. Example:rjmp
go_here

• rjmp:
"Relative Jump". This instruction performs a jump within a
range of +/- 2k words. Added together, it can reach 4k words
or 8k bytes of program memory
 Contd…

• ijmp
• "Indirect Jump" to (Z). This instruction performs a jump
to the address pointed to by the Z index register pair. As
Z is 16 bits wide, ijmp allows jumps within the lower
64k words range of code space (big enough for a
mega128)
• Example:
ldi ZL, low(go_there)
ldi ZH, high(go_there)
ijmp
 Contd..
Jmp

"Jump". While rjmp is limited to +/- 2k words, jmp can be used

to jump anywhere within the code space. The address operand
of jmp can be as big as 22 bits, resulting in jumps of up to 4M
words. The disadvantage over rjmp is that jmp needs 2 words
of code space, while rjmp needs just one word.

Example: jmp go_far

 subroutines

⚫ icall :"Indirect Call to (Z)". This instruction works similar

to ijmp, but as a subroutine call.
⚫ rcall :"Relative Call Subroutine". Just as rjmp, rcall can
reach addresses within +/- 2k words. When rcall is
executed, the return address is pushed onto the
stack.
call
 conditional branches

• Conditonal branches are branches based on the micro's

Status Register. If the result of a previous operation left a
status (for example "Zero"), this can be used to jump to
code handling this result. Loops (for, while...) make use
of this.
ldi r16, 5 ;load 5 inreg
loop:dec r16 ;
brne loop ;branch if not equal
 Lab

• avr-as -D –gstabs -ahlms -mmcu=atmega8 -o file.o

file.s
• avr-ld -Aatmega8 -o file
file.o
• simulavr -d atmega8 -g
&
• avr-gdb file
DATA TRANSFER INSTRUCTIONS
Some more instruction
BIT AND BIT-TEST INSTRUCTIONS
 macros
⚫ Macros are a good way to make code more readable, for
example if it contains code that is often reused or if a lot of 16-
bit calculations are done.
⚫ Macros in AVR assembler can be defined everywhere in the
code as long as they're not used at a location before the macro
definition

.macro stack

ldi r16, 0x10 ;

out SPH, r16 ;
ldi r16, 0xff;
out SPL, r1 ;
.endmacro
 for loops?
ldi r16, 0 ;clear the register
loop: out PortB, r16 ;write register to port b
inc r16 ;inc the counter
cpi r16, 10 ;compare with 10
brne loop ;if less than 10 loop

ldi r16, 0
loop1: inc r16 ;this code differs slightly
out PortB, r16 ;find it
cpi r16, 10
brne loop1
 another assignment>>

⚫make code for WHILE (true) { } ;

⚫and DO { }WHILE(true)
 i/o ports
⚫ Atmega8 is having total 3 i/o ports B-D

⚫ All the ports are bi/directional

⚫ Port B ,PortD are 8bit and portC is 7 bit

⚫The AVR I/O Ports are pretty simple to

understand. They have a Port register, a
Data Direction register and a Pin register.
These are part of every I/O port in every
AVR.
I/o REGISTERS

PINB(8bit)

PORTB (8bit)

DDRB(8bit)
 i/o instructions

⚫The simplest I/O instructions are in and out.

⚫ in : reads the value of an I/O Port into a
register.Example: in r16, PinB
⚫ out :writes the value of a register to an I/O Port

⚫but before this something is to be done??

⚫some settings.
 note>>>>

sbi and cbi don't operate on all I/O registers. The same is
true for sbic/sbis. These can only be used for "classic" I/O
Ports and other peripheral registers with addresses from 0 to
31 (0x00 to 0x1F).
 ......

thats all .........

Port diagram
 Interrupts

● An interrupts is an external or internal

event that interrupts the micro-
controller to inform that a device needs
its service.
 interrupt vs polling

● micro controller can serve many devices. there

are two ways to do that interrupt or polling
● In polling the micro controller continuously monitors the
status of a given device ,when the condition is met it
performs specific service.After that it moves to the next
device until every one is serviced.
● in interrupt whenever any device needs its service the
device notifies by sending an interrupt.
 Advantages of interrupt.

● We can assign priority in case of

interrupts.
● In interrupt micro controller can also
ignore (mask ) a device request
● Polling method waste time of micro
controller
Sequence of event when interrupt happens.

● Current instruction execution is completed

● The address of next instruction is stored on stack
● Address of ISR is loaded into PC
● The processor executes the ISR
● The ISR execution is indicated by RETI
instruction.
● The processor loads the PC with the value stored on the
stack
 note>>

● Interrupt can occur at any time so status register (SREG)

needs to be saved.
● One method :use register
● Second :use stack
● Note>>> normally after the interrupt occurs & is being
serviced , global interrupt is disabled
 How the priorities are assigned?

● These are fixed for avr

● The priorities of interrupt is
determined by the way interrupts
vectors are assigned.
● An interrupt vector at lower memory
address is having a higher priority
; PROGRAM FOR 2 FREQUENCY GENERATION BY PRESSING KEYS
;********************************************************************************
.INCLUDE "../8515def.inc" ;
.TEXT
.ORG 0X00
.GLOBAL _START
;*********************************************************************************
_START:
RJMP RESET_HANDLER ;
RJMP EXT_INT0_HANDLER ;
RJMP EXT_INT1_HANDLER ;
RJMP TIM_CAPT_HANDLER ;
RJMP TIM1_COMA_HANDLER ;
RJMP TIM1_COMB_HANDLER ;
RJMP TIM1_OVF_HANDLER ;
RJMP TIM0_OVF_HANDLER ;
RJMP SPI_STC_HANDLER ;
RJMP UART_RXCINT0_HANDLER ;
RJMP UART_DRE_HANDLER ;
RJMP UART_TXC_HANDLER ;
RJMP ANA_COMP_HANDLER ;
;************************************************************************************
RESET_HANDLER : rjmp main
EXT_INT0_HANDLER : reti
EXT_INT1_HANDLER : reti
TIM_CAPT_HANDLER : reti
TIM1_COMA_HANDLER : reti
TIM1_COMB_HANDLER : reti
TIM1_OVF_HANDLER : reti
Various interrupt registers
Registers
 Timers

● Two 8-bit Timer/Counters with Separate Prescalers and

Compare Modes
● One 16 bit timers with seperate prescaler ,compare mode
and capture mode
 Purpose

● To calculate time delays

● To be use as the counters
● Its advantage is that the input clock
and operationof the timer is
independent of the program execution.
 Why different timers?

● The answer is simple to have right timer for the right

application
● A timer with 16-bit resolution is certainly more flexible to
use than one with 8-bit resolution.
● for many application it is sufficient to have 8 bit resolution
using higher resolution means higher program load &
higher cost.
 Different modes of operation

● Normal mode
● Capture mode
● Pwm mode
Registers
 Modes of operation of timers

●Normal mode : start the timer , as the timer

reaches the maximum value it overflows ,generate
the interrupt if enabled ,set the
corresponding timer overflow flag .
●The timer will continue to run unless u stop it
or u reach the end of the program
 compare mode & waveform generation

● There is a 8 bit comparator that continuously compares the

value in the TCNT2 and OCR2 when ever TCNT2
equals OCR2 the comparator signals a match .
● it will set the corresponding flag
● will generate the interrupt if enabled
Register
Registers
what are the two possibility that can happen
?

● When there is a match we can clear the contents of the

TCNT2 . this is nothing but clear the timer on compare
match mode .
● Let the timer run and overflow.
Com bits
 Timers can also be used for PWM
generation

● Fast PWM mode

● Phase correct PWM mode
 Phase correct PWM mode

● It is based on the dual slope operation

● The timer in this case act as count up & count down timer .
● The resolution is fixed to the 8 bits
● the timer overflow flag will be set when the timer reaches
the bottom value .
● The pwm is generated on OC2pin.
 Fast PWM

● It provides a high frequency PWM wave

form generation .
● It has a single slope operation .
● The counter counts from bottom to max
then then restart from bottom.
 Refer datasheet .>>>

Page no. 104 – 120 for timer2(8 bit timer)

 Data communication

Some Embedded systems cannot work in isolation.

They may need to communicate with the other systems.
Two approaches of the communication is possible.
Serial communication & parallel communication.

vivekn@cdac.in 6/03/2010
 Continued...

A bit is transmitted at a
single time
Slower [ ↓]
Sender Reciever Few wires [ ↑ ]

Byte or more at a time.

[↑]
Faster [↑]
Large wire [↓]
Sender Receiver

vivekn@cdac.in 6/03/2010
 Serial data transmission type
Transmission only in one
direction
Simplex
Data transmitted in one
direction
Direction of data can be
changed
DUPLEX Both direction &
simultaneously

FULL DUPLEX

vivekn@cdac.in 6/03/2010
 Serial com transmission mode

Synchronous mode

Asynchronous mode

vivekn@cdac.in 6/03/2010
 Asynchronous mode

Transmit one character at a time

Data bits in a character ?
Order of transmission LSB to MSB
Start and stop bits tells receiver where one
character stops and other starts
Stop bits can be either one or two
Parity bit for error detection
Sending parity bit is optional

vivekn@cdac.in 6/03/2010
 frame format

vivekn@cdac.in 6/03/2010
 Async.. serial transfer

NO data- signal is kept high

Start bit – signal low for 1 bit time
The data transmission rates are specified in terms of
Baud rate
Common values
2400,9600,19200,57600,115200
Baud rate

vivekn@cdac.in 6/03/2010
 Atmega8 USART facts

Full duplex operation

(independent receive and transmit register)
High resolution baud rate register (UBRR)
Serial frames with 5 -9 data bits
( 1-2 stop bits ,odd even parity generator,checking by
H/W)
Errors
data overrun :data loss due to receive buff
full frame error : error in the stops bits received
Parity error:

vivekn@cdac.in 6/03/2010
 Parity Bit

A parity bit is a bit

that is added to
ensure that the
number of bits with
value of one in a given
set of bits is always
even or odd.
Parity bits are used as
the simplest error
detecting code.

vivekn@cdac.in 6/03/2010
 Registers

vivekn@cdac.in 6/03/2010
 Registers

vivekn@cdac.in 6/03/2010
vivekn@cdac.in 6/03/2010
 Baud Rate register

vivekn@cdac.in 6/03/2010
 Equations

vivekn@cdac.in 6/03/2010
 Uart Init

vivekn@cdac.in 6/03/2010
 Transmit function

vivekn@cdac.in 6/03/2010
 Refer>>>

page no (for usart registers) 153 – 159

page no 133 -159

vivekn@cdac.in 6/03/2010
 EEPROM

● EEPROM (Electrically Erasable Programmable

Read Only Memory) is one of the three memory
types of AVRs .
● EEPROM is able to retain its contents when there
is no supply voltage.
● You can also change the EEPROM contents on
runtime, so, EEPROM is useful to store
information like calibration values, ID numbers,
etc.
● To write in the EEPROM, you need to specify the data you
want to write and the address at which you want to write
this data.

● In order to prevent unintentional EEPROM writes (for

instance, during power supply power up/down), a specific
write procedure must be followed

● The write process is not instantaneous, it takes between 2.5

to 4 ms. For this reason, your software must check if the
EEPROM is ready to write a new byte (maybe a previous
write operation is not finished yet).
Registers
● The EEPROM Control Register (EECR) is used to control the
operation of the EEPROM
● The EERE (EEPROM Read Enable) bit is used to read the
EEPROM.
● In order to issue an EEPROM write, you must first set the
EEMWE (EEPROM Master Write Enable) bit, and then set the
EEWE (EEPROM write enable) bit. If you don't set EEMWE
first, setting EEWE will have no effect.
● The EEWE bit is also used to know if the EEPROM is ready to
write a new byte. While the EEPROM is busy, EEWE is set to
one, and is cleared by hardware when the EEPROM is ready.
So, your program can poll this bit and wait until is cleared
before writing the next byte.
 The following is a code snippet for writing the data 0xAA in
address 0x10 :

cli ; disable interrupts

EEPROM_write: ;if write enable bit is cleared, EEPROM is
sbic EECR, EEWE ;ready to be written to else loop until EEWE
rjmp EEPROM_write ;cleared

ldi r16, 0x10 ;load r16 with address (0x10)

out EEAR, r16 ;and write it to the address register

ldi r16, 0xAA ;load with the data we want to write (0xAA)
out EEDR, r16 ;and write it to the data register

sbi EECR; EEMWE ;set master write enable bit

sbi EECR, EEWE ; set write enable bit

sei ; and allow interrupts again

 Eeeprom read

● To read a data from the EEPROM, you must first

check that the EEPROM is not busy by polling the
EEWE bit
● Then you set the EEAR register with the address
you want to read, and then set the EERE bit in the
EECR register.
● After that, the requested data is found in the EEDR
register.
The following is a code snippet for reading the data stored in
address 0x10. The read data is stored in r16.

EEPROM_read:

sbic EECR, EEWE ;check if the EEPROM is busy writing a `

;byte
rjmp EEPROM_read

ldi r16, 0x10 ;load address register with 0x10

out EEAR, r16

sbi EECR, EERE ;set read enable bit

in r16, EEDR ; and get the data from address 0x10
 The Serial Peripheral Interface (SPI)

● The SPI (Serial Peripheral Interface) is a

peripheral used to communicate between the
AVR and other devices, like others AVRs,
external EEPROMs, DACs, ADCs, etc.
● With this interface, you have one Master device
which initiates and controls the communication,
and one or more slaves who receive and transmit
to the Master.
● The core of the SPI is an 8-bit shift register in both the Master
and the Slave, and a clock signal generated by the Master.

● Let's say the Master wants to send a byte of data (call it A) to

the Slave and at the same time receive another byte of data
from the Slave (call it B).

● Before starting the communication, the Master places A in its

shift register, and the Slave places B in its shift register.
Then the Master generates 8 clock pulses, and the contents of the
Master's shift register are transferred to the Slave's shift register
and vice versa
So, at the end of the clock pulses, the Master has completely received B,
and the Slave has received A. As you can see, the transmission and
reception occurs at the same time, so it is a full duplex data transfer
● In an AVR, four signals (pins) are used for the SPI:
MISO, MOSI, SCK and SS' (SS' means SS
complemented).
● MISO (Master In Slave Out): the input of the
Master's shift register, and the output of the Slave's
shift register.
● MOSI (Master Out Slave In): the output of the
Master's shift register, and the input of the Slave's
shift register.
● SCK (Serial Clock): In the Master, this is the
output of the clock generator. In the Slave, it is the
input clock signal.
● SS' (Slave Select): Since in an SPI setup you can have
several slaves at the same time, you need a way to select
which Slave you want to communicate to.

● If SS' is held in a high state, all Slave SPI pins are normal
inputs, and will not receive incoming SPI data.

● On the other hand, if SS' is held in a low state, the SPI is

activated. The software of the Master must control the SS'-
line of each Slave.
● If the SPI-device is configured as a Master, the
behavior of the SS' pin depends on the configured
data direction of the pin.
● If SS' is configured as an output, the pin does not
affect the SPI.
● f SS' is configured as an input, it must be held high
to ensure Master SPI operation.
● If the SS' pin is driven low, the SPI system
interprets this as another Master selecting the SPI
as a Slave and starting to send data to it.
● Having two SPI Masters is quite unusual
A word of caution about the SPI pin names. MISO, MOSI, SCK
and SS' are the names used by AVRs. Other devices may use a
different set of names. You must check the data sheet of the
particular device you are using to get them right.

What are the data directions of the SPI pins?

It depends on the particular pin and on whether the
SPI is set as a Master or Slave
 Registers
[SPCR] [SPSR] [SPDR]
These two bits control the SCK rate of the device
configured as a master. SPR1 and
SPR0 have no effect on the slave.
 -

● CPOL: Clock Polarity-> When this bit is written to

one, SCK is high when idle. When CPOL is written
to zero,SCK is low when idle.
● CPHA: Clock Phase-> The settings of the clock
phase bit (CPHA) determine if data is sampled on
the leading (first) or trailing (last) edge of SCK.
 SPI is used to talk to a variety of peripherals

● Sensors: temperature, pressure, ADC, touchscreens

● Control devices: audio codecs, digital potentiometers, DAC
● Communications: Ethernet, USB, USART, CAN, IEEE
802.15.4
● Memory: flash and EEPROM
● Real-time clocks
● LCD displays, sometimes even for managing image data
● Any MMC or SD card
 For example program of SPI
reffer to page number 124-132
of Data Sheet
 master side algo

● ->>Set MOSI as output.

● ->> Set SCK as output.

● ->> Set SS' as output.

● ->>Set SPI as a Master, with interrupt

disabled,MSB first, SPI mode 3 and clock
frequency .
● ->> Initiate data transfer.

● ->> Wait for transmission to complete.

● ->>The received data is placed in register.

 Slave side algo

● Set MISO as an output.

● Set SPI as a Slave, with interrupt disabled,

● MSB first and SPI mode 3.

● Send data on Master request.

● Wait for reception to complete.

● The received data is placed in register.

 watchdog timer

A watchdog timer is a piece of hardware, often

built into a microcontroller that can cause a
processor reset when it judges that the system
has hung, or is no longer executing the correct
sequence of code
 Kicking the dog

● The process of restarting the watchdog timer's

counter is sometimes called "kicking the dog."
Disabling Watchdog
Default Values