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9 FET Amplifier PDF

FET amplifiers provide excellent voltage gain, high input impedance, low power consumption, and a good frequency range. The transconductance (gm) of a FET relates a change in drain current (ID) to the corresponding change in gate-source voltage (VGS). FET amplifiers can be configured in common-source, common-gate, or common-drain circuits. Common-source circuits provide voltage gain but introduce a phase shift, while common-gate and common-drain circuits do not introduce phase shifts.

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242 views21 pages

9 FET Amplifier PDF

FET amplifiers provide excellent voltage gain, high input impedance, low power consumption, and a good frequency range. The transconductance (gm) of a FET relates a change in drain current (ID) to the corresponding change in gate-source voltage (VGS). FET amplifiers can be configured in common-source, common-gate, or common-drain circuits. Common-source circuits provide voltage gain but introduce a phase shift, while common-gate and common-drain circuits do not introduce phase shifts.

Uploaded by

abdullah mohammed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 8:

FET Amplifiers
Introduction

FETs provide:

• Excellent voltage gain


• High input impedance
• Low-power consumption
• Good frequency range

First Year 2014 ٢


FET Small-Signal Model

Transconductance

The relationship of a change in ID to the corresponding change in VGS is


called transconductance or mutual conductance

Transconductance is denoted gm and given by:

ΔI D
gm 
ΔV GS

First Year 2014 ٣


Graphical Determination of gm

First Year 2014 ٤


Mathematical Definitions of gm
I D
For JFET and D-MOS gm 
 VGS
2
 V  2I DSS  VGS 
I D  I DSS 1  GS  gm   1  
 VP  VP  V P 

2I DSS
Where VGS =0V g m0 
VP
 V 
g m  g m0 1  GS 
 VP 

VGS ID
Where 1 
VP I DSS

 V  ID
g m  g m0  1  GS   g m0
 VP  I DSS

First Year 2014 ٥


Mathematical Definitions of gm
I D
For E-MOS gm 
 VGS

I D  K VGS  VT 
2

g m  2 K VGS  VT 

ID
Where ( VGS  VT ) 
K

ID
g m  2K  2 KI D
K

First Year 2014 ٦


FET AC Equivalent Circuit

Input impedance: Zi   
1
Output Impedance: Z o  rd 
y os
VDS
where: rd  VGS  constant
I D
yos= admittance parameter listed on FET specification sheets.

First Year 2014 ٧


Common-Source (CS) Fixed-Bias Circuit

Input impedance:

Zi  RG

Output impedance:

Z o  R D || rd

Zo  R D
rd  10R D

Voltage gain:

Vo
Av    g m (rd || R D )
Vi
Vo
Av   g m R D
Vi rd  10R D

First Year 2014 ٨


Common-Source (CS) Self-Bias Circuit

Voltage gain: Input impedance: Zi  RG

Vo g m v gs R D g R Output impedance: Zo  R D
Av    m D
Vi v gs  g m v gs R S 1 gmRS

First Year 2014 ٩


Common-Source (CS) Voltage-Divider Bias

Input impedance:

Z i  R 1 || R 2

Output impedance:

Z o  rd || R D

Zo  R D
rd  10R D

Voltage gain:
A v   g m (rd || R D )

A v  g m R D
rd 10R D

First Year 2014 ١٠


Source Follower (Common-Drain) Circuit

Input impedance: Zi  R G
v
Output impedance: Z0  o when v i  0
Io
v0
Io   g m v gs
R s || rd
v gs   v o
vo 1
Zo   rd || R S ||
Io gm
1
Zo  R S || r 10R
gm d S
Voltage gain:
V g (r || R S )
Av  o  m d
Vi 1  g m (rd || R S )
Vo g R
Av   m S rd 10
Vi 1  g m R S

First Year 2014 ١١


Common-Gate (CG) Circuit

The input is on the source


and the output is on the
drain.

There is no phase shift


between input and output.

First Year 2014 ١٢


Calculations
Input impedance:
v
Zi  i
ii
v
i i  i  g m v gs
Rs
v gs   v i
 1 
Zi  R S ||  
gm  rd  10R D
Output impedance: Voltage gain:
Zo  R D Vo  g m v gs R D  g m v gs R D
Av     g m R D
Vi vi  v gs

First Year 2014 ١٣


D-Type MOSFET AC Equivalent

First Year 2014 ١٤


E-Type MOSFET AC Equivalent

gm and rd can be found in


the specification sheet for
the FET.

First Year 2014 ١٥


Common-Source Drain-Feedback

There is a 180 phase shift


between input and output.

First Year 2014 ١٦


Calculations
vi
Input impedance: Zi 
Ii
v i  I i R F  I R rd || R D
I R  I i  g m v gs
v i  I i R F  ( I i  g m v gs )rd || R D
v i (1  g m rd || R D )  I i ( R F  rd || R D )
R F  rd || R D
Zi 
1  g m (rd || R D )
Output impedance:
Z o  R F || rd ||R D

Z o  R D R F  rd || R D , rd  10R D
Voltage gain:

A v  g m (R F || rd || R D )

A v  g m R D R F  rd ||R D ,rd 10R D

First Year 2014 ١٧


Common-Source Voltage-Divider Bias

First Year 2014 ١٨


Calculations
Input impedance:
Z i  R 1 || R 2

Output impedance:
Z o  rd || R D
Z o  R D rd  10

Voltage gain:
A v   g m (rd || R D )
A v   g m R D rd  10R D

First Year 2014 ١٩


Summary Table

First Year 2014 ٢٠


Summary Table

First Year 2014 ٢١

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