0% found this document useful (0 votes)
19 views20 pages

MOSFET CS Amplifier

Uploaded by

Renel Anto
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
19 views20 pages

MOSFET CS Amplifier

Uploaded by

Renel Anto
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 20

Module 3 – Field Effect Transistor

Topic: AC Circuit Analysis:


Small signal model of MOSFET CS amplifier

Reference books –
Robert Boylestad and Louis Nashelsky, Electronic Devices and Circuits,
Neamen D.A., Electronic Circuit Analysis and Design, McGraw Hill International
Syllabus of Module 3 : Field Effect Transistor

• Types of FETs, basics of construction and working principle; MOSFET structure


and I-V characteristics. MOSFET as a switch. MOSFET as an amplifier
• DC Circuit Analysis: Types of biasing circuits of MOSFET (Numerical), dc load
line and region of operation.
• AC Circuit Analysis: Small signal model of MOSFET CS amplifier, derivation of
expressions for voltage gain and output impedance of MOSFET CS amplifier
• (Numerical).

FCRIT, VASHI 2
Three basic MOSFET transistor amplifier configurations.

• common source,
• common drain (source follower), and
• common gate.

FCRIT, VASHI 3
NMOS common source circuit with time varying signal source in
series with gate dc source

• NMOS common-source circuit


with a time-varying sinusoidal
voltage source in series with the
dc source VGG

Source : Neamen D.A., Electronic Circuit Analysis and Design,


McGraw Hill International 4
Common-source transistor characteristics with dc load line

• As vi increases, the instantaneous


value of v GS increases, and the bias
point moves up the load line. A larger
value of v G S means a larger drain
current and a smaller value of vDS .
• VDS = VDD - ID RD
• For a negative vi (the negative portion
of the sine wave), the instantaneous
value of v G S decreases below the
quiescent value, and the bias point
moves down the load line. A smaller
v G S value means a smaller drain
current and increased value of vDS

Source : Neamen D.A., Electronic Circuit Analysis and Design,


5
McGraw Hill International
• The time-varying signal source v i generates a
time-varying component of the gate-to-source
voltage. vgs is the time varying component of the
gate-to-source voltage.
• For the FET to operate as a linear amplifier, the
transistor must be biased in the saturation
region
• When symmetrical sinusoidal signals are applied
to the input of an amplifier, symmetrical
sinusoidal signals are generated at the output, as
long as the amplifier operation remains linear.
• The load line can be used to determine the
maximum output symmetrical swing. If the
output exceeds this limit, a portion of the output
signal will be clipped and signal distortion will
occur.
• In the case of FET amplifiers, the output signal
must avoid cutoff (i D = 0) and must stay in the
saturation region (vDS > vDS (sat)).

Source : Neamen D.A., Electronic Circuit Analysis and Design,


6
McGraw Hill International
Transfer char. for n-channel enhancement MOSFET
• The transconductance g m is a transfer
coefficient relating output current to input
voltage and can be thought of as
representing the gain of the transistor.
• The transconductance g m is the slope of
the curve.
• If the time-varying signal vgs is sufficiently
small, the transconductance gm is a
constant.
• With the Q-point in the saturation region,
the transistor operates as a current source
that is linearly controlled by vgs
• gm = ΔiD/ΔvGS

Source : Neamen D.A., Electronic Circuit Analysis and Design,


7
McGraw Hill International
Depletion type MOSFETs

FCRIT, VASHI 8
transfer char. (ID v/s VGS) for Depletion MOSFET

FCRIT, VASHI 9
dI D
gm  |Q - po int
dVGS
VGS 2
I D  I DSS (1  )
VP
dI D d VGS 2
 [ I DSS (1  ) ]
dVGS dVGS VP
VGS d VGS
 2 I DSS (1  ){ (1  )}
VP dVGS VP
VGS d d VGS
 2 I DSS (1  ){ (1)  ( )}
VP dVGS dVGS VP
I DSS VGS
gm  2 (1  )
| VP | VP

FCRIT, VASHI 10
relationship between Id and gm
VGS 2
I D  I DSS (1  )
VP
VGS ID
1 
VP I DSS
ID
g m  g mo
I DSS

FCRIT, VASHI 11
AC equivalent model

FCRIT, VASHI 12
FCRIT, VASHI 13
• Input Impedance (Zi)
The input impedance is sufficiently
l a rge to a s s u m e t h at t h e i n p u t
terminals approximate an open circuit.
Its practical value is of the order of
1012 to 1015 Ω for MOSFETs
• The input impedance is
represented by the open circuit at
the input terminals and the output
impedance by the resistor rd from
drain to source.
• The control of Id by Vgs is included
a s a c u r r e n t s o u rc e g m Vg s
connected from drain to source.
• 180° phase shift between output
and input voltages
FCRIT, VASHI 14
• The output impedance of MOSFET
is similar in magnitude to that of
conventional BJTs.
• In specification sheets, the output
impedance will typically appear as
gos or yos with the units of mS.
• Zo = rd = 1/ gos = 1/yos
• The output impedance is defined
on the characteristics as the slope
of the horizontal characteristic
curve at the point of operation.
• The more horizontal the curve, the
greater is the output impedance.
• rd = ΔVDS/ ΔID ` VGS=constant

FCRIT, VASHI 15
voltage-divider configuration

FCRIT, VASHI 16
ac equivalent circuit

FCRIT, VASHI 17
ac equivalent circuit for voltage divider bias of Depletion
MOSFET

FCRIT, VASHI 18
Input impedance (Zi)
• R1 and R2 are in parallel with the open-
circuit equivalence of the MOSFET
• Zi= R1 || R2

Output impedance (Zo)


• Setting Vi = 0 V sets Vgs=0 and current
source gmVgs to zero, hence it will be
open circuit.
• Zo = rd || RD
• For rd ≥ 10RD,
• Zo = RD

FCRIT, VASHI 19
Voltage gain (Av)
• Vgs = Vi
• Vo = -gmVgs(rd || RD)
• Now Av = Vo/Vi
= -gmVgs(rd || RD)/ Vgs

Vo
Av =
Vi
- gmVgs (rd || RD)
=
Vgs

If rd  10R D ,
Vo
Av =  - gmR D
Vi
FCRIT, VASHI 20

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy