LABORATORY MANUAL

LINEAR INTEGRATED CIRCUITS AND

APPLICATIONS LABORATORY

Regulations : GR14
Programme/ : B.Tech. V Semester
Semester
Branch : ELECTRONICS AND
COMMUNICATION
ENGINEERING

Department of Electronics and Communication

Engineering

GODAVARI INSTITUTE OF ENGINEERING &

TECHNOLOGY
(Autonomous)

NH-16, CHAITANYA KNOWLEDGE CITY, RAJAHMUNDRY – 533 296

 Description Subject Teaching Methodology L T P C
Name of the Linear Integrated Circuits and Application 0 0 3 2
Course LAB
Course Code
Knowledge of theoretical and experimental properties of
Prerequisite (s) linear integrated circuits.

List of experiments as in the syllabus

1. Study of IC’s – IC 741,IC 555,IC 565, IC 566, IC 1496 Functioning, parameters and specifications
2. OP-AMP application-Adder,subtractor, Comparator Circuits.

3. Integrator and Differentiator Circuits using IC 741

4 Active Filters Applications-LPF, HPF(first order)
5 Active Filters Applications-BPF, Band Reject(wideband) And Notch Filter
6 IC 741 Oscillator Circuits-Phase shifting and Wien Bridge Oscillator
7 Function Generator using OP AMP’s
8 IC 555 Timers- Monostable And Astable Opertation Circuit
9 Schmitt Trigger Circuit-using IC 741
10 IC 565- PLL Application
11 IC 566 – VCO Application
12 Voltage Regulator using IC 723
13 Three Terminal Voltage Regulator- 7805
14 4 bit DAC using OP AMP AND 4 Bit ADC

Course Outcomes

After completion of the course, a successful student is able to

1. Design and analyze various circuits like adder, subtractor, integrator and differentiator etc .
2. Design active filters for the given specifications and obtain their frequency response
characteristics.
3. Design and analyze multivibrator circuits using op-amp and 555Timer
4. .Design the circuits using op-amps for various applications like Schmitt Trigger, Precision
Rectifier, Comparators and three terminal IC 78XX regulator.

.Text Books:

1. ‘Linear integrated circuits by D.Roy choudhury and Shail.B.Jain,fourth edition, New

Age International Publications, New Delhi.
Web-Resources: www.nptel.com

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 TOTAL EXPERIMENTS

S.NO EXPT NAME OF THE EXPERIMENT PAGE

NO NUMBER
1 1 Study of IC’s – IC 741,IC 555,IC 565, IC 566, 9
IC 1496 Functioning, parameters and
specifications
2 2 OP-AMP application-Adder,subtractor, 14
Comparator Circuits
3 3 Integrator and Differentiator Circuits using IC 19
741
4 4 Active Filters Applications-LPF, HPF(first 22
order)
5 5 Active Filters Applications-BPF, Band 29
Reject(wideband) And Notch Filter
6 6 IC 741 Oscillator Circuits-Phase shifting and 35
Wien Bridge Oscillator
7 7 Function Generator using OP AMP’s 39

8 8 IC 555 Timers- Monostable And Astable 43

Opertation Circuit
9 9 Schmitt Trigger Circuit-using IC 741 51

10 10 IC 565- PLL Application 55

11 11 IC 566 – VCO Application 58

12 12 Voltage Regulator using IC 723 61

13 13 Three Terminal Voltage Regulator- 7805 65

14 14 4 bit DAC using OP AMP AND 4 Bit ADC 68

15 15 ZERO CROSSING DETECTOR 73

16 16 INVERTING AMPLIFIER 75

17 17 NON-INVERTING AMPLIFIER 77

18 18 VOLTAGE FOLLOWER 79

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19 19 PRECISION RECTIFIER 81

20 20 LOGARITHMIC AMPLIFIER 83

EXPERIMENTS AS PER SYLLABUS

S.NO EXPT NAME OF THE EXPERIMENT PAGE

NO NUMBER
1 1 Study of IC’s – IC 741,IC 555,IC 565, IC 9
566, IC 1496 Functioning, parameters and
specifications
2 2 OP-AMP application-Adder,subtractor, 14
Comparator Circuits
3 3 Integrator and Differentiator Circuits using IC 19
741
4 4 Active Filters Applications-LPF, HPF(first 22
order)
5 5 Active Filters Applications-BPF, Band 29
Reject(wideband) And Notch Filter
6 6 IC 741 Oscillator Circuits-Phase shifting and 35
Wien Bridge Oscillator
7 7 Function Generator using OP AMP’s 39

8 8 IC 555 Timers- Monostable And Astable 43

Operation Circuit.
9 9 Schmitt Trigger Circuit-using IC 741 51

10 10 IC 565- PLL Application 55

11 11 IC 566 – VCO Application 58

12 12 Voltage Regulator using IC 723 61

13 13 Three Terminal Voltage Regulator- 7805 65

14 14 4 bit DAC using OP AMP AND 4 Bit ADC 68

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 LIST OF ADDITIONAL EXPERIMENTS

S.NO EXPT NAME OF THE EXPERIMENT PAGE

NO NUMBER
15 15 ZERO CROSSING DETECTOR 73

16 16 INVERTING AMPLIFIER 75

17 17 NON-INVERTING AMPLIFIER 77
18 18 VOLTAGE FOLLOWER 79

19 19 PRECISION RECTIFIER 81

20 20 LOGARITHMIC AMPLIFIER 83

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Evaluation of Laboratory Marks for III Year (Internal Exams)
1. The internal lab examination schedules will be given by the Examination
Branch.
2. During a semester there will be two lab exams and each
exam will be evaluated for 50 marks.
3. Average of two lab exams will be the final internal lab exam marks.

4. First laboratory exam will be conducted on First

half of the total number of experiments, Second
Laboratory Exam will be conducted on the Second half
of experiments.
The evaluation is as follows
I. Continuous evaluation - 20 marks

II. Internal Laboratory Exam - 30 marks

I. Continuous Evaluation 20 marks

a) Day to day evaluation: 15 marks
i. Attendance 2 out of 15
ii. Experiments and 5 out of 15
observation 3 out of 15
iii. Result 5 out of 15
iv. Record
b) Viva voice 5 marks
II. Internal Laboratory Exam 30 marks
a) Exam 15 marks
i. Experiments write up 10 out of 15
ii. Result and Graphs 5 out of 15
b) Viva voice 5 marks
c) Lab knowledge Test (Quiz) 10 marks

I. Continuous evaluation - 20 marks

a) Day to day evaluation - 15 marks

Each experiment / program will be evaluated for 15 marks.

The splitting of marks is as follows
i) Attendance - 2 marks

The student should attend the lab regularly; if he/she

is absent he/she will be losing 2 marks.
ii) Experiments and observation
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The student should complete the
program within the assigned time
otherwise he / she will be losing 5
marks.
iii) Experiment result will carry 3 marks.

iv) Record 5 marks

Student must submit the record in the next lab session.

v) Average marks of the Half of the experiments will
be considered for day to day evaluation for 15 marks
separately for lab examination one and two.
b) Viva Voce – 5 marks

II. Internal laboratory examination - 30 marks

a) Exam - 15 marks
The Splitting of marks as follows
i) Experiments write up - 10 marks

ii) Result and Graphs - 5 marks

b) Viva Voce - 5 marks

c) Lab knowledge Test (Quiz) 10 marks

A quiz will be conducted along with the internal lab
exam and schedule will be given separately.
The quiz will be conducted for 20 minutes. The quiz
contains 20 questions of type multiple choice. Each
question carrying 0.5 marks
The internal lab examination duration - 2 hours
Every student will be given experiments in the internal lab exam. In
case the student wishes to change the experiments 5 marks will be
deducted. A time slot of 45 minutes is given for write up of
programs / experiments.
The student is expected to complete the assigned
program / experiment within 1 hour and the
remaining 15 minutes will be utilized for viva
voce examination.
There shall be no supplementary exams in case the student fails to attend internal
lab and quiz exam as per schedule

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Evaluation of Laboratory Marks (End exams)

1. The external lab examination schedules will be given by the Examination

Branch.
2. Duration of External lab examinations - 3 Hours

3. Exam will be evaluated for 50 Marks

I. Experiment write-up 15marks

II. Experiment Setup execution 15 marks
III. Result 10 marks
IV. Viva –Voce 10 marks

The Splitting of marks is as follows

I. Experiment write-up - 15 marks

II. Experiment Setup execution - 15 marks

III. Result - 10 marks

IV. Viva –Voce - 10 marks

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 1. STUDY OF ICs-IC 741, IC 555, IC 565, IC 566,IC 1496 - FUNCTIONING ,
PARAMETERS AND SPECIFICATIONS

AIM: To study the functioning, parameters and specifications of IC 741,IC555,IC565,IC

566,IC 1496.
An operational amplifier IC is a solid-state integrated circuit that uses external feedback to control its
functions. It is one of the most versatile devices in all of electronics. The term 'op-amp' was originally used
to describe a chain of high performance dc amplifiers that was used as a basis for the analog type computers
of long ago. The very high gain op-amp IC's our days uses external feedback networks to control responses.
The op-amp without any external devices is called 'open-loop' mode, referring actually to the so-called 'ideal'
operational amplifier with infinite open-loop gain, input resistance, bandwidth and a zero output resistance.
However, in practice no op-amp can meet these ideal characteristics. Since the LM741/NE741/µA741 Op-
Amps are the most popular one, this tutorial is direct associated with this particular type. Nowadays the 741
is a frequency compensated device and although still widely used, the Bi-polar types are low-noise and
replacing the old-style op-amps.

The µA741 is Manufactured by Fairchild Semiconductor.

Supply Voltage (+/-Vs): The maximum voltage (positive and negative) that can be safely used to feed the op-
amp.

Dissipation (Pd): The maximum power the op-amp is able to dissipate, by specified ambient temperature (500mW @
80° C).

Differential Input Voltage (Vid): This is the maximum voltage that can be applied across the + and - inputs.

Input Voltage (Vicm): The maximum input voltage that can be simultaneously applied between both input and ground
also referred to as the common-mode voltage. In general, the maximum voltage is equal to the supply voltage.

Operating Temperature (Ta): This is the ambient temperature range for which the op-amp will operate within the
manufacturer's specifications. Note that the military grade version (µA741)has a wider temperature range than the
commercial, or hobbyist, grade version (µA741C).

Output Short-Circuit Duration: This is the amount of time that an op-amp's output can be short-circuited to either
supply voltage.

Dynamic Parameters:

1. Open-Loop Voltage Gain (Aol)

The output to input voltage ratio of the op-amp without external feedback.
2. Large-Signal Voltage Gain
This is the ratio of the maximum voltage swing to the charge in the input voltage required to drive the output
from zero to a specified voltage (e.g. 10 volts).
3. Slew Rate (SR)
The time rate of change of the output voltage with the op-amp circuit having a voltage gain of unity (1.0).

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 IC µA 741 OP-AMP

Definition of 741-pin functions:

Pin 1 (Offset Null): Offset nulling, see Fig. 11. Since the op-amp is the differential type, input offset voltage must be
controlled so as to minimize offset. Offset voltage is nulled by application of a voltage of opposite polarity to the
offset. An offset null-adjustment potentiometer may be used to compensate for offset voltage.

Pin 2 (Inverted Input): All input signals at this pin will be inverted at output pin 6. Pins 2 and 3 are very important
(obviously) to get the correct input signals or the op amp can not do its work.

Pin 3 (Non-Inverted Input): All input signals at this pin will be processed normally without inversion. The rest is
the same as pin 2.

Pin 4 (-V): The V- pin (also referred to as Vss) is the negative supply voltage terminal. Supply-voltage operating
range for the 741 is -4.5 volts (minimum) to -18 volts (max), and it is specified for operation between -5 and -15 Vdc.
The device will operate essentially the same over this range of voltages without change in timing period. Sensitivity of
time interval to supply voltage change is low, typically 0.1% per volt. (Note: Do not confuse the -V with ground).

Pin 5 (Offset Null): See pin 1, and Fig. 11.

Pin 6 (Output): Output signal's polarity will be the opposite of the input's when this signal is applied to the op-amp's
inverting input. For example, a sine-wave at the inverting input will output a square-wave in the case of an inverting
comparator circuit.

Pin 7 (posV): The V+ pin (also referred to as Vcc) is the positive supply voltage terminal of the 741 Op-Amp IC.
Supply-voltage operating range for the 741 is +4.5 volts (minimum) to +18 volts (maximum), and it is specified for
operation between +5 and +15 Vdc. The device will operate essentially the same over this range of voltages without
change in timing period. Actually, the most significant operational difference is the output drive capability, which
increases for both current and voltage range as the supply voltage is increased. Sensitivity of time interval to supply
voltage change is low, typically 0.1% per volt.

Pin 8 (N/C): The 'N/C' stands for 'Not Connected'.

1. Supply voltage:
µA 741A, µA 741, µA 741E ------------- ±22V
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 2. Internal power dissipation
DIP package -----------310

3. Differential input voltage ---------------- ±30 V.

4. Operating temperature range

Military (µA 741A, µA 741) -- ---------- -550 to +1250 C.

Commercial (µA 741E, µA 741C) 00 C to +700 C.

5. Input offset voltage --------- 1.0 mV.
6. Input Bias current ------------ 80 nA.
7. PSSR -------------- 30 µV/V.
8. Input resistance ------------- 2MΩ.
9. CMMR -------------- 90
10. Output resistance ---------- 75Ω.
11. Bandwidth -----------1.0 MHz.
12. Slew rate ------------0.5 V/µ sec.

IC555-TIMER:

Pin 1 (Ground): The ground (or common) pin is the most-negative supply potential of the device, which is normally
connected to circuit common (ground) when operated from positive supply voltages.

Pin 2 (Trigger): This pin is the input to the lower comparator and is used to set the latch, which in turn causes the
output to go high. This is the beginning of the timing sequence in monostable operation.
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Pin 3 (Output): Actuation of the lower comparator is the only manner in which the output can be placed in the high
state. The output can be returned to a low state by causing the threshold to go from a lower to a higher level

Pin 4 (Reset): This pin is also used to reset the latch and return the output to a low state. The reset voltage threshold
level is 0.7 volt, and a sink current of 0.1mA from this pin is required to reset the device

Pin 5 (Control Voltage): This pin allows direct access to the 2/3 V+ voltage-divider point, the reference level for the
upper comparator. It also allows indirect access to the lower comparator, as there is a 2:1 divider (R8 - R9) from this
point to the lower-comparator reference input

Pin 6 (Threshold): Pin 6 is one input to the upper comparator (the other being pin 5) and is used to reset the latch,
which causes the output to go low. Resetting via this terminal is accomplished by taking the terminal from below to
above a voltage level of 2/3 V+ (the normal voltage on pin 5).

Pin 7 (Discharge): This pin is connected to the open collector of a npn transistor (Q14), the emitter of which goes to
ground, so that when the transistor is turned "on", pin 7 is effectively shorted to ground. Usually the timing capacitor
is connected between pin 7 and ground and is discharged when the transistor turns "on"

VCO IC 566

1. Operating supply voltage (Vcc) --------- 12V (on less otherwise specified 24V)

2. Operating Supply current -------------- 12.5 m.A.

3. Input Voltage (Vc) -------------- 3Vp-p.

4. Operating Temprature ------------ 0 to 700C

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1. Maximum supply voltage ----------- 26 V

2. Input Voltage ---------------- 3 V(P-P)

3. Power dissipation ------------- 300Mw

4. Operating temperature ----- NE 565- 00 C to 700C (SE 565—55 to +1250 C

5. Supply voltage ----------- 12 V

6. Supply current ---8 mA

7. Output current- (sink) ------- 1
mA (Source) ---------
- 10 m

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 2. ADDER AND SUBTRACTOR

AIM: To design the adder and subtractor using IC741 Op-amp

APPARATUS:
1.OP-AMP-741IC- 1NO

2.RESISTORS -10K Ω -3NO

-3.3K Ω -1NO

-1K Ω-1NO

3.BREAD BOARD

4.POWER SUPPLY

5.DIGITAL MULTIMETER

CIRCUIT DIAGRAM:

ADDER:

Rf=10K Ω ,Rb=Ra=10K Ω,R=3.3k Ω,RL=1K Ω

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Subtractor

Rf=Rb=Ra=R=RL=10K Ω

THEORY:

The adder can be obtained by using either non-inverting mode or differential amplifier. Here the inverting
mode is used. So the inputs are applied through resistors to the inverting terminal and non-inverting terminal
is grounded. This is called “virtual ground”, i.e. the voltage at that terminal is zero. The gain of this
summing amplifier is 1, any scale factor can be used for the inputs by selecting proper external resistors. The
subtractor circuit, input signals can be scaled to the desired values by selecting appropriate values for the
resistors. When this is done, the circuit is referred to as scaling amplifier. However in this circuit all
external resistors are equal in value. So the gain of amplifier is equal to one. The output voltage Vo is equal
to the voltage applied to the non-inverting terminal minus the voltage applied to the inverting terminal;
hence the circuit is called a subtractor.

Procedure:

1. Connect the Adder Circuit as shown in figure(1) on the bread-board.

2. Apply the input voltages from the regulated supplies to the corresponding inputs.
3. Connect the multimeter at the output terminals and note down the values and verify with theoretical
values.
4. Repeat the above steps for different input voltages
5. Now connect the subtractor circuit as shown in figure.
6. Repeat steps 2&3 and record the values.
7. Repeat the above steps for different input voltage

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CALCULATIONS:
ADDER
V0= -Rf/Ra(VA+VB)
SUBTRACTOR
V0= -Rf/Ra(VA-VB)

OBSERVATIONS:

S NO VA VB OUTPUT(p) OUTPUT(T)

RESULT:
The adder and subtractor is designed and observed by using IC741 OP-AMP.

VIVA QUESTIONS:
1.What are the advantages of integrated circuits.
2.What are the popular IC packages available.
3. Mention some of the linear applications of op–amps.
4.Define adder and subtractor.
5.Design an adder circuit with feedback resistor Rf=100KΩ .FIND Ra,Rb &R.

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 (b)Inverting and Non-inverting Comparator

AIM: To study the characteristics of Inverting AND Non inverting comparator.

Apparatus:

1. Cathode Ray Oscilloscope

2.Dual channel power supply

3.Bread board

4.Resistors: 10k Ω (2)

5.Op-Amp LM741

CIRCUIT DIAGRAM:

INVERTING:

NON-INVERTING:

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Theory:
 Voltage comparator is a circuit which compares unknown signal voltage with a known reference
voltage.
 Voltage comparator consists of an op-amp operated in open-loop with signal voltage applied at one
input and known reference voltage at the other input.
 A fixed reference voltage Vref is applied to the inverting terminal and a time varying signal is applied
to the non-inverting terminal of the op-amp.
 Op-amp, in open-loop, produces one of the two saturation voltages + Vsat at the output.
 When Vref is positive, the circuit acts as positive comparator and when Vref is negative, the circuit
acts as negative comparator.
Procedure:
1. Construct the circuit as shown below in figure
2. Set the voltage in V1 to 7V
3. Set the reference voltage V2 to +6V.
4. Observe simultaneously the input and output waveform using oscilloscope. Repeat
the above steps by changing the reference voltage V2 to - 2V.

WAVEFORMS:

RESULT:
Thus, the use of op-amp as voltage comparator and was studied.

VIVA QUESTIONS:
1.What are the ideal characteristics of an op-amp.
2.In which mode op-amp comparator will operate.
3.what configuration the op-amp is employed in voltage comparator..
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 3.INTEGRATOR AND DIFFERENTIATOR
AIM: To design and test an op-amp differentiator and integrator using IC 741
APPARATUS: 1.OP-AMP-1 NO
2.BREAD BOARD-1 NO
3. CAPACITOR – 0.01µf,0.1µf- 1 NO
4. RESISTOR -10kΩ,100kΩ,5.6kΩ - 1 NO
5.CATHODE RAY OSCILLOSCOPE

CIRCUIT DIAGRAMS :-
INTEGRATOR AND DIFFERENTIATOR

R1=5.6K Ω,C1=0.1K Ω,Rf=100k Ω. R1=10K Ω,C1=0.1K Ω,Rf=100k Ω.

THEORY:-

The operational amplifier can e used in many applications. It can be used as differentiator
and integrator. In differentiator the circuit performs the mathematical operation of differentiation that is
the output waveform is the derivative of the input wave form for good differentiation, one must ensure
that he time period of the input signal is larger than or equal to RfC1.the practical differentiator
eliminates the problem of instability and high frequency noise.
the op-amp circuit would generate an output voltage proportional to the magnitude and
duration that an input voltage signal has deviated from 0 volts. Stated differently, a constant input signal
would generate a certain rate of change in the output voltage: differentiation in reverse.

PROCEDURE:
1 connect the differentiator circuit as shown in fig 1.adjust the signal generator to produce a 5 volt peak
sine wave at 100 Hz.

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2.observe input Vi and Vo simultaneously on the oscilloscope measure and record the peak value of Vo
and the phase angle of Vo with respect to Vi.
3.Repeat step 2 while increasing the frequency of the input signal. Find the maximum frequency at
which circuit offers differentiation. Compare it with the calculated value of fa Observe & sketch the
input and output for square wave.
4.Connect the integrator circuit shown in Fig2. Set the function generator to produce a square wave of
1V peak-to-peak amplitude at 500 Hz. View simultaneously output Vo and Vi.
5.Slowly adjust the input frequency until the output is good triangular waveform. Measure the amplitude
and frequency of the input and output waveforms.

6.Verify the following relationship between R1Cf and input frequency for good integration
f>fa & T< R1C1
Where R1Cf is the time constant
7.Now set the function generator to a sine wave of 1 V peak-to-peak and frequency 500Hz. Adjust the
frequency of the input until the output is a negative going cosine wave. Measure the frequency and
amplitude of the input and output waveforms.

WAVE FORMS:-

Differentiator

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 INTERGRATOR

OBSERVATIONS:

S.No Capacitance Resistance Square Triangle

Cf R1 Wave O/P Wave O/P

in volts in volts

RESULT:-

The integrator circuit is designed by using A 741and the output waveforms are noted down for
different values of Capacitance.

VIVA QUESTION:
1.Define Integrator and differentiator.
2. What are the limitations of the basic differentiator circuit?

3.What are the limitations of the basic Integrator circuit?

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 4.ACTIVE FILTER APPLICATIONS

(A) 1ST ORDER LOW PASS FILTER

Aim :
To verify the operation of first order Low Pass Filter and to construct frequency response plot for the low pass filter
from the experimental data.

Apparatus:
1. Cathode ray oscilloscope

2. Bread board

3.singal generator.

4.IC 741 - I No.

5.Resistor -10 k - 2 No.

- 3.3 k - 1 No.

6. Capacitor -0.01 µF I No.

SPECIFICATIONS OF 741 IC:

Maximum Supply voltage = +22 v

power dissipation = 500 mw

Maximum input voltage = 15 v

Large Signal dc voltage gain = 2x 105 v

CMRR = 90 dB

Operating temperature = 00 to 700

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CIRCUIT DIAGRAM :

Theory :
A low pass filter is a filter that passes only low frequencies and attenuates high frequencies. The range of frequencies
that arte passed upto FH Comes under pass band and other Frequencies greater than FH Come under stop band. Since

Op- amp is used in the non inverting configuration hence it does not load From the RC network Resistors R1 and RF

determine the gain of the Filter. Since a single RC network is used. It is a First order low pass Filter.

Cut off Frequency is the frequency at which the magnitude of the gain is 0.707 times its. Pass band value.

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APPLICATIONS :

Communications and signal processing and in one from or the other in almost all sophisticated electronic
instruments.

PROCEDURE :

1. Connect the circuit as shown in the Fig. Apply power to the Circuit. Adjust the input voltage V in to 1Vp-p.

2. Vary the Frequency From 100 HZ .to 100KHz and measure the output Voltage every time using
oscilloscope.
3. Calculate the cut Off Frequency FH and the pass band gain using the following equations.

fH = 1/2  RC

Pass band gain in dB = 20 log[ 1+ (Rf/R1)]

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OBSERVATIONS:

Vin = 1V

Frequency (Hz) V0 (P – P) V0/ Vin 20 log V0/ Vin

RESULT:

The operation of Low pass Filter is verified.

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 (B) 1ST ORDER HIGH PASS FILTER

AIM :

To verify the operation of first order High Pass Filter and to construct a frequency response plot for the High Pass
Filter from the experimental data.

APPARATUS :

1.Cathode Ray oscilloscope

2.Bread board

3.Signal generator

4.Op amp ----- A 741 IC - I No

5.Resistors ------ 10 k - 1 No

3.3 k -I No

6.Capacitors ---- 0.05F -I No.

Specifications of 741 IC :

Maximum Supply Voltage = + 22v

Power dissipation =500 mw

Maximum input voltage gain = + 15v

Large Signal de voltage gain = 2 x105

CMPR = 90 dB

Operating temperature = 0o to 70o

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CIRCUIT DIAGRAM :

THEORY :

Filters are used in circuits that pass electric signals of specified band of frequencies and alternates the signals of
frequencies out side the band is called frequency selective electric filter.

High pass filters can be formed simply by inter changing frequency determining resistors and capacitors in Low pass
filter. The band of frequencies above the cut off Frequency FL come under pass band and below FL, come under
stop band.

Cut off Frequency is the frequency at which the magnitude of the gain is 0.707 times the pass band value.

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PROCEDURE :

1. Connect the circuit as shown in the Fig. Apply power to the circuit. Adjust the input voltage Vin to 1VP-P.

2. Vary the Frequency From 100 HZ to 100 KHZ and measure the output voltage every time using
oscilloscope.

3. Calculate the Cut off. Frequency FH and the pass and gain using the following equations.
F 2 = 1/2 RC

Pass band gain in dB = 20 log [1+(Rf/R1)]

OBSERVATIONS:
Vin = 2V

Frequency V0 V0/Vin 20log(V0/vin)

RESULT:
The Operation of High Pass Filter is verified and the characteristics are drawn.

Fh =

VIVA QUESTIONS:
1.Define low pass and high pass filter.

2. What is cut-off frequency of first order high pass filter.

3. what is cut off frequency of the low pass filter .

4. What is the voltage gain of the active high pass filter

5. How the high pass filter could be converted to a low pass filter .

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 5. ACTIVE FILTERS APPLICATIONS
(A)BAND PASS FILTER

AIM: a) To design the Band pass filter (wide band).

b) To plot and observe the frequency response of band pass filter.

APPARATUS:
* Signal generator (1MHZ)
* CRO (20MHZ)
* Multimeter
* Connecting patch Chords
* Bread board

CIRCUIT DIAGRAM:

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THEORY:
1. A BPF has a pass band between two cutoff frequencies fH, fL such that fH > fL
2. When the input frequency is less than the designed frequency of fL , the gain of the BPF increases to
its3dB level . After reaching the total pass band region, the gain of the filteris constant up to its designed f
H (high cut off frequency) as stated above.
3 Once the input frequency reaches to the fH, the gain of the BPF decreases to its –
3dB level. From that point the gain of the filter gradually decreases.
4. There is a phase shift between input and output voltages of BPF in its Pass Band region. This filter pass
es all frequencies equally i.e. output and input voltages are equal inamplitude for all frequencies, with the ph
ase shift between the two, a function of frequency. This highest frequency up to which the input andout
put amplitudes remain equal isdependent on the unity gain bandwidth of the Op Amp. At this frequen
cy, the phase shift between input and output is maximum.

FILTER DESIGN:
Select the cut off frequencies
fH = Higher cut off frequency
fL = Lower cut off frequency
fC =√(fL.fH)

PROCEDURE:
1. Make the circuit connection as shown in figure.
2. Connect the signal generator to input terminals. And connect the C.R.O at out put terminals of the circuit
3. Apply the input signal frequency from 100Hz to 10KHz .
4. Record the input frequency, Input voltage and Output voltage. Find the gain of the
Output voltage B.P.F using the formula. dB is equal to 20LogVo/Vin

OBSERVATION TABLE:

30 | P a g e
 fin Input Vin VO Gain Gain in dB
frequency
Input voltage Output voltage VO/Vin 20 log VO/Vin

RESULT: The band pass filter has been designed for chosen fL= , fH = and frequency response is
plotted between Output voltage gain (in dB) vs input frequency.

31 | P a g e
 (B)BAND REJECT FILTER
AIM: a. To design the Band reject filter (wide band)
b. To plot and observe the frequency response of band reject filter.

APPARTUS:
* 1MHz Signal generator
* 20MHz C.R.O
* Connecting patch Chords
* Multimeter

* RESISTORS
* BREAD BOARD

CIRCUIT DIAGRAM:

32 | P a g e
THEORY:
1. A BRF has a stop band between the cutoff frequency fH&fL such tha fH < fL.

2. When the input frequency is less than the designed frequency of fH ,the gain of the BRF is constant up
to fH .In other words it allows the frequencies equally well that is output and input voltages are
equal in amplitude
3. By increasing the input frequency after fH , the gain gradually decreases to its center frequency fC .
After this increases to its 3db level. After reaching the total pass band region. The gain of the filter is
again constant up to its designed fH (High cutoff frequency) as stated above.

4. Figure shows the phase shift between input and output voltages of BPF in its “Pass band region”. This
filterpasses all the frequencies equally well i.e. output and input voltages are equal in (magnitude) amplitude
for all frequencies with the phase shift between the two functions of frequency. This highest frequency up
to which the input and output amplitude remains equal. It is dependent on the unity gain bandwidth of the
Op-Amp. At this frequency however, the phase shift between the input and output is maximum.

FILTER DESIGN:
Select the cut off frequency of BRF fH, fL

fH = Higher cutoff frequency

fL = Lower cutoff frequency

fC=√fL.fH

PROCEDURE:
1. Make the circuit connection as shown figure.
2. Connect the signal generator to input terminals. And connect the C.R.O at out put terminals of the
circuit.
3. Apply the input signal frequency from 10Hz to 10KHz insteps and record the input frequency, in put
voltage and out put voltage find the gain of the B.P.F using the formula. Calculate the gain magnitude in
db which is equal to 20log(Vo/Vin)

33 | P a g e
 OBSERVATION TABLE:

fin Vin VO Out put Gain Gain in dB

Input Input voltage voltage Vo/Vin 20log(Vo/Vin)
frequency

RESULT: The band rejected filter has been designed for chosen fL= ,

Fh=________

and frequency response is plotted between input frequency and Output voltage gain (in d.B).

VIVA QUESTIONS:
1.What is pass band and stop band.

2.Define Band pass filter

3.Define Band reject filter.

4.What is the center frequency of wide band filter.

5.what is the Quality factor of wide band pass filter.

34 | P a g e
 6. IC 741 Oscillator Circuit
(A) RC PHASE SHIFT
AIM:

To construct a RC phase shift oscillator to generate sine wave using op-amp.

APPARATUS:

1.Cathode Ray Oscilloscope

2.Dual channel Power supply

3.Bread board

4.Resistrors: 3.3k, 1.2k, 10k, 390kΩ:

5.capacitors 0.1uf

6.Op Amp-UA 741

CIRCUIT DIAGRAM:

35 | P a g e
THEORY:

Basically, positive feedback of a fraction of output voltage of a amplifier fed to the input in the
same phase, generate sine wave.
The op-amp provides a phase shift of 180 degree as it is used in the inverting mode.An additional
phase shift of 180 degree is provided by the feedback RC network. The frequency of the oscillator fo is
given by

fo = 1 / √6 (2 π R C)
Also the gain of the inverting op-amp should be atleast 29,or Rf ͇ 29 R1

MODEL WAVE FORM:

T
OBSERVATIONS:

Time period = Frequency =

Amplitude =

Procedure:
1. Connect the circuit as shown in fig. With the design values.
2. Observe the output waveforms using a CRO.For obtaining sine wave adjust Rf.
3. Measure the output wave frequency and amplitude.

Result:
The sine wave output signal is obtained in RC phase shift oscillator.
Frequency f =

36 | P a g e
 (B)WEIN BRIDGE OSCILLATOR

AIM:
To construct a wein bridge oscillator for fo = 1 khz and study its operation

APPARATUS REQUIRED:

1. Cathode Ray Oscilloscope

2.Dual channel power supply

3.Bread board

4.Resistors: 1.5k(2), 10k,

5.Capacitors: 0.01uf, (2), 0.1uf

CIRCUIT DIAGRAM:

THEORY:

In wein bridge oscillator ,wein bridge circuit is connected between the amplifier input terminals
and output terminals . The bridge has a series rc network in one arm and parallel network in the adjoining
arm. In the remaining 2 arms of the bridge resistors R1and Rf are connected . To maintain oscillations
total phase shift around the circuit must be zero and loop gain unity. First condition occurs only when the
bridge is p balanced . Assuming that the resistors and capacitors are equal in value ,the resonant
frequency of balanced bridge is given by

Fo = 0.159 / RC

Design:
37 | P a g e
 At the frequency the gain required for sustained oscillations is given by 1+Rf /R1 = 3 or
Rf = 2R1
Fo = 0.65/RC and Rf = 2R1

PROCEDURE:

1.Connections are made as per the diagram .R,C,R1,Rf are calculated for the give
value of Fo using the design .
2. Output waveform is traced in the CRO .

CALCULATION:

Theoretical: F = 1/(2*3.14*R*C)

Practical: F = 1/T

RESULT:

Hence the WEIN BRIDGE OSCILLATOR is studied and its output waveform traced.

VIVA QUESTIONS:

1. What is the function of lead-lag network in Wein bridge oscillator?

2. Wein bridge oscillator uses positive and negative feedback. Why?

38 | P a g e
 7. FUNCTION GENERATOR
AIM: To design a function generator to generate a square wave and a triangular wave using 741 Op-
Amp

APPARATUS:

Op Amp A741 – 2No.s

Resistors 3.3K, 2.2K, 1K

Capacitors 0.1F or Decade Capacitance Box

CRO,

CRO Probes

Power Supply +12V and -12V 2No.s

CIRCUIT DIAGRAM:

THEORY:

The function generator that generates triangular as well as square wave is shown in the figure. It
requires two OPAMPS. The first works as a regenerative comparator while the second works as an
integrator. The voltage at node B i.e. the voltage across the capacitor which is a triangular wave shape but

39 | P a g e
the sides of the triangular waveform are exponential rather than straight lines. To obtain a linear rise, it is
required that the capacitor has to be charged with a constant current.
With the comparator output at its positive saturation level the integrator o/p decreases at a linear rate
until the lower trip point of the comparator. The comparator Output switches rapidly to its negative
saturation level and the integrator output then increases linearly. When the integrator output reaches the
upper trip point, the comparator again switches its state and the operation repeats.

f= R2
The frequency is 4R1R3C

The performance limits are determined by comparator’s slew rate, integrator bandwidth at high frequencies
and integrator drifts at low frequencies.

PROCEDURE:

 Make connections are as shown in the figure/circuit diagram.

 Monitor the waveforms at nodes A &B on an Oscilloscope.
 Verify that the output is square and triangular waveforms. By varying the
capacitance value, check the frequency of the waveforms with the theoretical

values.

f= R2

4R1R3C

40 | P a g e
OBSERVATIONS:

Sl No. C1(F) Frequency of Peak to peak Peak to peak

waveforms in
Amplitude Amplitude of
Hz
Square Wave (V
Of Triangular wave
)
(V)

MODEL GRAPH:

RESULT: The triangular and square wave forms are observed by designing function generator.

VIVA QUESTIONS:

1) In which region the op amp is acts like a wave form generator

2) Another name for square wave generator is --------------------

3) The triangular wave amplitude is depends on --------------------

41 | P a g e
 8.IC 555 TIMERS
(A) MONOSTABLE OPERATATION IN CIRCUIT
AIM:

To design and construct a Monostable Multivibrator using IC 555 with a time period of 5 seconds.

APPARATUS:

1.IC 555 - 1 no

2.LED -1 no.

3.Resistors –1M Ohms.

4.Capacitors – 4.7F, 0.01 F

5.Bread _ board - 1 No.

5.Power Supply 5V

6.Connecting Wires

CIRCUIT DIAGRAM:

fig.1 PIN DIAGRAM OF IC555 TIMER

42 | P a g e
 fig 2. MONOSTABLE MULTI VIBRATOR USING IC 555 TIMER

THEORY:
The Timer can be used either in Astable or Monostable modes of operation. In the monostable mode
the timer is controlled by an external capacitor and an external resistor. In the astable mode of operating
features of interest are frequency and duty cycle of output waveforms. They are controlled by an external
transistor.

MONOSTABLE MULTIVIBRATOR:

The 555 Timer connected for the monostable operation is shown in the fig. 2. The timing capacitor
CA is changed from Vcc through RA. In stable state the capacitor is held in the discharge mode. At the

moment a negative trigger is applied at PIN 2, it sets the flip-flop and a s a result transistor T1 is turned off

and allows the timing cycle to begin. The capacitor starts charging from zero to 2/3 Vcc and is calculated

from the formulae.....

2/3 Vcc = Vcc (1-e-T/RA.CA)

43 | P a g e
Hence, time period of monostable multivibrator is

T= 1.1 RA CA

PROCEDURE:

MONOSTABLE MULTIVIBRATOR:

 Connections are made according to the circuit diagram.

 The circuit is triggered by a negative pulse or just connects it to ground point and back to Vcc (at pin

4).
 Immediately the output goes high and LED starts glowing.
 After the time T1 = 1.1 RA CA , the LED GLOWS OFF. The ON time is measured by a watch or

measured by the CRO( for milliseconds )

 Compare this value with the theoretical value.

OBSERVATIONS :

a. Theoretical TON =

b. Practical TON =

RESULT :
The function of the timer circuit as Monostable multivibrators has been verified and practical time
period is found.

44 | P a g e
 (B)ASTABLE MULTIVIBRATOR

AIM:

To design and as an asymmetrical construct a Astable multivibrator and symmetrical square wave
generator using IC 555.

APPARATUS:
1. IC 555 - 1 no

2.Resistors -3.8 K.Ohms, 3.3K.Ohms, 330 Ohms.

3.Capacitor – 0.1 F, 0.01F

4.Power supply 5V

5.Connecting Wires

6.Bread _ board - 1 No.

CIRCUIT DIAGRAM:

fig.1 PIN DIAGRAM OF IC555 TIMER

45 | P a g e
 fig 2. ASTABLE MULTIVIBRATOR USING IC 555 TIMER

THEORY:

The Timer can be used either in Astable or Monostable modes of operation. In the monostable an
external capacitor and an external resistor control mode the timer. In the astable mode of operation, features
of interest are frequency and duty cycle of output waveforms. They are controlled by an external resistors
and capacitor.

ASTABLE MULTIVIBRATOR:

The Astable multivibrator is as shown in the figure 2. The capacitor charges through R 1 and R2

from Vcc until the capacitor voltage just exceeds from the 2/3 Vcc value. This voltage will reset the flip-

flop. As a result the transistor T1 goes ON and capacitor starts discharging through R2. The discharge

continues until the voltage across the capacitor is just less than Vcc/3. Then Flip-Flop will be in the Set

state and the capacitor to charge again. The process continues which produces the square wave as output.
The Charge time and Discharge time are

46 | P a g e
 TC= 0.693 (R1+R2) C

and

TD = 0.693 R2C

Where TC and TD are charge time period and discharge time period;

R1 and R2 are external resistors and C is external capacitor

Therefore, the total time period TC+ TD is

T = 0.693 (R1 + 2R2) C

PROCEDURE:

ASTABLE MULTIVIBRATOR:

 Connections are made according to the circuit diagram

 The output waveforms are observed on CRO and the time periods are noted.
 The ON time Tc and OFF time TD are compared with the theoretical values. Therefore, the total time period is
calculated.
 The duty cycle d is verified with the theoretical value.
 Then the diode is placed across pin 2 and pin 7 and the value of Ra is varied so as to obtain a square wave.
The value of Ra is noted down.

47 | P a g e
OBSERVATIONS :

Theoretical :TON = TC =

TOFF = TD =

Practical : TON = TC =

TOFF = TD =

Total Time Period = T = TON + TOFF =

Frequency = f = 1/T =

Duty cycle = TON / (TON + TOFF) * 100%

Theoretical Duty cycle =

Practical Duty cycle =

RESULT :

The function of the timer circuit as astable multivibrators has been verified.

For asymmetrical square wave

Frequency f =

Duty Cycle d =

For Symmetrical square wave

R1 is found to be

48 | P a g e
VIVA QUESTIONS:

1. What is the basic principle of 555 to act like a astable multivibrator?

2. How astable mode of 555 can be changed to square wave generator?

3. How the duty cycle of astable multivibrator using IC555 can be changed?

4. What is the basic principle of 555 to act like a monostable multivibrator?

5. What is the difference between astable multivibrator and mono stable multivibrator using IC 555

49 | P a g e
 9.SCHMITT TRIGGER USING 555

AIM: To construct and study of the Schmitt Trigger using IC 555 timer.

APPARATUS:
1) IC A 741 OP -AMP –1No.

2) IC 555 timer –1No

3) Resistor 10 k - 2 No

4) Resistor 47 k -1No

5) Resistor 100k - 2 No

6) Capacitors 0.01  F - 2 No

7) DC Power supply 5 V- 1No

8) DC Power

9) Function Generator

10 )CRO & Probes.

CIRCUIT DIAGRAM:

Schmitt trigger using IC A 741

50 | P a g e
 Schmitt trigger using IC 555

THEORY
SCHMITT TRIGGER USING OP AMP 741 :-

Figure shows the schmitt trigger circuit op,Amp 741. The schmitt trigger is also knows as a
regenerative comparator " The i/p voltage is applied to the inverting terminal of op- amp and feedback
voltage to the non- inverting terminal. The i\p voltage Vi triggers the O/p Vo every time it exceeds certain
voltage levels. These voltage levels are called upper threshold voltage ( VuT ) & longer threshold voltage
(VLT). The hysteresis width is the difference between these two threshold voltages.

As long as Vi is less than VuT the o\p VO remains constant at + V sat. When VP is just greater VuT .
the o\p regenerative switches to - Vsat and remains at this level as long as Vi > VuT The i/p Voltage Vi
must become lesser than VLT in order to cause Vo to switch from - v sat to + Vsat, because of the
hysterisis, the circuit triggers at a higher the hystersis, the circuit triggers at a higher voltage for increasing
signals than for decreasing orves. If peak to peak 1\p signal vi where smaller than VH then the circuit,
having responded at, a threshold voltage by a transistor in one direction never reset itself.

SCHMITT TRIGGER USING IC 555

51 | P a g e
The use of 555 timer as a schmitt trigger as shown in Figure. Here the two internal comparators are tled together and
externally biased at Vcc/2 through R1 & R2 Since the upper comparator will trip ar 2/3 vcc & lower comparator at

1/3 Vcc, the bias provided by R1 & R2 is centered with in these two thresholds thus, a sine wave of sufficient
amplitude

(> Vcc/6 = 2/3 Vcc - Vcc/2) to exceed the reference levels causes the internal Flip Flop to alternately set
and reset, providing a square wave o/p as shown in Fig, It may be noted that unlike conventional
multivibrator, no frequency division is talking place and frequency of square wave remains the same as that
of i/p signal.

PROCEDURE:

1. Construct the circuit as shown in Figure.

2. Apply Sinusoidal signal of 20 v (p-p) amplitude and frequency of 1KHz to i\p signal, with vi =ov measure
the o\p voltage
3. Slowly increase the i/p voltage vi from o volt to maximum by using potentiometer V1 and note down the
UTP voltage
4. Similarly, decrease the i/p voltage from high to low by using vi and note down the LTP Voltage.

OBSERVATIONS:

Using IC 555.

Vin UTP LTP Hystersis

52 | P a g e
Using Op- amp IC 741:

Vin UTP LTP Hystersis

INPUT AND OUTPUT WAVEFORMS:

RESULT:
The function of 741 IC 555 timer as Schmitt trigger are verified and hysteresis UTP & LTP values are
calculated.

53 | P a g e
VIVA QUESTIONS:

1. How can you obtain triangular wave using schmitt trigger?

2. Why Schmitt trigger is called regenerative comparator?

3. What is hysteresis voltage in Schmitt trigger?

54 | P a g e
 10. PLL Using 1C 565
Aim: To study the operation of PLL using NE/SE 565.

Apparatus:

• 1C chip NE/SE 565.

• CRO.
• Signal generator
• 0.001 U.F, 1 u,F capacitors.

• 6.8K resistor

CIRCUIT DIAGRAM:

Theory:
A Phase Lock Loop (PLL) is an electronic circuit, which locks the phase of the input signal with that
of the output by keeping them synchronised. It achieves this through a closed loop feedback mechanism that
compares the input signal with the output and makes the necessary corrections so that the phase remains
synchronous. If the inputs signal changes, the phase detector will recognise the change in frequency and
force the VCO to change the output accordingly, such that the output is equal to the new input frequency,
thereby eliminating the error value from the phase comparator.The free running frequency "ƒc" occurs when
the PLL has no lock or if there is no input signal, or if the signal is outside the lock range.The range of
frequencies over which the PLL will track an input signal and remain locked is the lock frequency. This
range is above and below the VCO free running frequency. The PLL will track and lock to any input
frequency in this range. If the input signal happens to be out of this lock range then the PLL will not be able
to track it.

55 | P a g e
PLL applications:
1. Frequency multiplication /division

2. Frequency translation.
3. AM detection.
4. FM demodulation

5. FSK demodulator.

PIN DIAGRAM:

PROCEDURE:
1. Make connections of the PLL as shown in fig
2. Measure the free running frequency of" VCO at pin 4.wilh the i/p signal Vin , set equal to
zero. Compare it with the calculated value = 0.25/RTCT
3. Now apply the i/p signal of 1 VPP, square wave at a 1 KHz to pin 2.connect one channel
of the scope to pin2 and display this signal on the scope.
4. Gradually increase the i/p frequency till the PLL is locked to the input frequency. This
frequency f1 gives the lower end of the capture range.Go on increasing the i/p frequency, till
PLL tracks the i/p signal, say. to a frequency "f2". This frequency "f2" gives
the upper end of the lock range. if i/p frequency is increased further, the loop will get
unlocked.
5. Now gradually decrease the i/p frequency t i l l the PLL is again locked. This is the frequency

56 | P a g e
 ( f 3 ) the upper end of the capture range. Keep on decreasing the i/p frequency until the
loop is unlocked. This frequency ‘f4’ gives lower end of lock range.
6. The lock range ∆fL=f2-f4. Compare it with the calculated value of ± 7.8fo/12. Also the
capture range is ∆fc= (f3 -f1 ). Compare it with the calculated value of capture range.

RESULT:
Theoretical values of lock range, capture range, free running frequency are compared with the
practical values.

VIVA QUESTIONS:

1. Define Lock-in range.

2. Define capture range.
3. What are the applications of PLL?
4. What are the 3 stages of PLL characteristic?

57 | P a g e
 11. DESIGN OF VCO USING IC 566

Aim:
i) To observe the applications of VCO-IC 566
ii) To generate the frequency modulated wave by using IC 566

Apparatus required:

1.IC 566-1No
2.Resistors-10K,1.5k
3. Capacitors-0.1 F ,100 pF-1NO

4. Regulated power supply-0-30 V, 1 A1No

5. Cathode Ray Oscilloscope-0-20MHZ-1No

6. Function Generator-0.1-1Mhz-1No

Circuit Diagram:

Theory: The VCO is a free running Multivibrator and operates at a set frequency fo called free
running frequency. This frequency is determined by an external timing capacitor and an external
resistor. It can also be shifted to either side by applying a d.c control voltage vc to an appropriate

58 | P a g e
 terminal of the IC. The frequency deviation is directly proportional to the dc control voltage and
hence it is called a “voltage controlled oscillator” or, in short, VCO.
The output frequency of the VCO can be changed either by R1, C1 or the voltage VC at the
modulating input terminal (pin 5). The voltage VC can be varied by connecting a R1R2 circuit.
The components R1 and C1 are first selected so that VCO output frequency lies in the centre of the
operating frequency range. Now the modulating input voltage is usually varied from 0.75 VCC
which can produce a frequency variation of about 10 to 1.

Design:
1. Maximum deviation time period =T.
2. fmin = 1/T.
where fmin can be obtained from the FM wave
3. Maximum deviation, ∆f= fo - fmin
4. Modulation index β = ∆f/fm
5. Band width BW = 2(β+1) fm = 2 (∆f+fm)
6. Free running frequency,fo = 2(VCC -Vc) / R1C1VCC

Procedure:
1. The circuit is connected as per the circuit diagram shown in Fig1.
2. Observe the modulating signal on CRO and measure the amplitude and frequency of the
signal.
3. Without giving modulating signal, take output at pin 4, we get the carrier wave.
4. Measure the maximum frequency deviation of each step and evaluate the modulating Index.
mf = β = ∆f/fm

59 | P a g e
Waveforms:

Sample readings:

VCC=+12V; R1=R3=10K ; R2=1.5K ; fm=1KHz

Free running frequency, fo = 26.1KHz fmin =
8.33KHz
∆f= 17.77 KHz
β = ∆f/fm = 17.77

Band width BW ≈ 36 KHz

Result:
Frequency modulated waveforms are observed and modulation Index, B.W required for FM is
calculated for different amplitudes of the message signal.

60 | P a g e
 12. IC VOLTAGE REGULATOR: (Using IC 723)

Aim: To design a low voltage variable regulator of 2 to 7V using IC 723.

Apparatus Required:
1. IC 723-1no
2. Resistors-3.3K ,4.7K ,100k-1no
3. Variable Resistors-1K , 5.6K-1no
4. Regulated Power supply-1no

Circuit Diagram:

Theory:

A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load
current and input voltage variations. Using IC 723, we can design both low voltage and high
voltage regulators with adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of voltages Vo < Vref,
where as for high voltage regulator, it is VO > Vref. The voltage Vref is generally about 7.5V. Although
voltage regulators can be designed using Op-amps, it is quicker and easier to use IC voltage
Regulators.
61 | P a g e
 IC 723 is a general purpose regulator and is a 14-pin IC with internal short circuit
current limiting, thermal shutdown, current/voltage boosting etc. Furthermore it is an adjustable
voltage regulator which can be varied over both positive and negative voltage ranges. By simply
varying the connections made externally, we can operate the IC in the required mode of operation.
Typical performance parameters are line and load regulations which determine the precise
characteristics of a regulator.

Pin Configuration:

Design of Low voltage Regulator:

Assume Io= 1mA,VR=7.5V RB = 3.3 K
For given Vo
R1 = ( VR – VO ) / Io R2 = VO / Io

PROCEDURE:
a) Line Regulation:
1. Connect the circuit as shown in fig 1.

2. Obtain R1 and R2 for Vo=5V

3. By varying Vn from 2 to 10V, measure the output voltage Vo.
4. Draw the graph between Vn and Vo as shown in model graph (a)
5. Repeat the above steps for Vo=3V

b) Load Regulation: For Vo=5V

1. Set Vi such that VO= 5 V
2. By varying RL, measure IL and Vo
3. Plot the graph between IL and Vo as shown in model graph (b)
4.Repeat above steps 1 to 3 for VO=3V.

62 | P a g e
 a)Line Regulation:
RL=10KΩ

Vi(V) Vo(V)

b) Load Regulation:
Vi set to 5V

RL(Ω) Vo(V)

Model graphs:

a) Line
9 Regulation b) Load Regulation

Results:
Low voltage variable Regulator of 2V to 7V using IC 723 is designed. The line and load
regulation characteristics are plotted.

VIVA QUESTIONS:

63 | P a g e
1. What are the main advantages of voltage regulators?

2. Define line regulation or source regulation.

3. Define Load regulation.

4. What are the limitations of 723 regulators?

5. What is current limiting ability?

64 | P a g e
. 13. THREE TEMINAL VOLTAGE REGULATOR-7805 & 7905

AIM: 1) To construct and study the 3-terminal fixed voltage regulator using IC7805 and 7905 .
2) To find line regulation and load regulation of the IC regulator

APPARATUS:
1. MultiMeter – 1No
2. Power supply -1No
3. Breadboard – 1No

COMPONENTREQUIRED:
0.1µf Capacitors – 2no.
IC’s 7805, 7809, 7905

CIRCUIT DIAGRAM:

I. 7805 fixed ‘+ ve’ voltage regulator:

65 | P a g e
 II. 7905 fixed ‘- ve’ voltage regulator:

Line regulation = ∆Vo/∆Vin

Load regulation = ∆Vo/∆Vin

THEORY:
A voltage regulator IC maintains the output voltage at a constant value. 7805 IC, a member of 78xx series of
fixed linear voltage regulators used to maintain such fluctuations, is a popular voltage regulator integrated
circuit (IC). ... 7805 IC provides +5 volts regulated power supply with provisions to add a heat sink.

Some of the important features of the 7805 IC are as follows:

 It can deliver up to 1.5 A of current (with heat sink).

 Has both internal current limiting and thermal shutdown features.
 Requires very minimum external components to fully function.

PROCEDURE:
1. Make connections of fig (1.a) on breadboard.
2. Connect input to Power supply and output to digital multimeter.
3. Apply input voltage of 7V to input and note down output voltage.
4. Vary input voltage from 7V to 20V and record the output voltages.
5. Connect fig (1.b) and repeat steps (2) to (4).
66 | P a g e
6. Calculate line regulation of IC’s used.

OBSERVATION TABLE:
7805 7905

Vin Vout

Vin Vout

RESULT: The operation of voltage regulator using 7805 and 7905 are observed practically to be 5v

VIVA QUESTIONS:
1.How does a voltage regulator work?
2.What is a voltage regulator?
3.Why use three terminals in ceilling fan?
4.What is the principle of three terminal voltage regulator?
5.What is the voltage regulator that have a 2A output?

14.4BIT DAC AND 4BIT ADC

67 | P a g e
 a)4BIT DAC

AIM: To design a Digital to Analog Converter using R – 2R ladder network.

APPARATUS:

 1 A 741 Op- Amp

 Resistors (R and 2R) - 1Kohm, 2.2 K ohm
 Voltmeter (0-10) V
 Power Supply –12V and +12V , 5V fixed power supply
 Connecting Wires

CIRCUIT DIAGRAM

THEORY:
68 | P a g e
The Digital to Analog Converter uses a summing Amplifier with a R- 2R ladder network. It has n electronic
switches called controlled by binary inputs. These switches are single pole double throw type. If a particular
switch is one it connects the resistor to the reference voltage. The circuit can use either a positive or negative
reference voltage. The Amplifier is connected in inverting mode. The Op-Amp acts as current to voltage
converter. If the reference voltage is negative the output is positive and vice versa. The switches are in
series with resistance and therefore their ON resistance must be very low and they should have zero offset
voltage.

The above circuit is R-2R Ladder DAC, which avoids the use of wide range of resistors. This makes the
circuit suitable for monolithic fabrication.

PROCEDURE:

 Build up the circuit as shown in the figure

 The two supply voltages for Op- Amp are +12V and –12V
 Note the corresponding output values in voltmeter by giving digital inputs from 0000
to 1111
 Plot the Digital input versus Analog output voltage.

OBSERVATIONS:

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 A B C D O/p voltage

(in Volts)

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

RESULT:

The digital inputs are applied and the corresponding Analog output voltage is measured and the output is
found to be linearly varying with digital input.

b)4bit ADC
AIM: To design a Analog to digital Converter using flash type ADC network
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APPARATUS:

 1 A 741 Op- Amp

 Resistors (R and 2R) - 1Kohm, 2.2K ohm
 Voltmeter (0-10) V
IC 74LS08 ( two input AND gate)
IC 74LS86 (two input EX-OR gate)

CIRCUIT DIAGRAM:

2 Bit Flash Type ADC

THEORY:

In a 3 input ADC, if the analog signal exceeds the reference signal, comparator turns on. If all
comparators are off, analog input will be between 0 and V/4.If C1 is high and C2 is low input will be
between V/4 andV/2.If C1 andC2 are high and C3 is low input will be between 3V/4 and V.
Flash converters are extremely fast compared to many other types of ADCs, which usually narrow in
on the "correct" answer over a series of stages. Compared to these, a flash converter is also quite simple and,
apart from the analog comparators, only requires logic for the final conversion to binary. For best accuracy,
often a track-and-hold circuit is inserted in front of the ADC input. This is needed for many ADC types
(like successive approximation ADC), but for flash ADCs there is no real need for this, because the
comparators are the sampling devices.A flash converter requires a huge number of comparators compared to
other ADCs, especially as the precision increases. A flash converter requires comparators for an n-bit
conversion. The size, power consumption and cost of all those comparators makes flash converters generally
impractical for precisions much greater than 8 bits (255 comparators). In place of these comparators, most
other ADCs substitute more complex logic and/or analog circuitry that can be scaled more easily for
increased precision.
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 PROCEDURE:

1. Connect the circuit as shown in circuit diagram.

2. For various inputs, measure the outputs using multimeter.

Observations:
Analog Input conditions Comparator Outputs Digital Outputs
0≤Vin≤V/4 C1 C2 C3 B1 B0
V/4≤Vin≤2V/4
2V/4≤Vin≤3V/4
3V/4≤Vin≤V

RESULT:

The operation of flash type ADC is verified and studied.

VIVA QUESTIONS:
1. How many comparisons will be performed in an 8 bit successive approximation type ADC?

2. The basic step of 9 bit DAC is 10.3mV. If 000000000 represents 0V. What output is produced if the input
is 101101111?

3. State the applications of DAC and ADC .

4. For R-2R ladder 4 bit type DAC find the output voltage if digital input is 1111. Assume VR = 10V, R =
Rf = 10K.

5. Which is the fastest type of ADC? Why?

15. Zero Crossing Detector

AIM: To study the characteristics of Zero crossing Detector using IC 741

Apparatus:
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 1. Cathode Ray Oscilloscope

2.Function Generator

3.Bread board

4.Resistors: 1k(2)

5.Op-Amp LM741

CIRCUIT DIAGRAM:

THEORY:

 Zero crossing detectors is a sine wave to square wave converter.

 Zero crossing detector circuit is a comparator with zero reference voltage.
 When the input signal voltage passes through zero in the negative and the positive directions, the output
waveform switches between positive and negative saturation levels respectively.

Procedure:
1. Construct the circuit as shown below in figure
2. Set the Function Generator in sinusoidal mode at 1 kHz and adjust the amplitude to 6 V peak to peak .
3. Observe simultaneously the input and output waveform using oscilloscope. Repeat the
above steps by interchanging the reference voltage and input signal.

waveforms:

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 RESULT:
Thus, the use of op-amp as Zero crossing detector was studied.

VIVA QUESTIONS:

1. What is a zero crossing detector?

2. Explain the applications of zero crossing detector

3.Define comparator.

4.What are different types of comparator.

16.INVERTING AMPLIFIER
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AIM:
To design an Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS: 1. Cathode Ray Oscilloscope

2.Function Generator

3.Bread board

4.Resistors: 10k(2),1K

5.Op-Amp LM741

CIRCUIT DIAGRAM:

R1=1kΩ,Rf=10kΩ,RL=1kΩ

THEORY:

The input signal Vi is applied to the inverting input terminal through R1 and the non- inverting input
terminal of the op-amp is grounded. The output voltage Vo is fed back to the inverting input terminal
through the Rf - R1 network, where Rf is the feedback resistor. The output voltage is given as,
Vo = - ACL Vi

Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal.

PROCEDURE:

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 1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input
voltage is applied to the inverting input terminal of the Op- Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.

OBSERVATIONS:

Output
S.No Input
Practical Theoretical
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )

MODEL GRAPH:

RESULT:

The design of the inverting amplifier is done and the input and output waveforms were
drawn.
VIVA QUESTIONS:

1. The op-amp in the Inverting circuit is in _________

2. In an Inverting Amplifier circuit, the output voltage vo is expressed as a function of ____________
3. If VCC = 12V and vs=1mV, then Rf/Rs is _____________
4. The input applied to an Inverting amplifier is ______________

17. NON - INVERTING AMPLIFIER

AIM: To design an Non Inverting Amplifier for the given specifications using Op-Amp IC 741.
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APPARATUS: 1. Cathode Ray Oscilloscope

2.Function Generator

3.Bread board

4.Resistors: 10k(2),1K

5.Op-Amp LM741

CIRCUIT DIAGRAM

R1=1kΩ,Rf=10kΩ,RL=1kΩ

THEORY:
The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies
the signal without inverting the input signal. It is also called negative feedback system since the output
is feedback to the inverting input terminals. The differential voltage Vd at the inverting input terminal of
the op-amp is zero ideally and the output voltage is given as,
Vo = ACL Vi

Here the output voltage is in phase with the input signal.

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input
voltage is applied to the non - inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms are
plotted in a graph sheet.
OBSERVATIONS:

Output
S.No Input
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 Practical Theoretical
Amplitude
1.
( No. of div x Volts per div )
Time period
2.
( No. of div x Time per div )

MODEL GRAPH:

RESULT: The design of the non inverting amplifier is done and the input and output
waveforms were drawn.

VIVA QUESTIONS:

1. The circuits of an inverting and Non-Inverting amplifying comprises of __________ and _______
number of resistors.
2. The condition for a Non-inverting amplifying circuit to operate in linear region operation
3. If Rs= 3Ω, Rf= 6Ω then the relation between vo and vg in case of a Non-Inverting amplifying circuit.

18. VOLTAGE FOLLOWER

Aim: To design and setup a voltage follower circuit with OPAMP IC 741C and observe the
waveforms.

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 APPARATUS: 1. Cathode Ray Oscilloscope-1no

2.Function Generator-1no

3.Bread board-1no

4.Op-Amp LM741-1no

Circuit Diagram:

THEORY:

A voltage follower (also called a unity-gain amplifier or buffer amplifier or isolation amplifier) is an
op-amp circuit which has a voltage gain of 1. This means that the op amp does not provide any amplification
to the signal. It is called a voltage follower because the output voltage follows the input voltage; means the
output voltage is same as the input voltage. Though the gain is unity, this circuit offers high input impedance
and low output impedance and hence it is used as buffer , which is used to isolate a low impedance load
from a voltage source to eliminate any loading that might occur.

Procedure:

1. Check the components.

2. Setup the circuit on the breadboard and check the connections.
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 3. Switch on the power supply.
4. Give 2Vpp/ 1 KHz sine wave as input.
5. Observe input and output on the two channels of the oscilloscope simultaneously.
6. Note down and draw the input and output waveforms on the graph.
7. Verify that the input and output waveforms are same in magnitude and phase.

CALCULATIONS:
The voltage follower is a non-inverting amplifier with unity gain.
A = 1+ R f / Ri = 1
Or R f / Ri = 0
Therefore Rf= 0

Voltage gain = Vo / Vi = ?;

Result: Voltage follower circuit using OPAMP 741 is designed and waveforms observed.
VIVA QUESTIONS:

1.In a voltage follower, what happens when you switch the inverting and non-inverting inputs of the op-
amp?
2.Define voltage follower?

3.What are the ideal characteristics of op-amp

4.What are ac of o characteristics op-amp?

19.PRECISION RECTIFIER
AIM: To construct precision half wave rectifier using Op Amp.

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 APPARATUS :

1.Resistor-1k

2.IC 741

3.Function Generator

4.DiodeIN4007

5.Connecting wires

6.CRO

7.Bread board

Circuit Diagram:

THEORY:

The major limitation of ordinary diodes is that it cannot rectify voltage below 0.6v,the cutin
voltage of the diode.The precision rectifier, which is also known as a super diode, is a configuration
obtained with an operational amplifier in order to have a circuit behaving like an ideal diode and
rectifier.It can be useful for high-precision signal processing. A half-wave rectifier is an electronic
circuit. The rectifier circuit takes alternating current (AC) from the wall outlet and converts it into a
positive direct current (DC) output. The particular electronic device that accomplishes this task is a
semiconductor called a diode. The diode like all semiconductors is a material which has a resistance in
between that of a conductor or wire and an insulator like that of a plastic.

PROCEDURE:

1. Conn ect the circuit as shown in the figures for Half wave rectifier.

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 2. Set the input signal voltage using Function generator.

3. Observe the output waveform in CRO and measure the output parameters.

TABULATION:

INPUT OUTPUT FREQUENCY

Amplitude Time Amplitude Time

ON OFF

MODEL GRAPH:

Input Waveform: Output waveform:

RESULT:

The half wave rectifier are constructed and the output waveforms are drawn.

VIVA QUESTIONS:
1.How does a precision rectifier work?
2.What is the design and development of a precision rectifier?
3.What is a precision rectifier?
4.What are the applications of rectifiers?
5.What is the disadvantage of uncontrolled rectifiers?

20. Logarithmic Amplifier

AIM: To understand the operation of logarithmic amplifiers.

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APPARATUS:
1.Resistors: 100K [2]

2.Transistor: BC548 [1]

3. Breadboard

4. Multimeter

CIRCUIT DIAGRAM:

THEORY:
Log amplifiers are widely used for analog signal compression applications. When a diode used in
the feedback loop of an operational amplifier is forward biased by a constant current of magnitude
Vi / R then it develops VD = VT ln Vi/ R1 across the diode. Note that the input voltage and diode
voltage are related in a logarithmic fashion. If we take the diode voltage as an output voltage then
the input and output will be related in a logarithmic fashion.

The base emitter junction of a bipolar junction transistor can be used as diode when collector
and base are shorted. So a transistor can also be used in the feedback loop of an op-amp.

PROCEDURE:
1. Set the supply voltage at +12V.

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 2. Set the input voltage to 1V.

3. See the voltage across the diode. Note the negative sign.

4. Increase the input voltage in the step of 1V up to 20V.

5. Plot the characteristics of input voltage and output voltage.

6. Reverse the polarity of the diode and see the effect for positive input voltage.

Observation Table:

Input Voltage Output Voltage

RESULT: The function of Log amplifier is verified and waveforms drawn.

VIVA QUESTIONS:
1.Why should we use diode in log amplifier?
2.Why do we not use an amplifier in place of a repeater?
3.What is the importance of using a log amplifier?

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