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Octal Bus Buffer With 3 State Outputs (Non Inverted) : PD CC o

This document summarizes the specifications and features of the 74ACT244 octal bus buffer chip. It operates at high speeds of up to 4.5ns with low power dissipation of 8uA max. It has 3-state outputs compatible with TTL levels and can drive 50ohm transmission lines. The chip provides symmetrical 24mA output currents and balanced propagation delays across its 8 buffer channels.

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0% found this document useful (0 votes)
141 views9 pages

Octal Bus Buffer With 3 State Outputs (Non Inverted) : PD CC o

This document summarizes the specifications and features of the 74ACT244 octal bus buffer chip. It operates at high speeds of up to 4.5ns with low power dissipation of 8uA max. It has 3-state outputs compatible with TTL levels and can drive 50ohm transmission lines. The chip provides symmetrical 24mA output currents and balanced propagation delays across its 8 buffer channels.

Uploaded by

criman45
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© © All Rights Reserved
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You are on page 1/ 9

 74ACT244

OCTAL BUS BUFFER


WITH 3 STATE OUTPUTS (NON INVERTED)
■ HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
■ COMPATIBLE WITH TTL OUTPUTS M
VIH = 2V (MIN), VIL = 0.8V (MAX) (Micro Package)
■ 50Ω TRANSMISSION LINE DRIVING B
CAPABILITY (Plastic Package)
■ SYMMETRICAL OUTPUT IMPEDANCE: ORDER CODES :
|IOH| = IOL = 24 mA (MIN) 74ACT244B T
■ BALANCED PROPAGATION DELAYS: 74ACT244M (TSSOP Package)
tPLH ≅ tPHL 74ACT244T
■ OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V G control output governs four BUS BUFFERs.
■ PIN AND FUNCTION COMPATIBLE WITH This device is desibned to be used with 3 state
74 SERIES 244 memory address drivers, etc.
■ IMPROVED LATCH-UP IMMUNITY The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
DESCRIPTION CMOS output voltage levels.
The ACT244 is an advanced CMOS OCTAL BUS All inputs and outputs are equipped with
BUFFER (3-STATE) fabricated with sub-micron protection circuits against static discharge, giving
silicon gate and double-layer metal wiring C2MOS them 2KV ESD immunity and transient excess
technology. It is ideal for low power applications voltage.
mantaining high speed operation similar to
equivalent Bipolar Schottky TTL.

PIN CONNECTION AND IEC LOGIC SYMBOLS

February 1999 1/9


74ACT244

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION


PIN No SYMBOL NAME AND FUNCT ION
1 1G Output Enable Input
2, 4,6, 8 1A1 to 1A4 Data Inputs
9, 7,5, 3 2Y1 to 2Y4 Data Outputs
11, 13, 15, 17 2A1 to 2A4 Data Inputs
18, 16, 14, 12 1Y1 to 1Y4 Data Outputs
19 2G Output Enabel Input
10 GND Ground (0V)
20 VCC Positive Supply Voltage

TRUTH TABLE
INPUT OUTPUT
G An Yn
L L L
L H H
H X Z
X:”H” or ”L”
Z: High impedance

ABSOLUTE MAXIMUM RATINGS


Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 50 mA
ICC orIGND DC VCC or Ground Current ± 400 mA
o
Tstg Storage Temperature -65 to +150 C
o
TL Lead Temperature (10 sec) 300 C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

RECOMMENDED OPERATING CONDITIONS


Symbol Parameter Value Unit
VCC Supply Voltage 4.5 to 5.5 V
VI Input Voltage 0 to VCC V
VO Output Voltage 0 to VCC V
o
Top Operating Temperature: -40 to +85 C
dt/dv Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) 8 ns/V
1) VIN from 0.8 V to 2.0 V

2/9
74ACT244

DC SPECIFICATIONS
Symb ol Parameter Test Co nditions Valu e Un it
V CC T A = 25 oC -40 to 85 o C
(V) Min. T yp. Max. Min. Max.
VIH High Level Input Voltage 4.5 VO = 0.1 V or 2.0 1.5 2.0
V
5.5 VCC - 0.1 V 2.0 1.5 2.0
VIL Low Level Input Voltage 4.5 VO = 0.1 V or 1.5 0.8 0.8
V
5.5 VCC - 0.1 V 1.5 0.8 0.8
VOH High Level Output 4.5 IO=-50 µA 4.4 4.49 4.4
VI(*) = V
Voltage 5.5 IO=-50 µA 5.4 5.49 5.4
VIH or
4.5 VIL IO=-24 mA 3.86 3.76
5.5 IO=-24 mA 4.86 4.76
VOL Low Level Output 4.5 (*) IO=50 µA 0.001 0.1 0.1
VI = V
Voltage 5.5 IO=50 mA 0.001 0.1 0.1
VIH or
4.5 VIL IO=24 mA 0.36 0.44
5.5 IO=24 mA 0.36 0.44
II Input Leakage Current 5.5 VI = VCC orGND ±0.1 ±1 µA
IOZ 3 State Output Leakage 5.5 VI = VIH orVIL ±0.5 ±5 µA
Current VO = VCC orGND
ICCT Max ICC /Input 5.5 VI = VCC -2.1V 0.6 1.5 mA
ICC Quiescent Supply 5.5 VI = VCC orGND 8 80 µA
Current
IOLD Dynamic Output Current 5.5 VOLD = 1.65 V max 75 mA
IOHD (note 1, 2) VOHD = 3.85 V min -75 mA
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω.
(*) All outputs loaded.

3/9
74ACT244

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)


Symb ol Parameter T est Con ditio n Valu e Un it
V CC T A = 25 oC -40 to 85 o C
(V) Min. T yp. Max. Min. Max.
(*)
tPLH Propagation Delay Time 5.0 1.5 4.5 9.0 1.5 10.0 ns
tPHL
tPZL Output Enable Time 5.0(*) 1.5 5.5 9.0 1.5 10.0 ns
tPZH
tPLZ Output Disable Time 5.0(*) 1.5 6.5 10.0 1.5 11.0 ns
tPHZ
(*) Voltage range is 5V ± 0.5V

CAPACITIVE CHARACTERISTICS
Symb ol Parameter Test Co nditions Valu e Un it
o o
V CC T A = 25 C -40 to 85 C
(V) Min. T yp. Max. Min. Max.
CIN Input Capacitance 5.0 4 pF
Ci/o I/O Capacitance 5.0 8 pF
CPD Power Dissipation 5.0 24 pF
Capacitance (note 1)
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit)

TEST CIRCUIT

T EST SW IT CH
tPLH , tPHL Open
tPZL , tPLZ 2VCC
tPZH , tPHZ Open
CL = 50 pF or equivalent (includes jigand probe capacitance)
RL = R1 = 500Ω orequivalent
RT = ZOUT of pulse generator (typically 50Ω)

4/9
74ACT244

WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)

WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)

5/9
74ACT244

Plastic DIP-20 (0.25) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130

Z 1.34 0.053

P001J

6/9
74ACT244

SO-20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.10 0.20 0.004 0.007
a2 2.45 0.096
b 0.35 0.49 0.013 0.019
b1 0.23 0.32 0.009 0.012
C 0.50 0.020
c1 45 (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.299
L 0.50 1.27 0.19 0.050
M 0.75 0.029
S 8 (max.)

P013L

7/9
74ACT244

TSSOP20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 1.1 0.433

A1 0.05 0.10 0.15 0.002 0.004 0.006

A2 0.85 0.9 0.95 0.335 0.354 0.374

b 0.19 0.30 0.0075 0.0118

c 0.09 0.2 0.0035 0.0079

D 6.4 6.5 6.6 0.252 0.256 0.260

E 6.25 6.4 6.5 0.246 0.252 0.256

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K 0o 4o 8o 0o 4o 8o

L 0.50 0.60 0.70 0.020 0.024 0.028

A A2
K L
A1 b e
c E

E1

PIN 1 IDENTIFICATION
1

8/9
74ACT244

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics

 1999 STMicroelectronics – Printed in Italy – All Rights Reserved


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