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ON "Vlsi - Design": Supervisor: Submitted By: DR Montasar Sharif Mohammed Ayoub Othman

This document reports on VLSI design. It discusses the history of VHDL, including its development under the VHSIC program in 1981 and standardization by IEEE in 1987. It describes VHDL's capabilities like supporting hierarchy, flexible design methodologies, synchronous/asynchronous timing. It discusses the main design units in VHDL - entity declaration, architecture body, configuration declaration and package. It provides examples of different styles to model architecture bodies - structural using components, dataflow using concurrent assignments, and behavioral using processes.

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Mahamad Ayoub
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57 views13 pages

ON "Vlsi - Design": Supervisor: Submitted By: DR Montasar Sharif Mohammed Ayoub Othman

This document reports on VLSI design. It discusses the history of VHDL, including its development under the VHSIC program in 1981 and standardization by IEEE in 1987. It describes VHDL's capabilities like supporting hierarchy, flexible design methodologies, synchronous/asynchronous timing. It discusses the main design units in VHDL - entity declaration, architecture body, configuration declaration and package. It provides examples of different styles to model architecture bodies - structural using components, dataflow using concurrent assignments, and behavioral using processes.

Uploaded by

Mahamad Ayoub
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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A

REPORT
ON
“VLSI –DESIGN”

Supervisor : Submitted By:


Dr Montasar Sharif Mohammed Ayoub
Othman

Department of Computer Technical Engineering


Electronic Branch
HISTORY

 First generated in 1981 under the VHSIC program

 IBM, TEXAS instruments and intermeterics are first awarded by the


DOD(department of defence) to develop a version of language in 1983

 Version 7.2 of VHDL was developed and released to the public in 1985

 the language was transferred to the IEEE for standardization in 1986

 the language was standardized by the IEEE in December 1987; this version of
the language is now known as the IEEE Std 1076-1987
CAPABILITIES
 Language supports hierarchy

 VHDL language supports flexible design methodologies

 It can also support various hardware technologies

 It supports both synchronous and asynchronous timing models

 Publicly available, human readable, machine readable

 It is an IEEE and ANSI standard

 Structural, dataflow, and behavioural

 Generics and attributes are also useful in describing vlsi designs


DESIGN UNITS
 Entity declaration

 Architecture body

 Configuration declaration

 Package declaration

 Package body
ENTITY

 A hardware abstraction of this digital system is called an entity in this text

 The entity' declaration specifies the name of the entity being modelled and
lists the set of interface ports

 An entity is modelled using an entity declaration and at least one architecture


body.

 The entity declaration describes the external view of the entity, for example,
the input and output signal names.
 ENTITY
 HARDWARE DECLARATION
ABSTRACTIO
N OF DIGITAL
SYSTEM
MODEL
ENTITY

FIG: AN ENTITY AND ITS MODEL ARCHITECURAL BODIES


Entity declaration for the half adder circuit is shown below:

entity HALF_ADDER is
port (A, B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;
-- This is a comment line.
CONFIGURATION DECLARATION
 Configuration for an entity

 Binding

A CONFIGURATION FOR ENTITY 1


ARCHITECTURE BODY
 As a set of interconnected components (to represent structure),

 As a set of concurrent assignment statements (to represent dataflow),

 As a set of sequential assignment statements (to represent behaviour),

 Any combination of the above three


Structural Style of Modelling

• In the structural style of modeling, an entity is described as a set of


interconnected components.

Model for half adder entity is shown below:


architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X, Y: in BIT; Z: out BIT);
end component; a
component AND2
port (L, M: in BIT; N: out BIT);
end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
A structural representation for the DECODER2x4
entity

architecture DEC_STR of DECODER2x4 is


component INV
port (A: in BIT; Z: out BIT);
end component;
component NAND3
port (A, B, C: in BIT; Z: out BIT);
end component;
signal ABAR, BBAR: BIT;
begin
I0: INV port map (A, ABAR);
I1: INV port map (B, BBAR);
N0: NAND3 port map (ABAR, BBAR, ENABLE, Z(0));
N1: NAND3 port map (ABAR, B, ENABLE, Z(1));
N2: NAND3 port map (A, BBAR, ENABLE, Z(2));
N3: NAND3 port map (A, B, ENABLE, Z(3));
end DEC_STR;
Dataflow Style of Modelling

 In this modeling style, the flow of data through the entity is expressed
primarily using concurrent signal assignment statements

 The structure of the entity is not explicitly specified in this modeling style, but
it can be implicitly deduced

Architecture body for the HALF..ADDER entity that uses this style

architecture HA_CONCURRENTof HALF_ADDER is


begin
SUM <= A xor B after 8 ns;
CARRY <= A and B after 4 ns;
end HA_CONCURRENT;
Behavioural Style of Modeling
 A set of statements that are executed sequentially in the specified order

 A process statement is a concurrent statement that can appear within an


architecture body

 Behavioural model for the DECODER2x4 entity

 A process statement, too, has a declarative part (between the keywords process
and begin), and a statement part (between the keywords begin and end
process)

architecture DEC_SEQUENTIAL of DECODER2x4 is begin process (A, B,


ENABLE)
variable ABAR, BBAR: BIT; begin
ABAR := not A; - statement 1 BBAR := not B; - statement 2 if (ENABLE = '1')
then -statements Z(3) <= not (A and B): - statement 4 Z(0) <= not (ABAR and
BBAR); ~ statement 5 Z(2) <= not (A and BBAR); - statement 6 Z(1 ) <= not
(ABAR and B); - statement 7 else

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