MX66UM2G45G

MX66UM2G45G
1.8V 2G-BIT [x 1/x 8]
CMOS octaflash Memory

Key Features
• Protocol Support - Single I/O and Octa I/O
• Support DTR (Double Transfer Rate) Mode
• Support clock frequency up to 133MHz

Macronix Proprietary Rev. 1.0, June 04, 2019

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Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 5
Table 1. Operating Frequency Comparison.................................................................................................5
3. PIN CONFIGURATIONS .......................................................................................................................................... 6
Table 2. PIN DESCRIPTION........................................................................................................................6
4. BLOCK DIAGRAM.................................................................................................................................................... 7
5. MEMORY ORGANIZATION...................................................................................................................................... 8
6. DATA PROTECTION................................................................................................................................................. 9
6-1. Block lock protection................................................................................................................................. 10
Table 3. Protected Area Sizes....................................................................................................................10
6-2. Additional 8K-bit secured OTP ..................................................................................................................11
Table 4. Secured OTP Definition................................................................................................................ 11
7. DEVICE OPERATION............................................................................................................................................. 12
8. COMMAND SET..................................................................................................................................................... 14
8-1. SPI Command Set.................................................................................................................................... 14
8-2. OPI Command Set.................................................................................................................................... 17
9. REGISTER DESCRIPTION..................................................................................................................................... 19
9-1.
Status Register......................................................................................................................................... 19
9-2.
Configuration Register.............................................................................................................................. 20
9-3.
Configuration Register 2........................................................................................................................... 21
9-4.
Security Register...................................................................................................................................... 24
Table 5. Security Register Definition..........................................................................................................24
10. COMMAND DESCRIPTION.................................................................................................................................. 25
10-1. Write Enable (WREN)............................................................................................................................... 25
10-2. Write Disable (WRDI)................................................................................................................................ 26
10-3. Read Identification (RDID)........................................................................................................................ 27
Table 6. ID Definitions ...............................................................................................................................27
10-4. Read Status Register (RDSR).................................................................................................................. 28
10-5. Read Configuration Register (RDCR)....................................................................................................... 31
10-6. Write Status Register (WRSR) / Write Configuration Register (WRCR)................................................... 32
10-7. Read Configuration Register 2 (RDCR2).................................................................................................. 35
10-8. Write Configuration Register 2 (WRCR2).................................................................................................. 36
10-9. Read Security Register (RDSCUR).......................................................................................................... 37
10-10. Write Security Register (WRSCUR).......................................................................................................... 38
10-11. Read Data Bytes (READ/READ3B/READ4B).......................................................................................... 39
10-12. Read Data Bytes at Higher Speed (FAST_READ/FAST_READ3B/FAST_READ4B).............................. 40
10-13. OCTA Read Mode (8READ)..................................................................................................................... 41
10-14. OCTA DTR Read Mode (8DTRD)............................................................................................................. 42
10-15. Preamble Bit............................................................................................................................................. 43
10-16. Burst Read................................................................................................................................................ 44
10-17. Fast Boot.................................................................................................................................................. 45
10-18. Sector Erase (SE/SE3B/SE4B)................................................................................................................ 50

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10-19. Block Erase (BE/BE3B/BE4B).................................................................................................................. 51

10-20. Chip Erase (CE)........................................................................................................................................ 52
10-21. Page Program (PP/PP3B/PP4B).............................................................................................................. 53
10-22. Deep Power-down (DP)............................................................................................................................ 55
10-23. Release from Deep Power-down (RDP)................................................................................................... 56
10-24. Enter Secured OTP (ENSO)..................................................................................................................... 57
10-25. Exit Secured OTP (EXSO)........................................................................................................................ 57
10-26. Write Protection Selection (WPSEL)......................................................................................................... 58
10-27. Advanced Sector Protection..................................................................................................................... 59
10-28. Program Suspend and Erase Suspend.................................................................................................... 74
Table 7. Acceptable Commands During Suspend.....................................................................................75
10-29. Program Resume and Erase Resume...................................................................................................... 76
10-30. No Operation (NOP)................................................................................................................................. 77
10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 77
11. Serial Flash Discoverable Parameter (SFDP)................................................................................................... 79
11-1. Read SFDP Mode (RDSFDP)................................................................................................................... 79
Table 8. Signature and Parameter Identification Data Values....................................................................80
12. Data Integrity check............................................................................................................................................ 81
12-1. ECC (Error Checking and Correcting)...................................................................................................... 81
Table 9. 16-Byte Chunks within a Page.....................................................................................................81
12-2. ECS# (Error corrected Signal) Pin............................................................................................................ 82
12-3. Parity Check (CRC1)................................................................................................................................ 83
13. RESET.................................................................................................................................................................. 86
Table 10. Reset Timing-(Standby)..............................................................................................................86
Table 11. Reset Timing-(Other Operation).................................................................................................86
14. POWER-ON STATE.............................................................................................................................................. 87
15. ELECTRICAL SPECIFICATIONS......................................................................................................................... 88
Table 12. ABSOLUTE MAXIMUM RATINGS.............................................................................................88
Table 13. CAPACITANCE TA = 25°C, f = 1.0 MHz.....................................................................................88
Table 14. DC CHARACTERISTICS...........................................................................................................90
Table 15. AC CHARACTERISTICS............................................................................................................91
16. OPERATING CONDITIONS.................................................................................................................................. 93
Table 16. Power-Up/Down Voltage and Timing .........................................................................................95
16-1. INITIAL DELIVERY STATE....................................................................................................................... 95
17. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 96
18. DATA RETENTION............................................................................................................................................... 96
19. LATCH-UP CHARACTERISTICS......................................................................................................................... 96
20. ORDERING INFORMATION................................................................................................................................. 97
21. PART NAME DESCRIPTION................................................................................................................................ 98
22. PACKAGE INFORMATION................................................................................................................................... 99
23. REVISION HISTORY .......................................................................................................................................... 100

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1.8V 2G-BIT [x 1/x 8] CMOS octaflash Memory

1. FEATURES

GENERAL HARDWARE FEATURES

• Supports Serial Peripheral Interface -- Mode 0 • SCLK Input
• Single Power Supply Operation - Serial clock input
- 1.65 to 2.0 volt for read, erase, and program • SIO0 - SIO7
operations - Serial Data Input or Serial Data Output
• Protocol Support • DQS
- Single I/O and Octa I/O - Data strobe signal
- Support DTR (Double Transfer Rate) Mode • RESET#
• Fast frequency support - Hardware Reset pin
- Support clock frequency up to • PACKAGE
- Single I/O mode: 133MHz -24-Ball BGA (5x5 ball array)
- Octa I/O mode: 133MHz -All devices are RoHS Compliant and Halogen
- Configurable dummy cycle number for OPI read Free.
operation
• Octa Peripheral Interface (OPI) available
• Equal Sectors with 4K byte each, or Equal Blocks
with 64K byte each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Octa Input/Output page program to enhance
program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
• JEDEC xSPI specification compliant

SOFTWARE FEATURES
• Input Data Format
- SPI: 1-byte command code
- OPI: 2-byte command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size of
the area to be protected against program and erase
instructions
- Advanced Sector Protection (Solid and Password
Protect)
• Additional 8K bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable
• Command Reset
• Program/Erase Suspend and Resume operation
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device
ID
• Support Serial Flash Discoverable Parameters
(SFDP) mode

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2. GENERAL DESCRIPTION

MX66UM2G45G is 2Gb bits Octal interface Serial NOR Flash memory, which is configured as 268,435,456 x 8
internally. MX66UM2G45G feature a serial peripheral interface and software protocol allowing operation on a simple
3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and
a serial data output (SO). Serial access to the device is enabled by CS# input.

The MX66UM2G45G octaflash provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Erase command is executed on sector (4K-byte), or block (64K-byte), or whole chip
basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX66UM2G45G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.

Table 1. Operating Frequency Comparison

Numbers of Dummy Cycle

6 8 10 12 14 16 18 20
Octa I/O STR (MHz) 66 84 104 104 133 133 133 133*
Octa I/O DTR (MHz) 66 84 104 104 133 133 133 133*

Notes: * means default status

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3. PIN CONFIGURATIONS

24-BALL BGA (5x5 ball array) Table 2. PIN DESCRIPTION

1 2 3 4 5 SYMBOL DESCRIPTION
CS# Chip Select
SCLK Clock Input
RESET# Hardware Reset Pin Active lowNote 1
ECS# ECC Correction Signal (open drain)
A
DQS Data Strobe Signal
NC NC RESET# ECS#
Serial Data Input (for 1 x I/O)/ Serial
SI/SIO0 Data Input & Output (for 8 x I/O read
B mode)
DNU SCLK GND VCC DNU
Serial Data Output (for 1 x I/O)/ Serial
SO/SIO1 Data Input & Output (for 8 x I/O read
C mode)
VSSQ CS# DQS SIO2 NC Serial Data Input & Output (for 8 x I/O
SIO2-SIO7
read mode)
D VCC 1.8V Power Supply
VCCQ SIO1 SIO0 SIO3 SIO4 VCCQ 1.8V Buffer Power Supply
GND Ground
E VSSQ IO Ground Supply
SIO7 SIO6 SIO5 VCCQ VSSQ NC No Connection
DNU Do Not Use
Notes:
1. The pin of RESET# will remain internal pull up
function while this pin is not physically connected
in system configuration.
However, the internal pull up function will be disabled
if the system has physical connection to RESET#
pin.

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4. BLOCK DIAGRAM

X-Decoder
Address Memory Array
Generator
SI/SIO0
SO/SIO1
SIO2
Y-Decoder
SIO3
SIO4 Data
SIO5 Register
SIO6
SRAM Sense
SIO7 Buffer Amplifier
RESET#
CS#
DQS Mode State HV
ECS# Logic Machine Generator

SCLK Clock Generator

Output
Buffer

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5. MEMORY ORGANIZATION

Block(64K-byte) Sector Address Range

65535 FFFF000h FFFFFFFh

…
4095 65528 FFF8000h FFF8FFFh
65527 FFF7000h FFF7FFFh

…
65520 FFF0000h FFF0FFFh
65519 FFEF000h FFEFFFFh

…
65512 FFE8000h FFE8FFFh
4094
65511 FFE7000h FFE7FFFh
…

…
65504 FFE0000h FFE0FFFh
65503 FFDF000h FFDFFFFh
…

…
65496 FFD8000h FFD8FFFh
4093
65495 FFD7000h FFD7FFFh
…

…
65488 FFD0000h FFD0FFFh
∼
47 002F000h 002FFFFh
…

2 40 0028000h 0028FFFh
39 027000h 0027FFFh
…

32 0020000h 0020FFFh
31 001F000h 001FFFFh
…

24 0018000h 0018FFFh
1
23 0017000h 0017FFFh
…

16 0010000h 0010FFFh
15 000F000h 000FFFFh
…

8 0008000h 0008FFFh
0 7 0007000h 0007FFFh
…

0 0000000h 0000FFFh

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6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.

• Valid command length (SPI Mode) or command/command# combination (OPI Mode) will be check.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP), and softreset command.

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6-1. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be
protected as read only. The protected area definition is shown as Table 3 Protected Area Sizes, the protected
areas are more flexible which may protect various area by setting value of BP0-BP3 bits.

Table 3. Protected Area Sizes

Protected Area Sizes (T/B bit = 0)
Status bit Protect Level
BP3 BP2 BP1 BP0 2Gb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 4095th)
0 0 1 0 2 (2 blocks, protected block 4094th-4095th)
0 0 1 1 3 (4 blocks, protected block 4092nd-4095th)
0 1 0 0 4 (8 blocks, protected block 4088th-4095th)
0 1 0 1 5 (16 blocks, protected block 4080th-4095th)
0 1 1 0 6 (32 blocks, protected block 4064th-4095th)
0 1 1 1 7 (64 blocks, protected block 4032nd-4095th)
1 0 0 0 8 (128 blocks, protected block 3968th-4095th)
1 0 0 1 9 (256 blocks, protected block 3840th-4095th)
1 0 1 0 10 (512 blocks, protected block 3584th-4095th)
1 0 1 1 11 (1024 blocks, protected block 3072nd-4095th)
1 1 0 0 12 (2048 blocks, protected block 2048th-4095th)
1 1 0 1 13 (4096 blocks, protected all)
1 1 1 0 14 (4096 blocks, protected all)
1 1 1 1 15 (4096 blocks, protected all)

Protected Area Sizes (T/B bit = 1)

Status bit Protect Level
BP3 BP2 BP1 BP0 2Gb
0 0 0 0 0 (none)
0 0 0 1 1 (1 block, protected block 0th)
0 0 1 0 2 (2 blocks, protected block 0th-1st)
0 0 1 1 3 (4 blocks, protected block 0th-3rd)
0 1 0 0 4 (8 blocks, protected block 0th-7th)
0 1 0 1 5 (16 blocks, protected block 0th-15th)
0 1 1 0 6 (32 blocks, protected block 0th-31st)
0 1 1 1 7 (64 blocks, protected block 0th-63rd)
1 0 0 0 8 (128 blocks, protected block 0th-127th)
1 0 0 1 9 (256 blocks, protected block 0th-255th)
1 0 1 0 10 (512 blocks, protected block 0th-511th)
1 0 1 1 11 (1024 blocks, protected block 0th-1023rd)
1 1 0 0 12 (2048 blocks, protected block 0th-2047th)
1 1 0 1 13 (4096 blocks, protected all)
1 1 1 0 14 (4096 blocks, protected all)
1 1 1 1 15 (4096 blocks, protected all)

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6-2. Additional 8K-bit secured OTP

The secured OTP for unique identifier: to provide 8K-bit one-time program area for setting device unique serial
number. Which may be set by factory or system customer.

- Security register bit 0 indicates whether the chip is locked by factory or not.

- To program the 8K-bit secured OTP by entering secured OTP mode (with Enter Security OTP command), and
going through normal program procedure, and then exiting secured OTP mode by writing Exit Security OTP
command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to "Table 5. Security Register Definition" for
security register bit definition and "Table 4. Secured OTP Definition" for address range definition.

- Note: Once lock-down by factory or customer, the corresponding range cannot be changed any more. While in
secured OTP mode, array access is not allowed.

Table 4. Secured OTP Definition

Address range Size Lock-down

xxx000~xxx1FF 4096-bit Determined by Customer
xxx200~xxx3FF 4096-bit Determined by Factory

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7. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.

2. When incorrect command# sequence is inputted to this device, this device becomes standby mode and keeps
the standby mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.

3. When correct command# sequence is inputted to this device, this device becomes active mode and keeps the
active mode until next CS# rising edge.

4. When device under STR mode, input data is latched on the rising edge of Serial Clock (SCLK) and data shifts
out on the falling edge of SCLK. When device under DTR mode, input data is latched on the both rising and
falling edge of Serial Clock (SCLK) and data shifts out on both rising and falling edge of SCLK.

5. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Input Timing (STR mode)

tSHSL

CS#

tCHSL tSLCH tCHSH tSHCH

SCLK

tDVCH tCHCL

tCHDX tCLCH

SI MSB LSB

High-Z
SO

Figure 2. Input Timing (DTR mode)

tSHSL

CS#

tCHSL tSLCH tCLSH tSHCH

SCLK

tDVCH tCHCL
tCLDX
tCLCH
tCHDX tDVCL

SIO MSB LSB

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Figure 3. Output Timing (STR mode)

CS#
tCH

SCLK
tCLQV tCLQV tCL tSHQZ

tCLQX tCLQX

SIO LSB

Figure 4. Output Timing (DTR mode)

SCLK
tCHQV tCLQV

tQSV
DQS
tDQSQ tDQSQ
tQH tQH

SIO[7:0]

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8. COMMAND SET
8-1. SPI Command Set
Address Byte
Command Total Dummy Data
Code ADD Byte 1 Byte 2 Byte 3 Byte 4 Cycle Byte
Byte
Array access
READ3B
03 (hex) 3 ADD1 ADD2 ADD3 0 1- ∞
(normal read)
FAST READ3B
0B (hex) 3 ADD1 ADD2 ADD3 8 1- ∞
(fast read data)
PP3B
02 (hex) 3 ADD1 ADD2 ADD3 0 1-256
(page program)
SE3B
20 (hex) 3 ADD1 ADD2 ADD3 0 0
(sector erase)
BE3B
D8 (hex) 3 ADD1 ADD2 ADD3 0 0
(block erase 64KB)
READ4B
13 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 1- ∞
(normal read)
FAST READ4B
0C (hex) 4 ADD1 ADD2 ADD3 ADD4 8 1- ∞
(fast read data)
PP4B
12 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 1-256
(page program)
SE4B
21 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 0
(sector erase 4KB)
BE4B
DC (hex) 4 ADD1 ADD2 ADD3 ADD4 0 0
(block erase 64KB)
CE 60 or C7
0 0 0
(chip erase) (hex)
Device operation
WREN
06 (hex) 0 0 0
(write enable)
WRDI
04 (hex) 0 0 0
(write disable)
WPSEL
68 (hex) 0 0 0
(Write Protect Selection)
PGM/ERS Suspend
B0 (hex) 0 0 0
(Suspends Program/ Erase)
PGM/ERS Resume
30 (hex) 0 0 0
(Resumes Program/ Erase)
DP
B9 (hex) 0 0 0
(Deep power down)
RDP
(Release from deep power AB (hex) 0 0 0
down)
NOP
00 (hex) 0 0 0
(No Operation)
RSTEN 66 (hex) 0 0 0
(Reset Enable) (Note2)
RST 99 (hex) 0 0 0
(Reset Memory) (Note2)
GBLK
7E (hex) 0 0 0
(gang block lock)
GBULK
98 (hex) 0 0 0
(gang block unlock)

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Address Byte
Command Total Dummy Data
Code ADD Byte 1 Byte 2 Byte 3 Byte 4 Cycle Byte
Byte
Register Access
RDID
9F (hex) 0 0 3
(read identification)
RDSFDP
5A (hex) 3 ADD1 ADD2 ADD3 8 0
(Read SFDP Table)
RDSR
05 (hex) 0 0 1
(read status register)
RDCR
15 (hex) 0 0 1
(read configuration register)
WRSR/WRCR
(write status/configuration 01 (hex) 0 0 1-2
register)
RDCR2
71 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 1
(read configuration register2)
WRCR2
72 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 1
(write configuration register2)
RDSCUR
2B (hex) 0 0 0
(read security register)
WRSCUR
2F (hex) 0 0 0
(write security register)
RDFBR
16 (hex) 0 0 1-4
(read fast boot register)
WRFBR
17 (hex) 0 0 4
(write fast boot register)
ESFBR
18 (hex) 0 0 0
(erase fast boot register)
SBL
C0 (hex) 0 0 1
(Set Burst Length)
ENSO
B1 (hex) 0 0 0
(enter secured OTP)
EXSO
C1 (hex) 0 0 0
(exit secured OTP)
WRLR
2C (hex) 0 0 1
(write Lock register)
RDLR
2D (hex) 0 0 1
(read Lock register)
WRSPB
E3 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 0
(SPB bit program)
ESSPB
E4 (hex) 0 0 0
(all SPB bit erase)
RDSPB
E2 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 1
(read SPB status)
WRDPB
E1 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 1
(write DPB register)
RDDPB
E0 (hex) 4 ADD1 ADD2 ADD3 ADD4 0 1
(read DPB register)

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Address Byte
Command Total Dummy Data
Code ADD Byte 1 Byte 2 Byte 3 Byte 4 Cycle Byte
Byte
RDPASS
27 (hex) 4 00h 00h 00h 00h 8 8
(read password register)
WRPASS
28 (hex) 4 00h 00h 00h 00h 0 8
(write password register)
PASSULK
29 (hex) 4 00h 00h 00h 00h 0 8
(password unlock)

Note 1: It is not recommended to adopt any other code/address not in the command definition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.

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8-2. OPI Command Set

Command Set Address Byte
8-8-8 8-8-8 Total Dummy Data
1'st 2'nd (STR) (DTR) Cycle Byte
ADD Byte 1 Byte 2 Byte 3 Byte 4
Byte Byte
Byte
Array access
8READ 6-20
EC (hex) 13 (hex) V 4 ADD1 ADD2 ADD3 ADD4 1- ∞
(8 I/O read ) (Note3)
8DTRD ADD4 6-20
EE (hex) 11 (hex) V 4 ADD1 ADD2 ADD3 1- ∞
(8 I/O DT Read) (Note5) (Note3)
PP4B ADD4
12 (hex) ED (hex) V V 4 ADD1 ADD2 ADD3 0 1-256
(Page Program) (Note5)
SE4B
21 (hex) DE (hex) V V 4 ADD1 ADD2 ADD3 ADD4 0 0
(Sector erase 4KB)
BE4B
DC (hex) 23 (hex) V V 4 ADD1 ADD2 ADD3 ADD4 0 0
(block erase 64KB)
CE 60 or C7 9F or
V V 0 0 0
(chip erase) (hex) 38 (hex)
Device operation
WREN
06 (hex) F9 (hex) V V 0 0 0
(write enable)
WRDI
04 (hex) FB (hex) V V 0 0 0
(write disable)
WPSEL
68 (hex) 97 (hex) V V 0 0 0
(Write Protect Selection)
PGM/ERS Suspend
(Suspends Program/ B0 (hex) 4F (hex) V V 0 0 0
Erase)
PGM/ERS Resume
(Resumes Program/ 30 (hex) CF (hex) V V 0 0 0
Erase)
DP
B9 (hex) 46 (hex) V V 0 0 0
(Deep power down)
RDP
(Release from AB (hex) 54 (hex) V V 0 0 0
deep power down)
NOP
00 (hex) FF (hex) V V 0 0 0
(No Operation)
RSTEN 66 (hex) 99 (hex) V V 0 0 0
(Reset Enable) (Note2)
RST 99 (hex) 66 (hex) V V 0 0 0
(Reset Memory) (Note2)
GBLK
7E (hex) 81 (hex) V V 0 0 0
(gang block lock)
GBULK
98 (hex) 67 (hex) V V 0 0 0
(gang block unlock)
Register Access
RDID 3
9F (hex) 60 (hex) V V 4 00h 00h 00h 00h 4
(read identification) (Note6)
RDSFDP
5A (hex) A5 (hex) V V 4 ADD1 ADD2 ADD3 ADD4 20
(Read SFDP Table)
RDSR 4
05 (hex) FA (hex) V V 4 00h 00h 00h 00h 1
(read status register) (Note4)
RDCR
(read configuration 15 (hex) EA (hex) V V 4 00h 00h 00h 01h 4 1
(Note4)
register)

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Command Set Address Byte

8-8-8 8-8-8 Total Dummy Data
1'st 2'nd (STR) (DTR) Cycle Byte
ADD Byte 1 Byte 2 Byte 3 Byte 4
Byte Byte
Byte
WRSR
01 (hex) FE (hex) V V 4 00h 00h 00h 00h 0 1
(write status register)
WRCR
01 (hex) FE (hex) V V 4 00h 00h 00h 01h 0 1
(configuration register)
RDCR2
(read configuration 71 (hex) 8E (hex) V V 4 ADD1 ADD2 ADD3 ADD4 4 1
(Note4)
register2)
WRCR2
(write configuration 72 (hex) 8D (hex) V V 4 ADD1 ADD2 ADD3 ADD4 0 1
register2)
RDSCUR 4
2B (hex) D4 (hex) V V 4 00h 00h 00h 00h 1
(read security register) (Note4)
WRSCUR
2F (hex) D0 (hex) V V 0 0 0
(write security register)
SBL
C0 (hex) 3F (hex) V V 4 00h 00h 00h 00h 0 1
(Set Burst Length)
RDFBR 4 1-4
16 (hex) E9 (hex) V V 4 00h 00h 00h 00h
(read fast boot register) (Note4) (Note6)
WRFBR
17 (hex) E8 (hex) V V 4 00h 00h 00h 00h 0 4
(write fast boot register)
ESFBR
18 (hex) E7 (hex) V V 0 0 0
(erase fast boot register)
ENSO
B1 (hex) 4E (hex) V V 0 0 0
(enter secured OTP)
EXSO
C1 (hex) 3E (hex) V V 0 0 0
(exit secured OTP)
WRLR
2C (hex) D3 (hex) V V 4 00h 00h 00h 00h 0 1
(write Lock register)
RDLR 4
2D (hex) D2 (hex) V V 4 00h 00h 00h 00h 1
(read Lock register) (Note4)
WRSPB
E3 (hex) 1C (hex) V V 4 ADD1 ADD2 ADD3 ADD4 0 0
(SPB bit program)
ESSPB
E4 (hex) 1B (hex) V V 0 0 0
(all SPB bit erase)
RDSPB 6-20
E2 (hex) 1D (hex) V V 4 ADD1 ADD2 ADD3 ADD4 1
(read SPB status) (Note3)
WRDPB
E1 (hex) 1E (hex) V V 4 ADD1 ADD2 ADD3 ADD4 0 1
(write DPB register)
RDDPB 6-20
E0 (hex) 1F (hex) V V 4 ADD1 ADD2 ADD3 ADD4 1
(read DPB register) (Note3)
RDPASS
27 (hex) D8 (hex) V V 4 00h 00h 00h 00h 20 8
(read password register)
WRPASS
28 (hex) D7 (hex) V V 4 00h 00h 00h 00h 0 8
(write password register)
PASSULK
29 (hex) D6 (hex) V V 4 00h 00h 00h 00h 0 8
(password unlock)
Note 1: It is not recommended to adopt any other code/address not in the command definition table, which will potentially enter
the hidden mode.
Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
Note 3: See dummy cycle and frequency table.
Note 4: 4 dummy cycles in both STR/DTR.
Note 5: The starting address must be even byte (A0 must be 0) in DTR OPI mode.
Note 6: Data bytes are always output in STR.

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9. REGISTER DESCRIPTION

9-1. Status Register

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.

WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be
set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions
are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP
and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be
confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected
memory area, the instruction will be ignored and WEL will clear to “0”.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area
(as defined in Table 3) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP/PP3B/PP4B), Sector
Erase (SE/SE3B/SE4B), Block Erase (BE/BE3B/BE4B) and Chip Erase (CE) instructions (only if Block Protect bits
(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-
protected.

Status Register
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BP3 BP2 BP1 BP0
WEL WIP
(level of (level of (level of (level of
Reserved Reserved (write enable (write in
protected protected protected protected
latch) progress bit)
block) block) block) block)
1=write 1=write
enable operation
Reserved Reserved (note 1) (note 1) (note 1) (note 1)
0=not write 0=not in write
enable operation
Non-volatile Non-volatile Non-volatile Non-volatile
Reserved Reserved volatile bit volatile bit
bit bit bit bit
Note 1: see the Table 3 "Protected Area Size".

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9-2. Configuration Register

The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.

ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as
defined in "Output Driver Strength Table") of the device. To write the ODS bits requires the Write Status Register (WRSR)
instruction to be executed.

TB bit
The Top/Bottom (TB) bit is a non-volatile bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by
BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which
means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To
write the TB bits requires the Write Status Register (WRSR) instruction to be executed.

PBE bit
The Preamble Bit Enable (PBE) bit is a volatile bit. It is used to enable or disable the preamble bit data pattern
output on dummy cycles. The PBE bit is defaulted as “0”, which means preamble bit is disabled. When it is set as “1”,
the preamble bit will be enabled, and inputted into dummy cycles. To write the PBE bits requires the Write Status
Register (WRSR) instruction to be executed.

Configuration Register

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PBE TB ODS 2 ODS 1 ODS 0
Reserved Reserved Reserved (Preamble bit (top/bottom (output driver (output driver (output driver
Enable) selected) strength) strength) strength)
0=Top area
0=Disable protect
x x x 1=Bottom (Note 1) (Note 1) (Note 1)
1=Enable area protect
(Default=0)
x x x volatile bit OTP volatile bit volatile bit volatile bit
Note 1: see "Output Driver Strength Table"

Output Driver Strength Table

ODS2 ODS1 ODS0 Resistance (Ohm) Note
0 0 0 146 Ohms
0 0 1 76 Ohms
0 1 0 52 Ohms
0 1 1 41 Ohms Impedance at VCC/2
1 0 0 34 Ohms (Typical)
1 0 1 30 Ohms
1 1 0 26 Ohms
1 1 1 24 Ohms (Default)

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9-3. Configuration Register 2

Readable/
Address Bit Symbol Description Define Default Type
Writable
Bit 7-2 x Reserved (8) Reserved 0 x x
(3) 00= SPI Volatile
Bit 1 DOPI DTR OPI Enable 0 R/W
00000000h 01= STR OPI enable Bit
10= DTR OPI enable Volatile
Bit 0 SOPI (3) STR OPI Enable 0 R/W
11= inhibit Bit
Bit 7-4 x Reserved (8) Reserved 0 x x
Bit 3-2 x Reserved (8) Reserved 0 x x
0= Disable Volatile
00000200h Bit 1 DOS DQS on STR mode 0 R/W
1= Enable Bit
0= 0 cycle Volatile
Bit 0 DQSPRC DTR DQS pre-cycle 0 R/W
1= 1 cycle Bit
Bit 7-3 x Reserved (8) Reserved 0 x x
00000300h Refer to "Dummy Cycle and Volatile
Bit 2-0 DC Dummy cycle 000 R/W
Frequency Table (MHz)" Bit
Bit 7-2 x Reserved (8) Reserved 0 x x
00= 2 bit error or double
programmed
00000400h ECS# pin goes low 01= 1 or 2 bit error or double Volatile
Bit 1-0 ECS 00 R/W
define programmed Bit
10= 2 bit error only
11= 1 or 2 bit error
Bit 7 x Reserved (8) 0 x x
00= 16Byte
CRC chunk size 01= 32Byte Volatile
Bit 6-5 CRC CYC 00 R/W
configuration 10= 64Byte Bit
11= 128Byte
00000500h
0= CRC# output Disable Volatile
Bit 4 CRCBEN CRC# output enable 0 R/W
1= CRC# output Enable Bit
Bit 3-1 x Reserved (8) Reserved 0 x x
Preamble pattern refer to "Preamble Pattern Volatile
Bit 0 PPTSEL 0 R/W
selection Select Bit Table" Bit
0= ECC failure address invalid
ECC fail address (no fail address recorded) Volatile
Bit 7 ECCFAVLD 0 R (6)
valid indicator 1= ECC failure address valid Bit
(there's fail address recorded)
000= None
00000800h/
xx1= 1 bit corrected
04000800h(5) Volatile
Bit 6-4 ECCFS ECC fail status x1x= 2 bits deteced 000 R (6)
Bit
1xx= Double programmed
page detected
(1) ECC failure chunk Volatile
Bit 3-0 ECCCNT 0000 R (6)
counter Bit

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Readable/
Address Bit Symbol Description Define Default Type
Writable
ECC failure chunk ECC 1st failure chunk Volatile
00000C00h(2)/ Bit 7-4 ECCFA
address address (A7:A4)
x R
Bit
04000C00h(5)
Bit 3-0 x Reserved (8) Reserved x x x
(2)
00000D00h / ECC failure chunk ECC 1st failure chunk Volatile
Bit 7-0 ECCFA x R
04000D00h(5) address address (A15:A8) Bit
(2)
00000E00h / ECC failure chunk ECC 1st failure chunk Volatile
Bit 7-0 ECCFA x R
04000E00h(5) address address (A23:A16) Bit
Bit 7-2 x Reserved (8) Reserved x x x
00000F00h(2)/
(5)
04000F00h Bit 1-0 ECC failure chunk ECC 1st failure chunk Volatile
ECCFA x R
address address (A25:A24) Bit
Bit 7-4 x Reserved (8) Reserved 1 x x
Enable Parity 0= Parity check Enable
Bit 3 CRCEN# 1 R/W OTP
checking 1= Parity check Disable
40000000h Bit 2 x Reserved (8) Reserved 1 x x
Enable DOPI after 00= inhibit
Bit 1 DEFDOPI# (3,4) 1 R/W OTP
Power on or reset 01= default DTR OPI mode
Enable SOPI after 10= default STR OPI mode
Bit 0 DEFSOPI# (3,4) 1 R/W OTP
Power on or reset 11= default SPI mode
Bit 7-5 x Reserved (8) Reserved 0 x x
0= CMD# or Parity check
CMD# or Parity pass Volatile
80000000h Bit 4 CRCERR 0 R (7)
checked fail 1= CMD# or Parity check Bit
fail
Bit 3-0 x Reserved (8) Reserved 0 x x

Notes:
1. ECC failure chunk counter (00000800h bit[3:0]) stops counting once reach maximum value 15. The counting number increases
if user reads the failure chunk multipe times.
2. ECC fail address only records first fail chunk fail address. For both 1bit and 2bit fail. ECCFA is valid only if ECCFAVLD value is 1.
3. The default status of DOPI and SOPI reflect the DEFDOPI# and DEFSOPI# setting. For example, if DEFDOPI#/DEFSOPI#
are 01, DOPI and SOPI value will change to 10 after next Power on or reset and default status of the device will be DTR OPI.
4. The default DEFDOPI# status depends on the device model selection.
5. This 2Gb product was stacked by four 512Mb devices, and each of them owns its own ECC status. User could retrieve the
ECC status of each 512Mb area via accessing the adress A26 & A27 matrix as: 00xxxxxxh (A27-A26=00) for 1st 512Mb
status, 04xxxxxxh (A27-A26=01) for 2nd 512Mb status, 08xxxxxxh (A27-A26=10) for 3rd 512Mb status, 0Cxxxxxxh (A27-A26=11)
for 4th 512Mb status.
6. Write "00" data into 00000800h can reset the ECC status registers.
7. Write "00" data into 80000000h can reset the CMD# or Parity check status register.
8. All reserved bits must keep value factory default. All addresses not shown in the table must keep value unchanged.

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9-3-1. Dummy Cycle and Frequency Table (MHz)

Numbers of Dummy
DC [2:0] Octa I/O STR (MHz) Octa I/O DTR (MHz)
Cycle
000(Default) 20 133 133
001 18 133 133
010 16 133 133
011 14 133 133
100 12 104 104
101 10 104 104
110 8 84 84
111 6 66 66

9-3-2. Preamble Pattern Select Bit Table

All SIOs (Except SIO3) SIO3
Bit 0= 0 0011 0100 1001 1010 0011 0101 0001 0100
Bit 0= 1 0101 0101 0101 0101 0101 0101 0101 0101

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9-4. Security Register

The definition of the Security Register bits is as below:

Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to
"1", if the erase operation fails or the erase region is protected. It will be set to "0", if the last operation is successful.
Please note that it will not interrupt or stop any operation in the flash memory.

Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be
set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is
successful. Please note that it will not interrupt or stop any operation in the flash memory.

Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use
ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB
is set to "1". ESB is cleared to "0" after erase operation resumes.

Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,
PSB is set to "1". PSB is cleared to "0" after program operation resumes.

Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more. While it is in 8K-bit secured OTP mode, main array access is not allowed.

Table 5. Security Register Definition

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

ESB PSB LDSO
Secured OTP
WPSEL E_FAIL P_FAIL Reserved (Erase (Program (indicate if
indicator bit
Suspend bit) Suspend bit) lock-down)
0=normal 0 = not lock-
0=normal 0=Erase 0=Program
0=normal Program down 0 = non-
Erase is not is not
WP mode succeed 1 = lock-down factory
succeed suspended suspended
1=individual 1=indicate - (cannot lock
1=indicate 1= Erase 1= Program
mode Program program/ 1 = factory
Erase failed suspended suspended
(default=0) failed erase lock
(default=0) (default=0) (default=0)
(default=0) OTP)
Non-volatile
Non-volatile Non-volatile
Volatile bit Volatile bit - Volatile bit Volatile bit bit
bit (OTP) bit (OTP)
(Read only)

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10. COMMAND DESCRIPTION

10-1. Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/
PP3B/PP4B, SE/SE3B/SE4B, BE/BE3B/BE4B, CE, WRSR, WRCR2, SBL, WRFBR, ESFBR, WRSCUR, WRLR,
WSPB and ESSPB which are intended to change the device content WEL bit should be set every time after the
WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.

Figure 5. Write Enable (WREN) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 06h

High-Z
SO

Figure 6. Write Enable (WREN) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 06h F9h

Figure 7. Write Enable (WREN) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 06h F9h

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10-2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI
instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- WRDI command completion
- WRSR/WRCR/WRCR2 command completion
- PP/PP3B/PP4B command completion
- SE/SE3B/SE4B/BE/BE3B/BE4B/CE command completion
- SBL command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
- WRFBR/ESFBR command completion
- WRLR/WSPB/ESSPB command completion
- GBLK/GBULK command completion

Figure 8. Write Disable (WRDI) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 04h

High-Z
SO

Figure 9. Write Disable (WRDI) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 04h FBh

Figure 10. Write Disable (WRDI) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 04h FBh

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10-3. Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as Table 6 ID Definitions.

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.

Table 6. ID Definitions
Manufacturer ID Memory type Memory density
RDID 9Fh
C2 80 3C

Figure 11. Read Identification (RDID) Sequence (SPI mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 28 29 30 31
SCLK

Command

SI 9Fh

Manufacturer Identification Device Identification

High-Z
SO 7 6 5 2 1 0 15 14 13 3 2 1 0

MSB MSB

Figure 12. Read Identification (RDID) Sequence (STR-OPI Mode)

CS#

SCLK

Pre-drive
SIO[7:0] 9Fh 60h 00 00 00 00 MID Type Density

Address Dummy

Figure 13. Read Identification (RDID) Sequence (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive
SIO[7:0] 9Fh 60h 00 00 00 00 MID Type Density

Address Dummy

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10-4. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.

Figure 14. Read Status Register (RDSR) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

command

SI 05h

Status Register Out Status Register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

Figure 15. Read Status Register (RDSR) Sequence (STR-OPI Mode)

CS#

SCLK

Pre-drive
SIO[7:0] 05h FAh 00 00 00 00 SR SR

Address Dummy

Figure 16. Read Status Register (RDSR) Sequence (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive
SIO[7:0] 05h FAh 00 00 00 00 SR SR

Address Dummy

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For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:

Figure 17. Program/Erase flow with read array data

start

WREN command

RDSR command*

No
WEL=1?

Yes
Program/erase command

Write program data/address

(Write erase address)

RDSR command

No
WIP=0?

Yes
RDSR command

Read WEL=0, BP[3:0]

Read array data

(same address of PGM/ERS)

No
Verify OK?

Yes
Program/erase successfully Program/erase fail

Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
No
Program/erase completed

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Figure 18. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)

start

WREN command

RDSR command*

No
WEL=1?

Yes
Program/erase command

Write program data/address

(Write erase address)

RDSR command

No
WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0]

RDSCUR command

Yes
P_FAIL/E_FAIL =1 ?

No
Program/erase successfully Program/erase fail

Program/erase Yes
another block?
* Issue RDSR to check BP[3:0].
No
Program/erase completed

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10-5. Read Configuration Register (RDCR)

The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition).

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.

Figure 19. Read Configuration Register (RDCR) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

command

SI 15h

Configuration register Out Configuration register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

Figure 20. Read Configuration Register (RDCR) (STR-OPI Mode)

CS#

SCLK

Pre-drive
SIO[7:0] 15h EAh 00 00 00 01 CR CR

Address Dummy

Figure 21. Read Configuration Register (RDCR) (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive
SIO[7:0] 15h EAh 00 00 00 01 CR CR

Address Dummy

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10-6. Write Status Register (WRSR) / Write Configuration Register (WRCR)

The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in "Table 3. Protected Area Sizes"). The WRSR has no
effect on bit1(WEL) and bit0 (WIP) of the status register.

In SPI, CS# must go high exactly at the 8 bits or 16 bits data boundary; In DOPI, CS# must go high while clock is
low; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW)
is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during
the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status
Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Figure 22. Write Status Register (WRSR) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK

command Status Configuration

Register In Register In

SI 01h 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

High-Z MSB
SO

Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.

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Figure 23. Write Status Register (WRSR) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 01h FEh 00 00 00 00 SR

Figure 24. Write Status Register (WRSR) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 01h FEh 00 00 00 00 SR

Note: CS# must go high while SCLK is low.

Figure 25. Write Configuration Register (WRCR) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 01h FEh 00 00 00 01 CR

Figure 26. Write Configuration Register (WRCR) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 01h FEh 00 00 00 01 CR

Note: CS# must go high while SCLK is low.

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Figure 27. WRSR flow

start

WREN command

RDSR command

No
WEL=1?

Yes
WRSR command

Write status register data

RDSR command

No
WIP=0?

Yes
RDSR command

Read WEL=0, BP[3:0]

No
Verify OK?

Yes
WRSR successfully WRSR fail

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10-7. Read Configuration Register 2 (RDCR2)

The RDCR2 instruction is for reading Configuration Register 2. Except CRCERR bit, the Read Configuration
Register 2 command would be rejected while Internal write operation is in progress (WIP=1).

The sequence of issuing RDCR2 instruction is: CS# goes low→ sending RDCR2 instruction code→ Sending 4 byte
address → Configuration Register 2 data out on SO.

Figure 28. Read Configuration Register 2 (RDCR2) Sequence (SPI Mode)

CS#

SCLK

command Address *

SI 71h 31 30 29 3 2 1 0

MSB
CR2 CR2
High-Z
SO 7 6 5 4 3 2 1 0 7
MSB

Note: * See "9-3. Configuration Register 2" for defining address .

Figure 29. Read Configuration Register 2 (RDCR2) Sequence (STR-OPI Mode)

CS#

SCLK

Pre-drive
SIO[7:0] 71h 8Eh A[31:24] A[23:16] A[15:8] A[7:0] CR2 CR2

Address * Dummy

Note: * See "9-3. Configuration Register 2" for defining address .

Figure 30. Read Configuration Register 2 (RDCR2) (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive
SIO[7:0] 71h 8Eh A[31:24] A[23:16] A[15:8] A[7:0] CR2 CR2

Address * Dummy

Note: * See "9-3. Configuration Register 2" for defining address .

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10-8. Write Configuration Register 2 (WRCR2)

The WRCR2 instruction is for changing the values of Configuration Register 2. Before sending WRCR2 instruction,
the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in
advance.

In SPI, CS# must go high exactly at the 8 bits data boundary; In DOPI, CS# must go high while clock is low;
otherwise, the instruction will be rejected and not executed, and the Write Enable Latch (WEL) bit is reset.

Figure 31. Write Configuration Register 2 (WRCR2) Sequence (SPI Mode)

CS#

SCLK

Command Address * CR2

SI 72h 31 30 29 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB

Note 1: * See "9-3. Configuration Register 2" for defining address .

Figure 32. Write Configuration Register 2 (WRCR2) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 72h 8Dh A[31:24] A[23:16] A[15:8] A[7:0] CR2

Address *

Note 1: * See "9-3. Configuration Register 2" for defining address .

Figure 33. Write Configuration Register 2 (WRCR2) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 72h 8Dh A[31:24] A[23:16] A[15:8] A[7:0] CR2

Address *

Note 1 : * See "9-3. Configuration Register 2" for defining address.

Note 2 : CS# must go high while SCLK is low

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10-9. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.

Figure 34. Read Security Register (RDSCUR) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

command

SI 2Bh

Security register Out Security register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

Figure 35. Read Security Register (RDSCUR) Sequence (STR-OPI Mode)

CS#

SCLK

Pre-drive
Security Security
SIO[7:0] 2Bh D4h 00 00 00 00 Register Register

Address Dummy

Figure 36. Read Security Register (RDSCUR) Sequence (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive
Security Security
SIO[7:0] 2Bh D4h 00 00 00 00 Register Register

Address Dummy

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10-10. Write Security Register (WRSCUR)

The WRSCUR instruction sets the LDSO bit of the Security Register. The WREN (Write Enable) instruction is
required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 4K-bit customer usage area of Secured OTP. Once the LDSO bit is set to "1", the
customer usage area of Secured OTP cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

Figure 37. Write Security Register (WRSCUR) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 2Fh

High-Z
SO

Figure 38. Write Security Register (WRSCUR) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 2Fh D0h

Figure 39. Write Security Register (WRSCUR) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 2Fh D0h

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10-11. Read Data Bytes (READ/READ3B/READ4B)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The address is automatically increased to the next higher
address after each byte data is shifted out, so the whole memory can be read out at a single READ/READ3B/
READ4B instruction. The address counter rolls over to 0 when the highest address has been reached.

The sequence of issuing READ/READ3B/READ4B instruction is: CS# goes low→sending READ/READ3B/READ4B
instruction code→ 3-byte or 4-byte address on SI→ data out on SO→to end READ/READ3B/READ4B operation
can use CS# to high at any time during data out.

Figure 40. Read Data Bytes (READ/READ3B/READ4B) Sequence (SPI Mode only)

CS#

SCLK

Command 24/32-Bit Address

(Note)

SI 03h/13h (Note) 31 30 29 3 2 1 0

MSB
Data Out 1 Data Out 2
High-Z
SO 7 6 5 4 3 2 1 0 7
MSB

Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.

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10-12. Read Data Bytes at Higher Speed (FAST_READ/FAST_READ3B/FAST_READ4B)

The FAST_READ/FAST_READ3B/FAST_READ4B instruction is for quickly reading data out. The address is latched
on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single FAST_READ/FAST_READ3B/FAST_READ4B instruction. The address counter
rolls over to 0 when the highest address has been reached.

The sequence of issuing FAST_READ/FAST_READ3B/FAST_READ4B instruction is: CS# goes low→ sending
FAST_READ/FAST_READ3B/FAST_READ4B instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles
→ data out on SO→ to end FAST_READ/FAST_READ3B/FAST_READ4B operation can use CS# to high at any
time during data out.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ/FAST_READ3B/FAST_READ4B

instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 41. Read at Higher Speed (FAST_READ/FAST_READ3B/FAST_READ4B) Sequence (SPI Mode only)

CS#

SCLK

Command 24/32-Bit Address

(Note)
SI 0Bh/0Ch (Note) 31 30 29 3 2 1 0

High-Z
SO

CS#

SCLK

Dummy Cycle

SI 7 6 5 4 3 2 1 0

DATA OUT 1 DATA OUT 2

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.

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10-13. OCTA Read Mode (8READ)

The 8READ instruction enable Octa throughput of Serial NOR Flash in read mode. An OPI Enable bit of
Configuration Register 2 must be set to "1" before sending the STR Octa READ instruction.

While Program/Erase/Write Status Register cycle is in progress, 8READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.

Figure 42. OCTA Read Mode Sequence (STR-OPI Mode)

CS#

≈
≈
SCLK

DQS

≈
(Note1)

Pre-drive
SIO[7:0] ECh 13h A[31:24] A[23:16] A[15:8] A[7:0] ≈ D0 D1 D2 D3

Address Dummy

Note1: DQS is enabled only when DOS (DQS on STR mode) bit is set. Otherwise, it keeps Hi-Z.

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10-14. OCTA DTR Read Mode (8DTRD)

The 8DTRD instruction enable DTR Octa throughput of Serial NOR Flash in read mode. An DOPI Enable bit of
Configuration Register 2 must be set to "1" before sending the DTR Octa READ instruction.

While Program/Erase/Write Status Register cycle is in progress, 8DTRD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.

In DTR Octa READ mode, the starting address must be even byte (A0=0).

Figure 43. OCTA Read Mode Sequence (DTR-OPI Mode)

CS#

≈
SCLK

DQS ≈
≈

SIO[7:0]
≈

EEh 11h A[31:24]A[23:16] A[15:8] A[7:0] D1 D0 D3 D2

Address Dummy

word unit word unit

Figure 44. OCTA Read Mode Sequence (DTR-OPI Mode) with DQS pre-cycle enabled (CR2 DQSPRC=1)

CS#
≈

SCLK
≈

DQS
≈

SIO[7:0]
≈

EEh 11h A[31:24]A[23:16] A[15:8] A[7:0] D1 D0 D3 D2

Address Dummy

word unit word unit

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10-15. Preamble Bit

The Preamble Bit data pattern supports system/memory controller to determine the valid windows of data output
more easily and improve data capture reliability while the flash memory is running in high frequency.

The preamble bit is designed as a 16-bit data pattern, which can be enabled or disabled by setting the bit4 of
Configuration register (Preamble bit Enable bit). Once CR<4> is set, the preamble bit is inputted into dummy
cycles. Two different patterns are selectable by setting CR<2> PSB (Pattern Select Bit), and please refer to "9-3.
Configuration Register 2" for details.

Once Preamble Bit feature is enabled, the preamble bit pattern will be output after a pre-driven signal. When the
device is under OPI mode, all SIO pins except SIO3 will output the same learning pattern. The signal on SIO3 will
be different from other I/O pins in case PSB=0.

In OPI, when dummy cycle number reaches 20, the complete 16 bits will start to output right after the pre-driven
signal. When dummy cycle number is not sufficient of 16 cycles, the rest of the preamble bits will be cut off.

In DOPI, when dummy cycles number reaches 12, the complete 16 bits will start to output right after the pre-driven
signal.

Figure 45. Preamble Bit data pattern Output Sequence (STR-OPI Mode)

CS#

SCLK
Preamble Bits
Pre-drive
SIO[7:0] ECh 13h A[31:24] A[23:16] A[15:8] A[7:0] P0 P1 P2 P3 D[7:0] D[7:0]

Address Dummy

Note: 8 dummy cycle example.

Figure 46. Preamble Bit data pattern Output Sequence (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive Preamble Bits
A A A A
SIO[7:0] EEh 11h [31:24] [23:16] [15:8] [7:0] P0 P1 P2 P3 D[7:0] D[7:0] D[7:0] D[7:0]

Address Dummy

Note: 6 dummy cycle example.

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10-16. Burst Read

To set the Burst length, following command operation is required to issue command: “C0h” in the first Byte, following
clock defining wrap around register value.

Their definitions are as the following table:

Data Wrap Around Wrap Depth
00h Reserved Reserved
01h Yes 16-byte
02h Yes 32-byte
03h Yes 64-byte
1xh No X
The wrap around unit is defined with the 16/32/64 Byte, with random initial address. It is defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0h” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0h” command in which data=“0xh”. The device is default without
Burst read.

Figure 47. Set Burst Length (SPI Mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCLK

SI C0h D7 D6 D5 D4 D3 D2 D1 D0

Figure 48. Set Burst Length (STR-OPI Mode)

CS#

SCLK

SIO[7:0] C0h 3Fh 00 00 00 00 SBL

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10-17. Fast Boot

The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset
without any read instruction.

A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also define the number of
delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register)
and ESFBR (erase fast boot register) can be used for the status configuration or alternation of the Fast Boot
Register bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The
default number of delay cycles is 21 cycles in OPI/DOPI; while the number of delay cycles is 13 in SPI and there is
a 16bytes boundary address for the start of boot code access.

When CS# starts to go low, data begins to output from default address after the delay cycles. After CS# returns to
go high, the device will go back to standard SPI/OPI/DOPI mode and user can start to input command. In the fast
boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output.

Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,
reset command, or hardware reset operation.

Fast Boot Register (FBR)

Bits Description Bit Status Default State Type
FBSA (FastBoot Start 16 bytes boundary address for the start of boot Non-
31 to 4 FFFFFFF
Address) code access. Volatile
Non-
3 Reserved 1
Volatile
00: 11 delay cycles
FBSD (FastBoot Start 01: 15 delay cycles Non-
2 to 1 11
Delay Cycle) 10: 17 delay cycles Volatile
11: 21 delay cycles
0=FastBoot is enabled. Non-
0 FBE (FastBoot Enable) 1
1=FastBoot is not enabled. Volatile

Figure 49. Fast Boot Sequence (SPI Mode)

CS#

0 - - - - - - n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11n+12n+13n+14n+15

SCLK

Delay Cycles
Don’t care or High Impedance
SI

Data Out 1 Data Out 2

High Impedance
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

Note: The delay cycle is always 13 in SPI mode.

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Figure 50. Fast Boot Sequence (STR-OPI Mode)

CS#

≈
0 1 n-1 n n+1 n+2 n+3

≈
SCLK

Pre-drive
SIO[7:0]

≈
D0 D1 D2 D3

Delay Cycles

Note: If FBSD = 11, delay cycles is 21 and n is 20.

If FBSD = 10, delay cycles is 17 and n is 16.
If FBSD = 01, delay cycles is 15 and n is 14.
If FBSD = 00, delay cycles is 11 and n is 10.

Figure 51. Fast Boot Sequence (DTR-OPI Mode)

CS#
≈ ≈

0 1 n-2 n-1 n n+1

SCLK

DQS
≈

Pre-drive
SIO[7:0]
≈

D1 D0 D3 D2

Delay Cycles

Note: If FBSD = 11, delay cycles is 21 and n is 21.

If FBSD = 10, delay cycles is 17 and n is 17.
If FBSD = 01, delay cycles is 15 and n is 15.
If FBSD = 00, delay cycles is 11 and n is 11.

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Figure 52. Read Fast Boot Register (RDFBR) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 37 38 39 40 41
SCLK

Command

SI 16h

Data Out 1 Data Out 2

High-Z
SO 7 6 5 26 25 24 7 6
MSB MSB

Figure 53. Read Fast Boot Register (RDFBR) Sequence (STR-OPI Mode)

CS#

SCLK

Pre-drive
SIO[7:0] 16h E9h 00 00 00 00 FBR1 FBR2

Address Dummy

Figure 54. Read Fast Boot Register (RDFBR) Sequence (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive
SIO[7:0] 16h E9h 00 00 00 00 FBR1 FBR2

Address Dummy

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Figure 55. Write Fast Boot Register (WRFBR) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 37 38 39
SCLK

Command Fast Boot Register

SI 17h 7 6 5 26 25 24
MSB

High-Z
SO

Figure 56. Write Fast Boot Register (WRFBR) Sequence (STR-OPI Mode)

CS#

≈
SCLK

≈ ≈ ≈
SIO[7:0] 17h E8h 00 00 00 00 FBR1 FBR4

Figure 57. Write Fast Boot Register (WRFBR) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 17h E8h 00 00 00 00 FBR1 FBR2 FBR3 FBR4

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Figure 58. Erase Fast Boot Register (ESFBR) Sequence

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 18h

High-Z
SO

Figure 59. Erase Fast Boot Register (ESFBR) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 18h E7h

Figure 60. Erase Fast Boot Register (ESFBR) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 18h E7h

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10-18. Sector Erase (SE/SE3B/SE4B)

The Sector Erase (SE/SE3B/SE4B) instruction is for erasing the data of the chosen sector to be "1". The instruction
is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Sector Erase (SE/SE3B/SE4B). Any address of the sector (Please refer to "5. MEMORY
ORGANIZATION") is a valid address for Sector Erase (SE/SE3B/SE4B) instruction. The CS# must go high exactly
at the byte boundary (the least significant bit of the address byte been latched-in); otherwise, the instruction will be
rejected and not executed.

The sequence of issuing SE/SE3B/SE4B instruction is: CS# goes low→ sending SE/SE3B/SE4B instruction code→
3-byte or 4-byte address → CS# goes high.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the Block is protected by BP bits (Block Protect Mode), the Sector Erase (SE/SE3B/SE4B) instruction will not be
executed on the block.

Figure 61. Sector Erase (SE/SE3B/SE4B) Sequence (SPI Mode)

CS#

SCLK

Command 24/32-Bit Address

(Note)
SI 20h/21h (Note) 31 30 2 1 0
MSB

Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.

Figure 62. Sector Erase (SE) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 21h DEh A[31:24] A[23:16] A[15:8] A[7:0]

Figure 63. Sector Erase (SE) Sequence (DTR-OPI Mode)

CS#

SCLK

A A A A
SIO[7:0] 21h DEh [31:24] [23:16] [15:8] [7:0]

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10-19. Block Erase (BE/BE3B/BE4B)

The Block Erase (BE/BE3B/BE4B) instruction is for erasing the data of the chosen block to be "1". The instruction
is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write
Enable Latch (WEL) bit before sending the Block Erase (BE/BE3B/BE4B). Any address of the block (Please refer to
"5. MEMORY ORGANIZATION") is a valid address for Block Erase (BE/BE3B/BE4B) instruction. The CS# must go
high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction
will be rejected and not executed.

The sequence of issuing BE/BE3B/BE4B instruction is: CS# goes low→ sending BE/BE3B/BE4B instruction code→
3-byte or 4-byte address → CS# goes high.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE
timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block
is protected by BP bits (Block Protect Mode), the Block Erase (BE/BE3B/BE4B) instruction will not be executed on
the block.

Figure 64. Block Erase (BE/BE3B/BE4B) Sequence (SPI Mode)

CS#

SCLK

Command 24/32-Bit Address

(Note)

SI D8h/DCh (Note) 31 30 2 1 0
MSB

Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.

Figure 65. Block Erase (BE) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] DCh 23h A[31:24] A[23:16] A[15:8] A[7:0]

Figure 66. Block Erase (BE) Sequence (DTR-OPI Mode)

CS#

SCLK

A A A A
SIO[7:0] DCh 23h [31:24] [23:16] [15:8] [7:0]

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10-20. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE
timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

When the chip is under "Block protect (BP) Mode". The Chip Erase (CE) instruction will not be executed, if one (or
more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".

Figure 67. Chip Erase (CE) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI 60h or C7h

Figure 68. Chip Erase (CE) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 60h or C7h 9Fh or 38h

Figure 69. Chip Erase (CE) Sequence (DTR-OPI Mode)

CS#

SCLK

60h or 9Fh or
SIO[7:0] C7h 38h

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10-21. Page Program (PP/PP3B/PP4B)

The Page Program (PP/PP3B/PP4B) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit before sending each Page Program (PP/
PP3B/PP4B) command. The device programs only the last 256 data bytes sent to the device. The last address
byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all
zero, transmitted data that exceed page length are programmed from the starting address (32-bit address that last
8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte
is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has
not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the
other data bytes of the same page. Please refer "12-1. ECC (Error Checking and Correcting)" for Partial program or
double program restriction.

In DTR OPI, the starting address given must be even address (A0=0) and data byte number must be even.

The sequence of issuing PP/PP3B/PP4B instruction is: CS# goes low→ sending PP/PP3B/PP4B instruction code→
3-byte or 4-byte address → at least 1-byte on data in SPI and STR OPI; at least two bytes in DOPI→ CS# goes
high.

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary in SPI (the latest eighth bit of data being latched in), CS# must go high while SCLK is low in DOPI,
otherwise the instruction will be rejected and will not be executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the page is protected by BP bits (Block Protect Mode), the Page Program (PP/PP3B/PP4B) instruction will not be
executed.

Figure 70. Page Program (PP/PP3B/PP4B) Sequence (SPI Mode)

CS#

SCLK

Command 24/32-Bit Address Data Byte 1

(Note)

SI 02h/12h (Note) 31 30 29 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB

CS#

SCLK

Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB MSB

Note: The number of address cycles are based on different address mode. In 3-Byte command operation, it is 24-bit.
In 4-Byte command operation, it is 32-bit.

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Figure 71. Page Program (PP) Sequence (STR-OPI Mode)

tCHSH

CS#

≈
tSLCH
SCLK

≈
≈≈
SIO[7:0] 12h EDh A[31:24] A[23:16] A[15:8] A[7:0] D0 D1 D254 D255

Figure 72. Page Program (PP) Sequence (DTR-OPI Mode)

tSLCH tCLSH

CS#

≈
SCLK

≈ ≈ ≈
SIO[7:0] 12h A
EDh [31:24] A A A
D1 D0 D255 D254
[23:16] [15:8] [7:0]

word unit word unit

Note: CS# must go high while SCLK is low.

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10-22. Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby
current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby
mode.

The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.

Figure 73. Deep Power-down (DP) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 tDP

SCLK

Command

SI B9h

Stand-by Mode Deep Power-down Mode

Figure 74. Deep Power-down (DP) Sequence (STR-OPI Mode)

CS#
tDP

SCLK

SIO[7:0] B9h 46h

Stand-by Mode Deep Power-down Mode

Figure 75. Deep Power-down (DP) Sequence (DTR-OPI Mode)

CS#

tDP
SCLK

SIO[7:0] B9h 46h

Stand-by Mode Deep Power-down Mode

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10-23. Release from Deep Power-down (RDP)

The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip
Select (CS#) must remain High for at least tRES1(max), as specified in Table 15 AC Characteristics. Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The
RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from
deep power down mode.

Even in Deep power-down mode, the RDP is also allowed to be executed, only except the device is in progress of
program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.

Figure 76. Release from Deep Power-down (RDP) Sequence (SPI Mode)

CS#

0 1 2 3 4 5 6 7 tRES1

SCLK

Command

SI ABh

High-Z
SO

Deep Power-down Mode Stand-by Mode

Figure 77. Release from Deep Power-down (RDP) Sequence (STR-OPI Mode)

CS#
tRES1

SCLK

SIO[7:0] ABh 54h

Deep Power-down Mode Stand-by Mode

Figure 78. Release from Deep Power-down (RDP) Sequence (DTR-OPI Mode)

CS#

tRES1
SCLK

SIO[7:0] ABh 54h

Deep Power-down Mode Stand-by Mode

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10-24. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 8K-bit secured OTP mode. While device is in 8K-bit secured
OTP mode, main array access is not available. The additional 8K-bit secured OTP is independent from main array
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated
again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.

Please note that after issuing ENSO command user can only access secure OTP region with standard read or
program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.

10-25. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 8K-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.

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10-26. Write Protection Selection (WPSEL)

There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced
Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection
mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is
disabled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL
command is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the
WPSEL command. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be
programmed back to “0”.

When WPSEL = 0: Block Protection (BP) mode,

The memory array is write protected by the BP3~BP0 bits.

When WPSEL =1: Advanced Sector Protection mode,

Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the
Dynamic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRPASS,
RDPASS, PASSULK, WRSPB, ESSPB, WRDPB, RDDPB, GBLK, and GBULK are activated. The BP3~BP0 bits of
the Status Register are disabled and have no effect.

The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced
Sector Protect mode → CS# goes high.

Write Protection Selection

Start
(Default in BP Mode)

WPSEL=1 Set WPSEL=0

WPSEL Bit

Advanced Block Protection

Sector Protection (BP)

Set Bit 2 =1
Lock Register

Bit 2 =0

Password Solid Dynamic

Protection Protection Protection

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10-27. Advanced Sector Protection

There are two ways to implement software Advanced Sector Protection on this device. Through these two protection
methods, user can disable or enable the programming or erasing op­eration to any individual sector or all sectors.

There is a non-volatile (SPB) and volatile (DPB) protection bit related to the single sector in main flash array. Each
of the sectors is protected from programming or erasing operation when the bit is set.

The figure below helps describing an overview of these methods. The device is default to the Solid mode when
shipped from factory. The detail algorithm of advanced sector protection is shown as follows:

Figure 79. Advanced Sector Protection Overview

Start

Bit 2=1 Bit 2=0

Set
Lock Register ?

Solid Protection Mode Password Protection Mode

Set 64 bit Password

Set Bit 6 = 0 SPB Locked

SPB Lock Down Bit ? All SPB can not be changeable
(SPBLKDN)

Bit 6 = 1

SPB Unlocked
SPB is changeable

Dynamic Protect Bit Register Solid Protection Bits

(DPB) (SPB)

Sector Array
DPB=1 sector protect SPB=1 Write Protect

DPB=0 sector unprotect SPB=0 Write Unprotect

DPB 0 SA 0 SPB 0

DPB 1 SA 1 SPB 1

DPB 2 SA 2 SPB 2
: : :
: : :

DPB N-1 SA N-1 SPB N-1

DPB N SA N SPB N

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10-27-1. Lock Register

The Lock Register is a 8-bit register. Lock Register Bit[6] is SPB Lock Down Bit (SPBLKDN) which is assigned to
control all SPB bit status. Lock Register Bit[2] is Password Protection Mode Lock Bit. Both bits are defaulted as 1
when shipping from factory.

When SPBLKDN is 1, SPB can be changed. When it is locked as 0, all SPB can not be changed.

Users can choose their favorite sector protecting method via setting Lock Register Bit[2] using WRLR command.
The device default status was in Solid Protection Mode (Bit[2]=1), Once Bit[2] has been programmed (cleared to
"0"), the device will enable the Password Protection Mode and lock in that mode permanently.

In Solid Protection Mode (Bit[2]=1, factory default), the SPBLKDN can be programmed using the WRLR command
and permanently lock down the SPB bits. After programming SPBLKDN to 0, all SPB can not be changed anymore,
and neither Lock Register Bit[2] nor Bit[6] can be altered anymore.

In Password Protection Mode (Bit[2]=0), the SPBLKDN becomes a volatile bit with default 0 (SPB bit protected).
A correct password is required with PASSULK command to set SPBLKDN to 1. To clear SPBLKDN back to 0, a
Hardware/Software Reset or power-up cycle is required.

If user selects Password Protection mode, the password setting is required. User can set password by issuing
WRPASS command before Lock Register Bit[2] set to 0.

Lock Register
Bits Description Bit Status Default Type
7 Reserved Reserved Reserved
SPB Lock Down bit 0: SPB bit Protected Solid Protection Mode: 1 Bit 2=1: OTP
6
(SPBLKDN) 1: SPB bit Unprotected Password Protection Mode: 0 Bit 2=0: Volatile
5 to 3 Reserved Reserved Reserved

Password Protection 0=Password Protection Mode Enable

2 1 OTP
Mode Lock Bit 1= Solid Protection Mode

1 to 0 Reserved Reserved Reserved

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Figure 80. Read Lock Register (RDLR) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

command

SI 2Dh

Register Out
High-Z
SO 7 6 5 4 3 2 1 0 7

MSB

Figure 81. Read Lock Register (RDLR) Sequence (STR-OPI Mode)

CS#

SCLK

Pre-drive
SIO[7:0] 2Dh D2h 00 00 00 00 LR LR

Address Dummy

Figure 82. Read Lock Register (RDLR) Sequence (DTR-OPI Mode)

CS#

SCLK

DQS
Pre-drive
SIO[7:0] 2Dh D2h 00 00 00 00 LR LR

Address Dummy

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Figure 83. Write Lock Register (WRLR) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK

Command Lock Register In

SI 2Ch 7 6 5 4 3 2 1 0

MSB
High-Z
SO

Figure 84. Write Lock Register (WRLR) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] 2Ch D3h 00 00 00 00 LR

Figure 85. Write Lock Register (WRLR) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] 2Ch D3h 00 00 00 00 LR

Note: CS# must go high while SCLK is low.

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10-27-2. Solid Protection Bits

The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.
The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom
and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits
is “0”, which has the sector/block write-protection disabled.

When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the
sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs
cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must
be executed to set the WEL bit before sending the WRSPB or ESSPB command.

The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the
SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating
write-protection is enabled.

Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored.

SPB Register
Bit Description Bit Status Default Type
00h = Unprotect Sector / Block
7 to 0 SPB (Solid Protection Bit) 00h Non-volatile
FFh = Protect Sector / Block

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Figure 86. Read SPB Status (RDSPB) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 37 38 39 40 41 42 43 44 45 46 47
SCLK

Command 32-Bit Address

SI E2h A31 A30 A2 A1 A0

MSB
Data Out
High-Z
SO 7 6 5 4 3 2 1 0

MSB

Figure 87. Read SPB Status (RDSPB) Sequence (STR-OPI Mode)

CS#

≈
SCLK

≈
Pre-drive
≈
SIO[7:0] E2h 1Dh A[31:24] A[23:16] A[15:8] A[7:0] SPB SPB

Address Dummy

Figure 88. Read SPB Status (RDSPB) Sequence (DTR-OPI Mode)

CS#
≈

SCLK
≈
≈

DQS
Pre-drive
A A A A
≈

SIO[7:0] E2h 1Dh [31:24] [23:16] [15:8] [7:0] SPB SPB

Address Dummy

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Figure 89. SPB Erase (ESSPB) Sequence

CS#

0 1 2 3 4 5 6 7
SCLK

Command

SI E4h

High-Z
SO

Figure 90. SPB Erase (ESSPB) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] E4h 1Bh

Figure 91. SPB Erase (ESSPB) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] E4h 1Bh

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Figure 92. SPB Program (WRSPB) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 37 38 39
SCLK

Command 32-Bit Address

SI E3h A31 A30 A2 A1 A0

MSB

Figure 93. SPB Program (WRSPB) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] E3h 1Ch A[31:24] A[23:16] A[15:8] A[7:0]

Figure 94. SPB Program (WRSPB) Sequence (DTR-OPI Mode)

CS#

SCLK

A A A A
SIO[7:0] E3h 1Ch [31:24] [23:16] [15:8] [7:0]

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10-27-3. Dynamic Write Protection Bits

The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from
unintentional change, and is easy to disable when there are necessary changes.

All DPBs are default as protected (FFh) after reset or upon power up cycle. Via setting up Dynamic Protection bit (DPB)
by write DPB command (WRDPB), user can cancel the Dynamic Protection of associated sector.

The Dynamic Protection only works on those unprotected sectors whose SPBs are cleared. After the DPB state is
cleared to “0”, the sector can be modified if the SPB state is unprotected state.

DPB Register
Bit Description Bit Status Default Type
00h= DPB for the sector address unprotected
7 to 0 DPB (Dynamic protected Bit) FFh Volatile
FFh= DPB for the sector address protected

Figure 95. Read DPB Register (RDDPB) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 37 38 39 40 41 42 43 44 45 46 47
SCLK

Command 32-Bit Address

SI E0h A31 A30 A2 A1 A0

MSB
Data Out
High-Z
SO 7 6 5 4 3 2 1 0

MSB

Figure 96. Read DPB Register (RDDPB) Sequence (STR-OPI Mode)

CS#
≈

SCLK
≈

Pre-drive
≈

SIO[7:0] E0h 1Fh A[31:24] A[23:16] A[15:8] A[7:0] DPB DPB

Address Dummy

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Figure 99. Read DPB Register (RDDPB) Sequence (DTR-OPI Mode)

CS#

≈
SCLK

≈
≈
DQS
Pre-drive
A A A A

≈
SIO[7:0] E0h 1Fh [31:24] [23:16] [15:8] [7:0] DPB DPB

Address Dummy

Figure 97. Write DPB Register (WRDPB) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 37 38 39 40 41 42 43 44 45 46 47
SCLK

Command 32-Bit Address Data Byte 1

SI E1h A31 A30 A2 A1 A0 7 6 5 4 3 2 1 0

MSB MSB

Figure 98. Write DPB Register (WRDPB) Sequence (STR-OPI Mode)

CS#

SCLK

SIO[7:0] E1h 1Eh A[31:24] A[23:16] A[15:8] A[7:0] DPB

Address

Figure 100. Write DPB Register (WRDPB) Sequence (DTR-OPI Mode)

CS#

SCLK

SIO[7:0] E1h 1Eh A[31:24] A[23:16] A[15:8] A[7:0] DPB

Address

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10-27-4. Password Protection Mode

Password Protection mode potentially provides a higher level of security than Solid Protection mode. In Password
Protection mode, the SPBLKDN bit defaults to “0” after a power-on cycle or reset. When SPBLKDN=0, the SPBs
are locked and cannot be modified. A 64-bit password must be provided to unlock the SPBs.

The PASSULK command with the correct password will set the SPBLKDN bit to “1” and unlock the SPB bits. After
the correct password is given, a wait of 2us is necessary for the SPB bits to unlock. The Status Register WIP bit will
clear to “0” upon completion of the PASSULK command. Once unlocked, the SPB bits can be modified. A WREN
command must be executed to set the WEL bit before sending the PASSULK command.

Several steps are required to place the device in Password Protection mode. Prior to entering the Password
Protection mode, it is necessary to set the 64-bit password and verify it. The WRPASS command writes the
password and the RDPASS command reads back the password. Password verification is permitted until the
Password Protection Mode Lock Bit has been written to “0”. Password Protection mode is activated by programming
the Password Protection Mode Lock Bit to “0”. This operation is not reversible. Once the bit is programmed, it
cannot be erased. The device remains permanently in Password Protection mode and the 64-bit password can
neither be retrieved nor reprogrammed.

The password is all “1’s” when shipped from the factory. The WRPASS command can only program password bits to “0”.
The WRPASS command cannot program “0’s” back to “1’s”. All 64-bit password combinations are valid password
options. A WREN command must be executed to set the WEL bit before sending the WRPASS command.

● The unlock operation will fail if the password provided by the PASSULK command does not match the stored
password. This will set the P_FAIL bit to “1” and insert a delay before clearing the WIP bit to “0”. User has to
wait 150us before issuing another PASSULK command. This restriction makes it impractical to attempt all
combinations of a 64-bit password (such an effort would take millions of years). Monitor the WIP bit to determine
whether the device has completed the PASSULK command.

● When a valid password is provided, the PASSULK command does not insert the delay before returning the WIP
bit to zero. The SPBLKDN bit will set to “1” and the P_FAIL bit will be “0”.

● It is not possible to set the SPBLKDN bit to “1” if the password had not been set prior to the Password Protection
mode being selected.

Password Register (PASS)

Field Description
Bits Function Type Default State
Name
Non-volatile OTP storage of 64 bit password. The
Hidden password is no longer readable after the Password
63 to 0 PWD OTP FFFFFFFFFFFFFFFFh
Password Protection mode is selected by programming Lock
Register bit 2 to zero.

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Figure 101. Read Password Register (RDPASS) Sequence

CS#

0 1 2 3 4 5 6 7 8 39 40 47 48 109 110
SCLK

Command 32-bit Address 8 Dummy

SI 27h 0 0 0 0

Data Out
High-Z High-Z
SO 7 6 58 57 56
MSB

Figure 102. Read Password Register (RDPASS) Sequence (STR-OPI Mode)

CS#

≈ ≈

≈
SCLK

≈
Pre-drive
SIO[7:0]
≈

27h D8h 00h 00h 00h 00h D0 D7

Address 20 Dummy

Figure 103. Read Password Register (RDPASS) Sequence (DTR-OPI Mode)

CS#
≈

≈ ≈

SCLK
≈

DQS
≈

Pre-drive
≈

SIO[7:0] 27h D8h 00h 00h 00h 00h D1 D0 D7 D6

Address 20 Dummy

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Figure 104. Write Password Register (WRPASS) Sequence

CS#

0 1 2 3 4 5 6 7 8 39 40 102 103
SCLK

Command 32-bit Address Password

SI 28h 0 0 0 0 7 6 58 57 56

MSB

High-Z
SO

Figure 105. Write Password Register (WRPASS) Sequence (STR-OPI Mode)

CS#

≈
SCLK

≈
SIO[7:0] 28h D7h 00h 00h 00h 00h D0 D6 D7

Address Password

Figure 106. Write Password Register (WRPASS) Sequence (DTR-OPI Mode)

CS#
≈
≈

SCLK

SIO[7:0] 28h D7h 00h 00h 00h 00h D1 D0 D7 D6

Address Password

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Figure 107. Password Unlock (PASSULK) Sequence

CS#

0 1 2 3 4 5 6 7 8 39 40 102 103
SCLK

Command 32-bit Address Password

SI 29h 0 0 0 0 7 6 58 57 56

MSB

High-Z
SO

Figure 108. Password Unlock (PASSULK) (STR-OPI Mode)

CS#

≈
SCLK

≈
SIO[7:0] 29h D6h 00h 00h 00h 00h D0 D6 D7

Address Password

Figure 109. Password Unlock (PASSULK) (DTR-OPI Mode)

CS#
≈
≈

SCLK

SIO[7:0] 29h D6h 00h 00h 00h 00h D1 D0 D7 D6

Address Password

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10-27-5. Gang Block Lock/Unlock (GBLK/GBULK)

These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is a chip-based
protected or unprotected operation. It can enable or disable all DPB.

The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.

The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

10-27-6. Sector Protection States Summary Table

Protection Status
Sector State
DPB bit SPB bit
0 0 Unprotect
0 1 Protect
1 0 Protect
1 1 Protect

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10-28. Program Suspend and Erase Suspend

The Suspend instruction interrupts a Program or Erase operation to allow the device conduct other operations.

After the device has entered the suspended state, the memory array can be read except for the page being
programmed or the sector being erased.

Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend
Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase
operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.

When the Serial NOR Flash receives the Suspend instruction, Program Suspend Latency(tPSL) or Erase Suspend
latency(tESL) is required to complete suspend operation. (Refer to "Table 15. AC CHARACTERISTICS") After the
device has entered the suspended state, the WEL bit is clears to “0” and the PSB or ESB in security register is set to “1”,
then the device is ready to acceptanother command.

However, some commands can be executed without tPSL or tESL latency during the program/erase suspend, and
can be issued at any time during the Suspend.

Please refer to "Table 7. Acceptable Commands During Suspend".

Figure 110. Suspend to Read Latency

tPSL / tESL
Suspend Command Read Command
CS#

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Table 7. Acceptable Commands During Suspend

Suspend Type
Command Name Command Code
Program Suspend Erase Suspend
Commands which require tPSL/tESL delay
READ 03h/13h • •
FAST_READ 0Bh/0Ch • •
8READ ECh • •
8DTRD EEh • •
RDSFDP 5Ah • •
RDID 9Fh • •
SBL C0h • •
ENSO B1h • •
EXSO C1h • •
WREN 06h • •
RESUME 30h • •
RDLR 2Dh • •
RDSPB E2h • •
RDFBR 16h • •
RDDPB E0h • •
RDCR2 with A[31:30]=00/01 71h • •
WRCR2 with A[31:30]=00 • •
72h
WRCR2 with A[31:30]=01
Commands not required tPSL/tESL delay
WRDI 04h • •
RDSR 05h • •
RDCR 15h • •
RDCR2 with A[31:30]=10 71h • •
WRCR2 with A[31:30]=10 72h • •
RDSCUR 2Bh • •
RES ABh • •
RSTEN 66h • •
RST 99h • •
NOP 00h • •

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10-29. Program Resume and Erase Resume

The Resume instruction resumes a suspended Program or Erase operation. After the device receives the Resume
instruction, the WEL and WIP bits are set to “1” and the PSB or ESB is cleared to “0”.The program or erase
operation will continue until it is completed or until another Suspend instruction is received.

To issue another Suspend instruction, the minimum resume-to-suspend latency (tPRS or tERS) is required.
However, in order to finish the program or erase progress, a period equal to or longer than the typical timing is
required.

To issue other command except suspend instruction, a latency of the self-timed Page Program Cycle time (tPP) or
Sector Erase (tSE) is required. The WEL and WIP bits are cleared to “0” after the Program or Erase operation is
completed.

Figure 111. Resume to Read Latency

tSE / tBE / tPP

Resume Command Read Command
CS#

Figure 112. Resume to Suspend Latency

tPRS / tERS
Resume Suspend
CS# Command Command

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10-30. No Operation (NOP)

The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.

10-31. Software Reset (Reset-Enable (RSTEN) and Reset (RST))

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.

The reset time is different depending on the last operation. For details, please refer to "Table 11. Reset Timing-
(Other Operation)" for tREADY2.

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Figure 113. Software Reset Recovery

Stand-by Mode

CS# 66 99

tREADY2

Mode

Note: Refer to "Table 11. Reset Timing-(Other Operation)" for tREADY2.

Figure 114. Reset Sequence (SPI mode)

TSHSL

CS#

SCLK

Command Command

SIO0 66h 99h

Figure 115. Reset Sequence (STR-OPI mode)

TSHSL

CS#

SCLK

SIO[7:0] 66h 99h 99h 66h

Figure 116. Reset Sequence (DTR-OPI mode)

TSHSL

CS#

SCLK

SIO[7:0] 66h 99h 99h 66h

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11. Serial Flash Discoverable Parameter (SFDP)

11-1. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.

The sequence of issuing RDSFDP instruction in SPI is CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→ send 8 dummy cycles → read SFDP code on SO→to end RDSFDP operation can use
CS# to high at any time during data out.

SFDP in SPI is a JEDEC standard, JESD216D.

The sequcn of issuing RDSFDP instruction in OPI/DOPI mode:

CS# low → send RDSFDP instruction (5Ah/A5h) → send 4 address bytes on SIO pin→ send 20 dummy cycles →
read SFDP code on SIO[7:0] → to end RDSFDP operation can use CS# to high at any time during data out.

Figure 117. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

Command 24 BIT ADDRESS

SI 5Ah 23 22 21 3 2 1 0

High-Z
SO

CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK

Dummy Cycle

SI 7 6 5 4 3 2 1 0

DATA OUT 1 DATA OUT 2

SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

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Figure 118. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence (STR-OPI Mode)

CS#

≈ ≈
1 2 3 4 5 6 26 27 28
SCLK

Pre-drive
SIO[7:0] 5Ah A5h A[31:24] A[23:16] A[15:8] A[7:0] D2

≈
D0 D1

Address 20 Dummy

Figure 119. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence (DTR-OPI Mode)

CS#

1 2 3 4
≈ 23 24 25

SCLK
≈

DQS
≈

SIO[7:0]
≈

5Ah A5h A[31:24]A[23:16] A[15:8] A[7:0] D1 D0 D3 D2

Address 20 Dummy

word unit word unit

Note: Address must be low byte (A0=0) in DTR OPI.

Table 8. Signature and Parameter Identification Data Values

For SFDP register values detail, please contact local Macronix sales channel for Application Note.

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12. Data Integrity check

The data storage and transmission errors will cause unexpected Flash device variation that makes a harmful impact
on overall system functions. To prevent these errors, this product provides advanced Data Integrity Check function.
For the data storage and data transmission in the flash device, Data Integrity Check can check errors and correct
them, allowing self-checking and preventing errors in advance.

The Data Integrity Check function includes two methods:

- ECC (Error Checking and Correcting): to prevent the data storage errors
- Parity Check (CRC1): to prevent the data transmission errors

The status register data and software signals can also be used to associate the Data Integrity Check function to fully
record the results of checking, and can also immediately feedback.

12-1. ECC (Error Checking and Correcting)

Macronix Serial Octa SPI Flash have built-in ECC. The ECC algorithm uses a Hamming code that can correct a
single bit error per 16-Byte chunk. During a page program operation, the internal state machine will create the ECC
automatically. During a read operation, the internal ECC state machine corrects bit errors automatically.

It is recommended that data be programmed in multiples of 16 bytes in the predefined 16-byte chunk address
(see "Table 9. 16-Byte Chunks within a Page") using the Page Program command instead of programming a byte
or a word at a time using the Program command. However, partial program of 16-byte chunk is allowed under the
restriction that user won't program or alter the content of partially programmed chunk without erasing the sector
first.

ECC checking of a 16-Byte chunk will be disabled if double program (rewriting without erase), or rewrite a chunk
(alternating of single bit, byte, or word) happens in that chunk. Once ECC checking of a chuck is disabled, it will not
be re-activated until the sector, containing the ECC disabled chunk, is erased.

The ECC registers show detailed information for error correction activity on the device. The ECC status registers
are placed on CR2. Which include 3-bit ECC status to identify the error type, 4-bit failure chunk counter and first
failure chunk address.

The ECC register can be reset through either of the following situations:
- Write "00" data into ECC status register
- Issuing Software Reset Command
- Hardware Reset
- Power-up cycle

Table 9. 16-Byte Chunks within a Page

Chunk# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

B0 B16 B32 B48 B64 B80 B96 B112 B128 B144 B160 B176 B192 B208 B224 B240
16 Bytes
~B15 ~B31 ~B47 ~B63 ~B79 ~B95 ~B111 ~B127 ~B143 ~B159 ~B175 ~B191 ~B207 ~B223 ~B239 ~B255

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12-2. ECS# (Error corrected Signal) Pin

The ECS# pin is a real time hardware signal to feedback the ECC correction status. The ECS# pin is designed as
an open drain structure. In normal situation, the ECS# is kept on Hi-Z state. Once error correction begins, the ECS#
pin will pull low during the whole ECC chunk unit after a duration of tECSV delay timing.

The ECS# pin is default as going low when 2-bit error detection is enabled and double program detected. However,
user can select the different option for error correction by setting the ECS register in CR2 [00000400h].

Figure 120. ECS# Timing

CS#
≈

≈
SCLK

≈≈ ≈

≈≈ ≈
≈
≈

SIO[7:0]

Command Address ECC chunk (16Bytes) ECC chunk (16Bytes)

ECS#
≈

≈
Chunk with ECC error detected
tECSV

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12-3. Parity Check (CRC1)

The parity check function can only be operated at DTR OPI mode, it does not support OPI mode. The CRCEN#
bit in CR2 [address 40000000h] bit3 can enable the parity check function. CRCEN# is an OTP bit; once it is
programmed to "0", it cannot be disabled anyhow.

For write operation after the Parity check function is enabled, the CRC code needs to be set after the address
and data cycles. The starting address for the Flash device has to be issued at CRC chunk boundary, and the data
CRC bit also should be output by each CRC chunk unit. Otherwise, read CRC code might be error; and program
command would abort.

There is a bit [CR2 00000500h] that output data is CRC on both clock edges, or is CRC/CRC# on clock rising/
falling edge respectively. The CRC chunk unit is default to set as 16bytes. It can also configure the chunk unit to
32bytes, 64bytes or 128bytes by CRC register setting in CR2 [address 00000500h].

For register write, an extra DATA# cycle must be set right after data cycle as in "Figure 124. CRC Timing (Write
Register - example for 1byte data)".
For register read, an extra DATA# would be output after the data cycle as in "Figure 125. CRC Timing (Read
register - example for 1byte data)".

The address CRC byte is calculated by bitwise exclusive-OR of all the address bytes; the data CRC bytes are
calculated by bitwise exclusive-OR of all the data bytes in the CRC chunk.

Figure 121. CRC Timing (Without CRC# output)

CS#
≈

≈
SCLK
≈≈ ≈

≈≈ ≈
≈
≈

SIO[7:0] CRC CRC CRC

Command Address Multiple of CRC chunks

ECS#
≈

ECC Chunk with ECC checking fail

tECSV

Figure 122. CRC Timing (With CRC# output)

CS#
≈

SCLK
≈

≈≈ ≈

≈≈ ≈

SIO[7:0]
≈

CRC
CRC CRC# CRC CRC#

Command Address Multiple of CRC chunks

ECS#
≈

ECC Chunk with ECC checking fail

tECSV

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Figure 123. CRC Timing (Page Program)

CS#

≈
SCLK

≈≈ ≈

≈ ≈ ≈
SIO[7:0] CRC Data (16/32/64/128B) CRC Data (16/32/64/128B) CRC

Command Address

Figure 124. CRC Timing (Write Register - example for 1byte data)

CS#

SCLK

SIO[7:0] CRC Data Data#

Command Address

Figure 125. CRC Timing (Read register - example for 1byte data)

CS#

SCLK

SIO[7:0] CRC Data Data#

Command Address

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Figure 126. CRC Timing (RDPASS)

CS#

≈ ≈
SCLK

≈
DQS

≈
Pre-drive

≈ ≈
SIO[7:0] CRC D1 D0 D3 D2 D5 D4 D7 D6 FF FF FF FF FF FF FF CRC

Command Address 20 Dummy 8 Bytes 8/24/56/120 Bytes

16/32/64/128 Bytes

Figure 127. CRC Timing (WRPASS/PASSULK)

CS#

≈ ≈
SCLK

SIO[7:0] CRC D1 D0 D3 D2 D5 D4 D7 D6 FF FF FF FF
≈≈ FF FF CRC

Command Address 8 Bytes 8/24/56/120 Bytes

16/32/64/128 Bytes

Figure 128. CRC Timing (WRFBR)

CS#
≈ ≈

SCLK
≈≈

SIO[7:0] CRC D1 D0 D3 D2 FF FF FF FF FF FF CRC

Command Address 4 Bytes Data 12/28/60/124 Bytes

16/32/64/128 Bytes

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13. RESET

Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP will return to the default status as power on.
- All the volatile bits in CR2 will return to the default status as power on.
- Fastboot read will be executed on first CS# pin goes low

If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and
data could be lost. During the resetting cycle, the SIO data becomes high impedance and the current will be
reduced to minimum.

Figure 129. RESET Timing

CS#
tRHSL

SCLK

tRH tRS

RESET#

tRLRH

tREADY1 / tREADY2

Table 10. Reset Timing-(Standby)

Symbol Parameter Min. Typ. Max. Unit
tRHSL Reset# high before CS# low 10 us
tRS Reset# setup time 15 ns
tRH Reset# hold time 15 ns
tRLRH Reset# low pulse width 10 us
tREADY1 Reset Recovery time 35 us

Table 11. Reset Timing-(Other Operation)

Symbol Parameter Min. Typ. Max. Unit
tRHSL Reset# high before CS# low 10 us
tRS Reset# setup time 15 ns
tRH Reset# hold time 15 ns
tRLRH Reset# low pulse width 10 us
Reset Recovery time (During instruction decoding) 40 us
Reset Recovery time (for read operation) 40 us
Reset Recovery time (for program operation) 310 us
tREADY2 Reset Recovery time(for SE4KB operation) 12 ms
Reset Recovery time (for BE64K operation) 25 ms
Reset Recovery time (for Chip Erase operation) 100 ms
Reset Recovery time (for WRSR operation) 40 ms

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14. POWER-ON STATE

The device is at below states when power-up:

- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the ""Power-up Timing"".

Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
- To stabilize the VCCQ level, the VCCQ/VSSQ rail decoupled by a suitable capacitor close to package pins is
recommended. One VCCQ pin connect to one capacitor.
- It is recommended VCC and VCCQ power are separated system supply with same supply voltage.

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15. ELECTRICAL SPECIFICATIONS

Table 12. ABSOLUTE MAXIMUM RATINGS

RATING VALUE
Ambient Operating Temperature Industrial grade -40°C to 85°C
Storage Temperature -65°C to 150°C
Applied Input Voltage -0.5V to VCC+0.5V
Applied Output Voltage -0.5V to VCC+0.5V
VCC to Ground Potential -0.5V to 2.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.

Figure 130. Maximum Negative Overshoot Waveform Figure 131. Maximum Positive Overshoot Waveform

20ns
0V VCC+1.0V

-1.0V 2.0V
20ns

Table 13. CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Parameter Min. Typ. Max. Unit Conditions

CIN Input Capacitance 32 pF VIN = 0V
COUT Output Capacitance 32 pF VOUT = 0V

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Figure 132. DATA INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing reference level Output timing reference level

0.8VCC
0.7VCC AC
Measurement 0.5VCC
0.3VCC Level
0.2VCC

Figure 133. SCLK TIMING DEFINITION

tCLCH tCHCL
VIH (Min.)
0.5VCC
VIL (Max.)
tCH tCL

1/fSCLK

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Table 14. DC CHARACTERISTICS

Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V

Symbol Parameter Notes Min. Typ. Max. Units Test Conditions

VCC = VCC Max,
ILI Input Load Current 1 ±2 uA
VIN = VCC or GND
VCC = VCC Max,
ILO Output Leakage Current 1 ±2 uA
VOUT = VCC or GND
VIN = VCC or GND,
ISB1 VCC Standby Current 1 80 500 uA
CS# = VCC
VIN = VCC or GND,
ISB2 Deep Power-down Current 12 150 uA
CS# = VCC
100MHz 8IO STR
80 160 mA
(SIO floating)

100MHz 8IO DTR

120 180 mA
(SIO floating)
ICC1 VCC Read 1,3
133MHz 8IO STR
120 180 mA
(SIO floating)

133MHz 8IO DTR

160 220 mA
(SIO floating)
Program in Progress,
ICC2 VCC Program Current 1 30 40 mA
CS# = VCC
VCC Write Status Register Program status register in
ICC3 80 160 mA
(WRSR) Current progress, CS#=VCC
VCC Sector Erase Current Erase in Progress,
ICC4 1 20 40 mA
(SE) CS#=VCC
VCC Block Erase Current Erase in Progress,
ICC4 1 30 40 mA
(BE) CS#=VCC
Erase in Progress,
ICC5 VCC Chip Erase Current (CE) 1 80 160 mA
CS#=VCC
VIL Input Low Voltage -0.4 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage 0.2 V IOL=100uA
VOH Output High Voltage VCC-0.2 V IOH=-100uA

Notes :
1. Typical values at VCC = 1.8V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
3. VCC current only; not include VCCQ current.

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Table 15. AC CHARACTERISTICS

Temperature = -40°C to 85°C, VCC = 1.65V ~ 2.0V
Symbol Alt. Parameter Min. Typ. Max. Unit
Clock frequency for SPI commands (except Read operation) 133 MHz
fSCLK fC
Clock frequency for OPI commands 133 MHz
fRSCLK fR Clock Frequency for READ instructions 66 MHz
Clock Frequency for FAST READ 133 MHz
fTSCLK "9-3-1. Dummy Cycle and
Clock Frequency for 8READ, 8DTRD MHz
Frequency Table (MHz)"
tCH(1)
tCLH Clock High Time 0.45*T ns
tCL(1) tCL Clock Low Time 0.45*T ns
tCLCH/ Clock Rise Time / fSCLK ≤ 100MHz 0.6 V/ns
tCHCL Clock Fall Time fSCLK ≤ 133MHz 0.8 V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 4.5 ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 3 ns
From Read to next Read 10 ns
tSHSL tCSH CS# Deselect Time From Write/Erase/Program
40 ns
to Read Status Register
tDVCH tDSU Data In Setup Time (10) STR ≤ 133MHz 2 ns
tDVCH / DTR ≤ 100MHz 1
Data setup time (9) (10) ns
tDVCL DTR ≤ 133MHz 0.8
tCHDX tDH Data In Hold Time (10) STR ≤ 133MHz 2 ns
tCHDX / DTR ≤ 100MHz 1
Data hold time (9) (10) ns
tCLDX DTR ≤ 133MHz 0.8
CS# Active Hold Time (relative to
tCHSH STR 3 ns
SCLK)
tCLSH CS# active hold time DTR 3 ns
CS# Not Active Setup Time STR 3 ns
tSHCH
(relative to SCLK) DTR 3 ns
tSHQZ tDIS Output Disable Time 8 ns
tQSV Clock transient to DQS valid time Align to 30pF tCLQV ns
Loading: 10pF 6.5
tCLQV / Loading: 15pF 6.5
tV Clock transient to Output Valid ns
tCHQV Loading: 20pF 6.5
Loading: 30pF 6.5
tCLQX tHO Output Hold Time 1 ns
Loading: 10pF(10) 0.8
Loading: 15pF(10) 1.0
tDQSQ SIO valid skew related to DQS ns
Loading: 20pF(10) 1.2
Loading: 30pF(10) 1.4
min(tCL,tCH)-
tQH SIO hold time related to DQS ns
tQHS

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AC CHARACTERISTICS - continued
Symbol Alt. Parameter Min. Typ. Max. Unit
Loading: 10pF(10) 1
Loading: 15pF(10) 1.2
tQHS SIO hold skew factor ns
Loading: 20pF(10) 1.4
Loading: 30pF(10) 1.6
tECSV ECS go low time Loading: 30pF(10) 10 ns
tDP CS# High to Deep Power-down Mode 10 us
tRES1 CS# High to Standby Mode 30 us
tW Write Status/Configuration Register Cycle Time 40 ms
tW2V Write Configuration Register 2 volatile bit 40 ns
tW2N(10) Write Configuration Register 2 non-volatile bit 60 us
tPP(4) Page Program Cycle Time 0.15 0.75 ms
tSE Sector Erase Cycle Time 25 400 ms
tBE Block Erase (64KB) Cycle Time 250 2000 ms
tCE Chip Erase Cycle Time 150 300 s
tESL(6) Erase Suspend Latency 25 us
tPSL(6) Program Suspend Latency 25 us
tPRS(7) Latency between Program Resume and next Suspend 0.3 100 us
(8)
tERS Latency between Erase Resume and next Suspend 0.3 400 us
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Test condition is shown as Figure 132.
4. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to
program the whole 256 bytes or only a few bytes between 1~256 bytes.
5. By default dummy cycle value. Please refer to the "Table 1. Operating Frequency Comparison".
6. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
7. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a
period equal to or longer than the typical timing is required in order for the program operation to make progress.
8. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a
period equal to or longer than the typical timing is required in order for the erase operation to make progress.
9. tDVCH+tCHDX>1.5ns for each SIO; tDVCL+tCLDX>1.5ns for each SIO.
10. Sampled, not 100% tested.

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16. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in Figure 134 and Figure 135 are for the supply voltages and the control signals at device
power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 134. AC Timing at Device Power-Up

VCC(min)
VCC
GND tVR tSHSL

CS#
tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHCL

tCHDX tCLCH

SI MSB IN LSB IN

High Impedance
SO

Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 500000 us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
Table 15. AC CHARACTERISTICS.

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Figure 135. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

Figure 136. Power-up Timing

VCC
VCC(max)

Chip Selection is Not Allowed

VCC(min)

tVSL Device is fully accessible

VWI

time

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Figure 137. Power Up/Down and Voltage Drop

When powering down the device, VCC must drop below VPWD for at least tPWD to ensure the device will initialize
correctly during power up. Please refer to "Figure 137. Power Up/Down and Voltage Drop" and "Table 16. Power-
Up/Down Voltage and Timing" below for more details.

VCC

VCC (max.)

Chip Select is not allowed

VCC (min.)

V_keep
tVSL Full Device
Access
Allowed
VWI

VPWD (max.)

tPWD

Time

Table 16. Power-Up/Down Voltage and Timing

Symbol Parameter Min. Max. Unit
VCC voltage needed to below VPWD for ensuring initialization will
VPWD 0.8 V
occur
Voltage that a re-initialization is necessary if VDD drop
V_keep 1.5 V
below to VKEEP
tPWD The minimum duration for ensuring initialization will occur 300 us
tVSL VCC(min.) to device operation 1500 us
VCC VCC Power Supply 1.65 2.0 V
VWI Write Inhibit Voltage 1.0 1.5 V
Note: These parameters are characterized only.

16-1. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0). DEFDOPI# in CR2 depends on shipping device model.

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17. ERASE AND PROGRAMMING PERFORMANCE

Parameter Min. Typ. (1) Max. (2) Unit
Write Status Register Cycle Time 40 ms
Sector Erase Cycle Time (4KB) 25 400 ms
Block Erase Cycle Time (64KB) 250 2000 ms
Chip Erase Cycle Time 150 300 s
Page Program Time 0.15 0.75 ms
Erase/Program Cycle 100,000 cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 1.8V, and checkboard pattern.
2. Under worst conditions of minimum operation voltage and the temperature of the worst case.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.

18. DATA RETENTION

Parameter Condition Min. Max. Unit
Data retention 55˚C 20 years

19. LATCH-UP CHARACTERISTICS

Min. Max.
Input Voltage with respect to GND on all power pins 1.5 VCCmax
Input current with respect to GND on all non-power pins -100mA +100mA
Test conditions are compliant to JEDEC JDESD78 standard

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20. ORDERING INFORMATION

Please contact Macronix regional sales for the latest product selection and available form factors.

PART NO. CLOCK (MHz) TEMPERATURE PACKAGE Remark

24-Ball BGA
MX66UM2G45GXRI00 133 -40°C to 85°C
(5x5 ball array)

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21. PART NAME DESCRIPTION

MX 66 UM 2G45G XR I 00

MODEL CODE:
00: Default STR, x1 I/O enable

TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)

PACKAGE:
XR: 24-Ball BGA (5x5 ball array)

DENSITY & MODE:

2G45G: 2Gb

TYPE:
UM: 1.8V Octa I/O

DEVICE:
66: Serial NOR Flash

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22. PACKAGE INFORMATION

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23. REVISION HISTORY

Revision Descriptions Page
March 01, 2017
0.00 1. Initial Release. All

June 04, 2019

1.0 1. Removed "Advanced Information" to align with the product status ALL
2. Updated "PIN CONFIGURATIONS" (B1 & B5 information) P6
3. Modified ICC3, tW2V, tW2N and tVSL values P90,92,95
4. Modified Input Timing & OCTA Read Mode Sequence P12,41
5. Removed "Figure 133. OUTPUT LOADING" P89,92
6. Modified "Configuration Register 2" bit description P21,22
7. Added "JEDEC xSPI specification compliant" P4
8. Added SFDP content description notes P80
9. Content correction ALL

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Except for customized products which have been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.

Copyright© Macronix International Co., Ltd. 2017~2019. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit,
Macronix NBit, HybridNVM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech,
MXSMIO, Macronix vEE, RichBook, Rich TV, OctaBus, FitCAM, ArmorFlash. The names and brands of third
party referred thereto (if any) are for identification purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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