Input and Output Characteristics

of Digital Integrated Circuits at

3.3ĆV Supply Voltage

Application
Report

September 1999 Logic Products

Printed in U.S.A. SZZA010
0999
Input and Output Characteristics
of Digital Integrated Circuits
at 3.3-V Supply Voltage

SZZA010
September 1999

1
 IMPORTANT NOTICE

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Copyright  1999, Texas Instruments Incorporated

2
 Contents
Title Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Series Damping Resistors (SN74XXX2xxx, SN74XXXR2xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Automatic High-Impedance State (Auto3-state) Output of the ALVT Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Bergeron Method Applied to the SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Voltage Value at the Output of the Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Voltage Value at End of the Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Abbreviations and Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Documents Published by TI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 Internet Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

List of Illustrations
Figure Title Page
1 Input Characteristic of the SN74AHCxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Input Characteristic of the SN74ACxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Input Characteristic of the SN74LVxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Input Characteristic of the SN74LVCxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Input Characteristic of the SN74ALVCxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Input Characteristic of the SN74ALBxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Input Characteristic of the SN74LVTHxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Input Characteristic of the SN74ALVTHxxx Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Simplified Output Stage of ALVT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Output Characteristics of the SN74AHC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
11 Output Characteristics of the SN74AHC240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Output Characteristics of the SN74AC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Output Characteristics of the SN74AC240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
14 Output Characteristics of the SN74LV00A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
15 Output Characteristics of the SN74LV240A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

iii
 List of Illustrations (Continued)
Figure Title Page
16 Output Characteristics of the SN74LVC00A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
17 Output Characteristics of the SN74LVC240A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
18 Output Characteristics of the SN74ALVCH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
19 Output Characteristics of the SN74LVTH240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
20 Output Characteristics of the SN74ALB16244A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
21 Output Characteristics of the SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
22 Measurement Setup for the Bergeron Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
23 Bergeron Diagram for the SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
24 Diagram of Line Reflections for the SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
25 Signal Shape of the SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
26 Output Waveforms of the SN74AHC240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
27 Output Waveforms of the SN74AC240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
28 Output Waveforms of the SN74LV00A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
29 Output Waveforms of the SN74LV240A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
30 Output Waveforms of the SN74LVC244A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
31 Output Waveforms of the SN74ALVC16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
32 Output Waveforms of the SN74ALB16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
33 Output Waveforms of the SN74LVTH240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
34 Output Waveforms of the SN74ALVTH16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

iv
 Abstract
This application report contains a comprehensive collection of the input- and output-characteristic curves of integrated circuits
from various 3.3-V logic families. These curves go beyond the information given in data sheets by providing additional details
regarding the characteristics of the components. This knowledge is particularly useful when, for example, a decision must be
made as to which circuit should be used in a bus system, or when the waveforms that can be expected in a transmission system
must be predicted using a Bergeron chart. These oscillograms are of great assistance when generating models for simulation
programs that analyze the dynamic behavior of the integrated circuits in a particular environment.

1 Introduction
The parameters given in the data sheets of integrated circuits can give only a very limited indication of their behavior in a
system. Generally, data sheets give only information regarding the behavior over the input and output (I/O) voltage range of
0 to 3.3 V. Even the output currents specified over this range provide an incomplete picture of in-system performance.
Behavior of integrated circuits outside the usually accepted operating conditions often is of interest. This is, for example, the
situation when the characteristic curves need to be used to predict the signal waveforms resulting from line reflections.
Along with the I/O characteristics, use of the Bergeron method, and knowledge of the load resistor, the amplitude of the line
reflections can be determined.
Many modern logic families are specified at different voltage nodes, for example the AHC logic, and can be used at 5-V, 3.3-V,
or even at 2.5-V supply voltage.
Since three main voltage nodes currently are used, it is necessary to provide I/O-characteristics at these different voltage levels.
This report deals exclusively with devices operated at 3.3-V supply voltage.
Two other application reports regarding this topic are available:
• Input and Output Characteristics of Digital Integrated Circuits at 5-V Supply Voltage, literature number
SZZA008
• Input and Output Characteristics of Digital Integrated Circuits at 2.5-V Supply Voltage, literature number
SZZA012
In view of the wide range of integrated circuits that are available, it has been necessary to limit this information to typical
characteristics only. In the second and third sections of this application report, the input and output characteristics of the
following circuits have been shown as being representative of other components that behave similarly in circuit:

’00 The characteristic curves of this NAND gate are given as representative of all logic circuits having normal
drive capability, such as gates, flip-flops, counters, multiplexers, etc.

’240/’244 The output characteristics of these bus-interface circuits are of particular importance when a decision must
be made as to which circuit family should be used for a specific system requirement. The available output
current has a decisive influence on the distortion of signals on bus lines.

’16240/’16244 The output characteristics of these bus-interface devices correspond with the ’240/’244 functions regarding
the electrical behavior. However, these devices support 16 drivers within one package. This meets the market
requirements, because modern designs are based on wider buses, using 16 bits, 32 bits, or more bits on the
backplanes. Further, the noise behavior of the Widebus shows a significant improvement versus the
standard octal packages.

Widebus is a trademark of Texas Instruments Incorporated.

1
Representatives of the different logic families (see Table 1) give an overview of the input and output characteristics, which
are presented in sections 2 and 3.
Table 1. Representatives of the Different Logic Families
TYPE
FAMILY
’00 ’240/’244 ’16244
SN74AHC √ √
SN74AC √ √
SN74LV √ √
SN74LVC √ √
SN74ALVC √
SN74ALB √
SN74ALVT √
SN74LVT √

Because the input characteristics depend exclusively on the technology used, not on the logical function of the device, only
one representative per logic family is shown (gate function ’00 or driver function ’240) in the input-characteristics section.
Section 4 of this application report presents the calculation of line reflections using the Bergeron method. The calculation is
done with the SN74ALVTH16244.
Measurement results demonstrating different switching behaviors of the various logic families are given in Section 5. For these
measurements, the devices under test were loaded with a 1.3-m-long coaxial cable having a characteristic impedance of 50 Ω;
the end of the line was not connected, i.e., open circuit. These waveforms provide good insight into the dynamic behavior of
the devices.

2
 2 Input Characteristics
The high impedance of the input stage of the logic circuit determines the input characteristics of logic circuits in the positive
range.
In contrast to the 5-V logic families, all of the 3.3-V families have CMOS input stages. The technologies used are based on
the CMOS or the BiCMOS manufacturing process. In both cases, CMOS input stages are used. CMOS input stages are
controlled exclusively by the applied voltage, so there is no current flowing into the input stage. Therefore, the input impedance
of CMOS and BiCMOS devices is in the megaohm range. Negative voltage peaks are limited by a protection diode.
The input stages of some CMOS and BiCMOS logic families (SN74AC, SN74ALB) also have an input protection diode
connected to VCC. This diode limits the positive input voltage to maximum VCC + 0.7 V, but prohibits their use in mixed-voltage
systems.
The bus-hold circuit represents a special input circuit that is implemented in the input stages of the LVT and ALVT logic
families and is optionally available for the LVC and ALVC family devices.
Inputs of components that have the bus-hold circuit hold the last valid logic state. This feature is suitable in the case where an
input stays undefined, e.g., during a high-impedance state on the bus. Using the bus-hold circuit eliminates the need for pullup
or pulldown resistors.
Devices with the bus-hold circuit are designated by the ‘H’ in their part numbers, for example, SN74LVTH245.
A more detailed application report, Bus-Hold Circuits, literature number SDZAE15, is available from Texas Instruments
(TI).
A list of application reports and other literature is given in Section 7.
7V

6V

SN74AHC00
5V

4V
Input Voltage

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 1. Input Characteristic of the SN74AHCxxx Series

TI is a trademark of Texas Instruments Incorporated.

3
 7V

6V

SN74AC00
5V

4V
Input Voltage

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 2. Input Characteristic of the SN74ACxxx Series

7V

6V

SN74LV00A
5V

4V
Input Voltage

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 3. Input Characteristic of the SN74LVxxx Series

4
 9V

8V
SN74LVC244A
7V

6V

5V
Input Voltage

4V

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 4. Input Characteristic of the SN74LVCxxx Series

9V

8V
SN74ALVCH16244
7V

6V

5V
Input Voltage

4V

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 5. Input Characteristic of the SN74ALVCxxx Series

5
 7V

6V

SN74ALB16244A
5V

4V
Input Voltage

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 6. Input Characteristic of the SN74ALBxxx Series

7V

6V

SN74LVTH240
5V

4V
Input Voltage

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 7. Input Characteristic of the SN74LVTHxxx Series

6
 7V

6V

SN74ALVTH16244
5V

4V
Input Voltage

3V

2V

1V

0V

–1 V

–2 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 8. Input Characteristic of the SN74ALVTHxxx Series

7
 3 Output Characteristics
The output stage of a logic circuit in the high-impedance state behaves like a voltage source with an open-circuit voltage of
VCC for CMOS logic and low voltage for BiCMOS logic. The internal resistance for the high-impedance state is inversely
proportional to the drive capability of the device. The value of the internal resistance for the standard logic families is in the
range of 30 Ω to 40 Ω.
In the low state for positive voltages, the output resistance is based on the internal resistance of the conducting transistor, i.e.,
collector-emitter for BiCMOS technologies and drain-source resistance for CMOS technologies. Negative voltage peaks are
limited by a protection diode. The output stages of some CMOS logic families (SN74AHC, SN74AC) also have an output
protection diode, which is connected to VCC. This diode limits the positive output voltage to maximum VCC + 0.7 V.

3.1 Series Damping Resistors (SN74XXX2xxx, SN74XXXR2xxx)

In the LVC, ALVC, LVT and ALVT families, TI offers driver options with integrated series resistors of about 25 Ω.
Using the damping resistors at the output stage, the effective output impedance of the driver is about 50 Ω. If the value of the
line impedance also is about 50 Ω, no line reflections are observed at the output of the device. In this case, the beginning of
the line is terminated perfectly. This option is especially beneficial for memory applications in which overshoots and
undershoots might cause a malfunction. In point-to-point applications, nearly ideal signal shapes can be achieved. The “2” in
the device part number indicates the presence of a series damping resistor. The “R” in combination with the “2” indicates series
damping resistors on both ports of bidirectional devices, for example, the SN74LVC2245A and LVTH162374.
Further information about series damping resistors is given in the TI application report, Bus-Interface Devices With Output
Damping Resistors or Reduced-Drive Outputs, literature number SCBA012.
A list of available application reports and other literature is in Section 7.

3.2 Automatic High-Impedance State (Auto3-state) Output of the ALVT Family

The auto3-state function, which is implemented in the output stages of the ALVT family, represents a specialty. The principle
is shown in Figure 9.
VCC

OE
Output Control

DATA
OUTPUT
+

SENSE

Figure 9. Simplified Output Stage of ALVT Devices

Assume that the output is in the active-high state and a comparator monitors the voltage at the output and compares it with the
supply voltage. If the voltage that is applied externally to the output exceeds the supply voltage, the output stage is switched
to the high-impedance-state. In this case, the logic levels applied to the data and control input pins of the device are irrelevant.
A current of about 30 mA is needed to trigger the auto3-state circuit, such that bus contentions are prevented, but switching
noise does not trigger the protective circuit. However, this also implies that the auto3-state cannot be implemented by using
a simple pullup resistor.
Current can flow into the output only in the case of an active high. If the output is set to high impedance by the OE control
pin, no current flows.

8
The series opposed Schottky diodes always connect the back gate of the pullup transistor of the output stage to the higher
voltage that is either VCC or the voltage that can be applied externally to the output. In this way, current flow from the output
to VCC is suppressed.
7V

6V

SN74AHC00
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 10. Output Characteristics of the SN74AHC00

7V

6V

SN74AHC240
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 11. Output Characteristics of the SN74AHC240

9
 7V

6V

SN74AC00
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 12. Output Characteristics of the SN74AC00

7V

6V

SN74AC240
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 13. Output Characteristics of the SN74AC240

10
 7V

6V

SN74LV00A
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 14. Output Characteristics of the SN74LV00A

7V

6V

SN74LV240A
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 15. Output Characteristics of the SN74LV240A

11
 7V

6V

SN74LVC00A
5V

4V
Output Voltage

3V

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 16. Output Characteristics of the SN74LVC00A

7V

6V

SN74LVC240A
5V

4V
Output Voltage

3V

2V

1V

0V

–1 V

–2 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 17. Output Characteristics of the SN74LVC240A

12
 7V

6V

SN74ALVCH16240
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 18. Output Characteristics of the SN74ALVCH16240

7V

6V

SN74LVTH240
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 19. Output Characteristics of the SN74LVTH240

13
 7V

6V

SN74ALB16244A
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 20. Output Characteristics of the SN74ALB16244A

7V

6V

SN74ALVTH16244
5V

4V

3V
Output Voltage

2V

1V

0V

–1 V

–2 V

–3 V
–200 mA –160 mA –120 mA –80 mA –40 mA 0 mA 40 mA 80 mA 120 mA 160 mA 200 mA
Output Current

Figure 21. Output Characteristics of the SN74ALVTH16244

14
 4 Bergeron Method Applied to the SN74ALVTH16244
The input and output characteristics, shown in Sections 2 and 3, can be used to determine the signal reflections within a certain
application by using a graphical procedure known as the Bergeron method.
The prerequisite for the use of the Bergeron method is that the lines exceed a certain length:
If the rise time or the fall time of a signal is shorter than twice the propagation delay on the line, the line theory must
be applied.
Practically, for a line with a signal propagation of 5 ns/m and a signal with a rising or falling edge of 2 ns, starting with a line
length that exceeds 20 cm [2 ns / (5 ns/m × 2)], the line theory must be applied.
For a bus line, the signal propagation delay increases to 25 ns/m, so that, in this case, the line theory has to be applied for a
line length that exceeds 4 cm [2 ns / (25 ns/m × 2)].
The SN74ALVTH16244 device was tested, using the measurement setup shown in Figure 22. The Bergeron method was used
to determine the signal shape in advance.

Measurement Point Measurement Point Measurement Point

“Input” “Output” “End of Cable”

Z = 50 Ω

L = 130 cm

Figure 22. Measurement Setup for the Bergeron Method

The first step in the graphical solution using the Bergeron method is to draw the following characteristics in a
voltage-versus-current diagram:
• Output characteristics of the SN74ALVTH16244 device
• Load characteristic at the end of the line
The output characteristics are taken directly from Figure 21. The load characteristic equals the Y-axis for the investigated case
because no resistor is connected to the end of the line (RL = ∞).
The intersection between the load characteristic and the output characteristic represents the steady states, the current and
voltage values at the line start, and the end of the line at the time t < 0, respectively.

4.1 Voltage Value at the Output of the Driver

For the low-to-high transition, draw a straight line, starting at the intersection of the output-low characteristic and the load
characteristic. For the high-to-low transition, start the straight line at the cross point of output-high characteristic and the load
characteristic.
The line impedance, ZO, determines the steepness of this line. In the example, the line impedance is 50 Ω.
The intersection of this straight line and the output characteristics equals the voltage and current values at the beginning of the
line at the time τ = 0.

15
 4.2 Voltage Value at End of the Line
Now, a straight line with the steepness –ZO is drawn through this point. The intersection between this line and the load
characteristics results in the voltage values at the end of the line after one propagation delay time of the line, that is after τ = 1.
Afterward, the procedure is repeated, applying straight lines to the output characteristics and the load characteristics.
The steepness of the straight line is:
• –ZO from the output characteristics to the load characteristics
• ZO from the load characteristic to the output characteristics
In this way, current and voltage values are obtained:
• at the end of the line, at the times τ = 1, 3, 5 . . .
• at the line start, at the times τ = 2, 4, 6 . . .
The Bergeron diagram is shown in Figure 23. The related diagram (see Figure 24) shows the line reflections.
The precalculated values using the Bergeron procedure match very well with the measured signal shapes. Another TI
application report, The Bergeron Method: A Graphic Method for Determining Line Reflections in Transient Phenomena,
literature number SDYA014, describes the graphic procedure in more detail

7V

6V τ =2
low to high
SN74ALVTH16244
5V

4V τ =3
low to high
τ =1
3V low to high
Input Voltage

2V τ =4
low to high

1V τ =1 τ =4
high to low high to low

0V τ =3
high to low

–1 V

–2 V
τ =2
high to low
–3 V
–100 mA –80 mA –60 mA –40 mA –20 mA 0 mA 20 mA 40 mA 60 mA 80 mA 100 mA
Input Current

Figure 23. Bergeron Diagram for the SN74ALVTH16244

16
6V

4V
Output

2V

End of Cable
0V

–2 V

–4 V
τ=0 τ=1 τ=2 τ=3 τ=4 τ=5 τ=6 τ=7 τ=8

Line Start,L > H End of Line, L > H

6V

End of Cable
4V

2V

0V

–2 V
Output

–4 V
τ=0 τ=1 τ=2 τ=3 τ=4 τ=5 τ=6 τ=7 τ=8

Line Start, H > L End of Line, H > L

Figure 24. Diagram of Line Reflections for the SN74ALVTH16244

17
 7V
τ =0 τ =2 τ =4
6V high to low high to low high to low

τ =1 τ =3 τ =5
5V high to low high to low high to low

4V

3V

2V

1V

0V

–1 V τ =1 τ =3 τ =5 τ =7
low to high low to high low to high low to high
τ =0 τ =2 τ =4 τ =6
–2 V low to high low to high low to high low to high

–3 V
SN74ALVTH16244
–4 V

–5 V
10 ns 30 ns 50 ns 70 ns 90 ns 110 ns 130 ns 150 ns 170 ns

Figure 25. Signal Shape of the SN74ALVTH16244

18
 5 Output Waveforms
The following measurements demonstrate the voltage waveforms of typical output stages. The measurement setup is shown
in Figure 22.
For these measurements, the devices under test were loaded with a 1.3-m coaxial cable having a characteristic impedance of
50 Ω; the end of the line was not connected, i.e., open circuit.
These waveforms provide good insight into the dynamic behavior of the devices. In particular, the oscillograms provide
information regarding drive capability with a low-resistance load, together with an indication of the line reflections that can
be expected.

7V

6V

Input End of Cable

5V

4V Output

3V

2V

1V

0V

–1 V

–2 V

–3 V
SN74AHC240
–4 V

–5 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 26. Output Waveforms of the SN74AHC240

19
 7V

6V
End of Cable
5V

4V Input

3V

2V

1V Output

0V

–1 V

–2 V

–3 V
SN74AC240
–4 V

–5 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 27. Output Waveforms of the SN74AC240

5V

4V
Output End of Cable

3V

2V
Input

1V

0V

–1 V
SN74LV00A
–2 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 28. Output Waveforms of the SN74LV00A

20
7V

6V

Output End of Cable

5V

4V

3V

2V

1V Input

0V

–1 V

–2 V

–3 V
SN74LV240A
–4 V

–5 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 29. Output Waveforms of the SN74LV240A

7V

6V
End of Cable
5V
Input
Output
4V

3V

2V

1V

0V

–1 V

–2 V

–3 V
SN74LVC244A
–4 V

–5 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 30. Output Waveforms of the SN74LVC244A

21
 7V

6V

5V Output

4V

3V

2V
Input
1V

0V

–1 V
End of Cable
–2 V

–3 V
SN74ALVC16244
–4 V

–5 V
0 ns 25 ns 50 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns

Figure 31. Output Waveforms of the SN74ALVC16244

7V

6V
End of Cable
5V

4V

3V

2V
Input

Output
1V

0V

–1 V

–2 V

–3 V
SN74ALB16244
–4 V

–5 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 32. Output Waveforms of the SN74ALB16244

22
7V

6V
Output
5V

4V Input

3V

2V

1V End of Cable

0V

–1 V

–2 V

–3 V
SN74LVTH240
–4 V

–5 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 33. Output Waveforms of the SN74LVTH240

7V

6V
End of Cable
5V

4V Output

3V

2V
Input

1V

0V

–1 V

–2 V

–3 V
SN74ALVTH16244
–4 V

–5 V
0 ns 20 ns 40 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 180 ns 200 ns

Figure 34. Output Waveforms of the SN74ALVTH16244

23
 6 Abbreviations and Glossary

5-V tolerance Logic devices with 5-V tolerance allow 5-V CMOS logic levels at their inputs and outputs in the
high-impedance state.

A
Auto3-state Devices tolerate a higher voltage level at the outputs during active high state at the output. Also called
overvoltage protection.

SN74ALVC Advanced Low-Voltage CMOS devices

SN74ALVT Advanced Low-Voltage Technology devices

SN74AC Advanced CMOS devices

SN74AHC Advanced High-speed CMOS devices

B
BiCMOS Combination of bipolar and CMOS processes (CMOS input structure, bipolar output structure)

G
GND Ground

I
I/O Input/Output

L
SN74LV Low-Voltage CMOS devices, originally designed for VCC = 3.3 V; also specified at 5 V

SN74LVC Low-Voltage CMOS devices

SN74LVT Low-Voltage Technology devices with overvoltage protection (see auto3-state)

R
RL Load resistor

S
SN74S Schottky devices

SPICE Simulation Program with Integrated Circuit Emphasis

24
 T
TTL level Transistor-Transistor Logic level

V
VCC Supply voltage

25
 7 References

7.1 Documents Published by TI

ABT Logic Advanced BiCMOS Technology, Data Book, 1998, literature number SCBD002C.
Advanced CMOS Logic, Data Book, 1996, literature number SCADE02.
Logic Selection Guide and Data Book, CD-ROM, April 1998, literature number SCBC001B.
AHC/AHCT Logic Advanced High-Speed CMOS, Data Book, 1997, literature number SCLD003A.
Design Considerations for Logic Products, Application Book, 1997, literature number SDYA002.
Digital Design Seminar, Reference Manual, 1998, literature number SDYDE01B.
Designing With Logic, March 1997, literature number SDYA009.
The Bergeron Method: A Graphic Method for Determining Line Reflections in Transient Phenomena, October 1996, literature
number SDYA014.
Bus-Interface Devices With Output Damping Resistors or Reduced Drive Outputs, August 1997, literature number
SCBA012A.
Live Insertion, October 1996, literature number SDYA012.
Thin Very Small-Outline Package (TVSOP), March 1997, literature number SCBA009C.
Low-Voltage Logic Families, April 1997, literature number SCVAE01A.
Bus-Hold Circuit, July 1992, literature number SDZAE15.
Electromagnetic Emission from Logic Circuits, November 1998, literature number SZZA007.
PCB Design Guidelines for Reduced EMI, November 1998, literature number SZZA009.
Input and Output Characteristics of Digital Integrated Circuits at 2.5-V Supply Voltage, literature number SZZA012.
Input and Output Characteristics of Digital Integrated Circuits at 5-V Supply Voltage, literature number SZZA008.

7.2 Internet Information Sources

TI Semiconductor Home Page
http://www.ti.com/sc

TI Distributors
http://www.ti.com/sc/docs/distmenu.htm

TI Logic Home Page

http://www.ti.com/sc/docs/asl/home.htm

TI Logic Literature
http://www.ti.com/sc/docs/asl/lit/lit.htm

TI Product Information and Document Search

http://www.ti.com/sc/docs/msp/download.htm

8 Acknowledgment
The author of this document is Peter Forstner. Revisions were made by Johannes Huchzermeier.

26