TLF35584

Multi Voltage Safety Micro Processor Supply

TLF35584QVVS1
TLF35584QVVS2
TLF35584QKVS1
TLF35584QKVS2

Data Sheet
Rev. 2.0, 2017-03-16

Automotive Power
 TLF35584

Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Pin Assignment - PG-VQFN-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
....8
3.2 Pin Definitions and Functions - PG-VQFN-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
....8
3.3 Pin Assignment - PG-LQFP-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 13 3.4 Pin Definitions and Functions - PG-LQFP-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 13
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 19
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 22
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 23
4.4 Quiescent Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 24 4.4.1 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 25
5 Wake Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 26
5.2 Electrical Characteristics Enable Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 27 5.3 Electrical Characteristics Wake Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 28
5.4 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Pre Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 30
6.2 Step Up Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 31
6.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 31 6.2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3 Step Down Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 33
6.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 33
6.3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 34
6.3.3 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 36
6.4 Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 39

Data Sheet 2 Rev. 2.0, 2017-03-16

 TLF35584

6.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 39
6.4.2 Electrical characteristics frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 39
6.4.3 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 40
7 Post Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 41
7.2 µ-Processor Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 43 7.2.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 43
7.2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 45
7.2.3 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 46
7.3 Communication Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 49
7.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 49
7.3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 51
7.3.3 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 52
7.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 53
7.4.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 53
7.4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 54
7.4.3 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 55
7.5 Tracker 1 & 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 56
7.5.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 56
7.5.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 57
7.5.3 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 58
7.6 External Post Regulator for Core Supply (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 59
7.7 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 62
7.7.1 Power sequencing from POR to INIT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 62
7.7.2 Power sequencing STANDBY to INIT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 64 7.7.3 Power sequencing SLEEP to WAKE state . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Data Sheet 3 Rev. 2.0, 2017-03-16

 TLF35584

8 Monitoring Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 66
8.2 Shutdown Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 67
8.3 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 67
8.4 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 71 8.5 Electrical Characteristics Voltage Monitoring and Reset Function . . . . . . . . . . . . . .
. . . . . . . . . . . . . 73
9 Standby LDO and Internal Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.1 Standby LDO: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 77
9.1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 77
9.1.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 78
9.1.3 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 80 9.2 Internal Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10 Wake Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 84 10.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 85
11 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 86
11.2 Description of States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 88
11.2.1 POWERDOWN-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 88
11.2.2 INIT-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 89
11.2.3 NORMAL -state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 91
11.2.4 STANDBY-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 92
11.2.5 SLEEP-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 93 11.2.6 WAKE-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.2.7 FAILSAFE-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.3 Transition Between States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 97
11.3.1 POWERDOWN -> INIT-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 97
11.3.2 INIT -> NORMAL-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 98
11.3.3 Movements between NORMAL and SLEEP state . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 100

Data Sheet 4 Rev. 2.0, 2017-03-16

 TLF35584

11.3.3.1 NORMAL -> SLEEP-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . 100
11.3.3.2 SLEEP -> WAKE-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 103
11.3.3.3 WAKE -> SLEEP state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 105
11.3.4 Movements between NORMAL and STANDBY state . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 107
11.3.4.1 NORMAL -> STANDBY-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 107
11.3.4.2 STANDBY -> INIT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 110
11.3.4.3 INIT -> NORMAL state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 111
11.3.5 NORMAL -> WAKE state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 112
11.3.6 WAKE -> NORMAL-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 112
11.3.7 WAKE -> STANDBY state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 114
11.3.8 FAILSAFE -> INIT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 117
11.4 Reaction on detected faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 119
11.4.1 Stay in current State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 119

11.4.2 Transition into INIT State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . 120
11.4.2.1 INIT -> INIT state due to detected fault . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 121
11.4.2.2 NORMAL -> INIT state due to detected fault . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 123
11.4.2.3 STANDBY -> INIT state due to detected fault . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 124
11.4.2.4 SLEEP -> INIT state due to detected fault . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 125
11.4.2.5 WAKE -> INIT state due to detected fault . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 126
11.4.3 Transition into FAILSAFE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 127
11.4.3.1 INIT -> FAILSAFE state due to detected fault . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 128
11.4.3.2 XXXX -> INIT -> FAILSAFE state due to detected fault . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 129
11.4.3.3 NORMAL -> FAILSAFE state due to detected fault . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 130
11.4.3.4 STANDBY -> FAILSAFE state due to detected fault . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 131

Data Sheet 5 Rev. 2.0, 2017-03-16

 TLF35584

11.4.3.5 SLEEP -> FAILSAFE state due to Fault . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . 132
11.4.3.6 WAKE -> FAILSAFE state due to detected fault . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 133
11.4.3.7 Transition into FAILSAFE state due to thermal shutdown . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 134
11.4.4 Transition into POWERDOWN-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 135
11.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 136
11.6 Built In Self Test (BIST) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 138
11.6.1 Analog Built In Self Test (ABIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 138
11.6.1.1 How to run the ABIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 139
11.6.1.2 Testing the comparator logic only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 141
11.6.1.3 Testing the comparator logic and the corresponding deglitching logic . . . .
. . . . . . . . . . . . . . . 142
11.6.1.4 Testing the complete monitoring chain (comparators, deglitching and
output) . . . . . . . . . . . . . 144
11.6.1.5 Abort conditions for ABIST operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 145
11.6.2 Logic Built In Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 146 11.7 Microcontroller Programming Support . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12 Safe State Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 148
12.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 151
12.3 Reaction On Microprocessor Safety Management Unit (SMU - Pin ERR): . . . . . . . . . . . . . . . . .
. . 153
12.3.1 Immediate reaction on ERR monitoring failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 153
12.3.2 Recovery delay reaction on ERR monitoring failure . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 155
12.4 Reaction On Error Triggered State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 158
12.5 Reaction On Window Watchdog Output (WWO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 159
12.6 Reaction On Functional Watchdog Output (FWO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 160 12.7 Reaction On Thermal Shutdown (TSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 161
13 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 162
13.2 SPI Write Access To Protected Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 165

Data Sheet 6 Rev. 2.0, 2017-03-16

 TLF35584

13.3 SPI Write Initiated State Transition Request And Regulator Configuration . . . . . . . . . . . . . . . . .
. . 166
13.4 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 167
13.4.1 Device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 169
13.4.2 Buck registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 214 13.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
15 Window Watchdog And Functional Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 222
15.2 Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 223
15.2.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 226
15.2.1.1 Normal operation: Correct triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 226
15.2.1.2 Fault operation: No trigger in open window after initialization . . . . . . . . . . .
. . . . . . . . . . . . . . . 227
15.2.1.3 Fault operation: No trigger in Open Window in steady state . . . . . . . . . . . .
. . . . . . . . . . . . . . . 228
15.2.1.4 Fault operation: False trigger in Closed Window after initialization . . . . . . .
. . . . . . . . . . . . . . . 229
15.2.1.5 Fault operation: False trigger in Closed Window in steady state . . . . . . . .
. . . . . . . . . . . . . . . . 230
15.2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 231
15.3 Functional Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 232
15.3.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 235
15.3.1.1 Normal operation: Correct triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 235
15.3.1.2 Fault operation: Synchronization is missing . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 236
15.3.1.3 Fault operation: Answer is wrong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 237
15.3.1.4 Fault operation: Missing response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 238 16 Application Information . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17 Package
Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 241 18 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Data Sheet 7 Rev. 2.0, 2017-03-16

 TLF35584

Data Sheet 8 Rev. 2.0, 2017-03-16

Multi Voltage Safety Micro Processor Supply TLF35584

1 Overview

Features
• High efficient multi voltage power supply chip
• Serial step up and step down pre regulator for wide input voltage
range from 3.0 to 40 V with full performance and low over all power
loss
• Low drop post regulator 5.0V/200mA for communication supply
(named LDO_Com) PG-VQFN-48
• Low drop post regulator 5.0 V/600 mA (TLF35584xxVS1) or
3.3 V/600 mA (TLF35584xxVS2) for µC supply (named LDO_µC)
• Provides enable, sync out signal and voltage monitoring (inside
device to be added to reset function) for an optional external post
regulator for core supply
• Voltage reference 5.0 V +/- 1% for ADC supply, 150 mA current
capability (named Volt_Ref)
• Two trackers for sensor supply following voltage reference 150 mA
current capability each (named Tracker 1 and Tracker 2)
• Standby regulator 5.0 V/10 mA (TLF35584xxVS1) or 3.3 V/10 mA
(TLF35584xxVS2) (named LDO_Stby) PG-LQFP-64
• Independent voltage monitoring block with reset function
• Configurable functional and window watchdog
• 16-bit SPI
• Safe state control with two safe state signals with programmable delay
• Input voltage monitoring (over voltage switch off)
• Green Product (RoHS compliant)
• ISO26262 compliant
• AEC Qualified

Type Package Marking (Line1 / Line2)

TLF35584QVVS1 (5.0 V Variant) PG-VQFN-48 35584 / VS1

TLF35584QVVS2 (3.3 V Variant) PG-VQFN-48 35584 / VS2

TLF35584QKVS1 (5.0 V Variant) PG-LQFP-64 TLF35584 / QK VS1

TLF35584QKVS2 (3.3 V Variant) PG-LQFP-64 TLF35584 / QK VS2

Data Sheet 9 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration
Block Diagram

2 Block Diagram

Figure 1 Block Diagram

Data Sheet 10 Rev. 2.0, 2017-03-16

 TLF35584

3 Pin Configuration

3.1 Pin Assignment - PG-VQFN-48

Figure 2 Pin Configuration - PG-VQFN-48

3.2 Pin Definitions and Functions - PG-VQFN-48

Pin Symbol Function

1 BSG Boost driver ground:

Connect this pin to ground at the low side of an external current sense resistor to
decouple the driver noise from the sensitive ground. If step up pre regulator option
is not used, connect to ground.

2 VST Supply voltage standby regulator, input:

Connect this input to supply (battery) voltage with reverse protection diode and
capacitor between pin and ground. An EMC filter is recommended.

3 ENA Enable Input:

A positive edge signal at this pin will wake the device. In case of not used connect
to ground.

4 WAK Wake/Inhibit Input:

A high level signal of defined length at this pin will wake the device. In case of not
used, connect to ground.

Data Sheet 11 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

Pin Symbol Function

5 QST Output standby LDO:
Connect a capacitor as close as possible to pin.
6 AG1 Analogue ground, pin 1:
Connect this pin directly (low ohmic and low inductive) to ground.
7 AG2 Analogue ground, pin 2:
Connect this pin directly (low ohmic and low inductive) to ground.
8 AGS1 Analogue ground, safety, pin 1:
Connect this pin directly (low ohmic and low inductive) to ground.
In case a safety switch is used, connect directly to the source of the NMOS used.
9 AGS2 Analogue ground, safety, pin 2:
Connect this pin directly (low ohmic and low inductive) to ground.
In case a safety switch is used, connect directly to the source of the NMOS used.
10 SS2 Safe state signal 2:
Safe state output signal 2, sets the application into a safe state. Signal is delayed
against SS1, delay can be adjusted via SPI command.
11 SS1 Safe state signal 1:
Safe state output signal 1, sets the application into a safe state.
12 SDI Serial peripheral interface, signal data input:
SPI signalling port, connect to SPI port “data output” of micro processor to receive
commands during SPI communication.
13 SDO Serial peripheral interface, signal data output:
SPI signalling port, connect to SPI port “data input” of micro processor to send
status information during SPI communication.
14 SCL Serial peripheral interface, signal clock:
SPI signalling port, connect to SPI port “clock” of micro processor to clock the
device for SPI communication.
15 SCS Serial peripheral interface, signal chip select:
SPI signalling port, connect to SPI port “chip select” of micro processor to address
the device for SPI communication.
16 WDI Watchdog input, trigger signal:
Input for trigger signal, connect the “trigger signal output” of the micro processor
to this pin. In case of not used, leave open (internal pull-down).
17 ROT Reset output:
Open drain structure with internal pull-up current source. A low signal at this pin
indicates a reset event.
18 INT Interrupt signal:
Push-pull-stage. A low pulse at this pin indicates an interrupt, the micro processor
shall read out the SPI status registers. Connect to a non maskable interrupt port
(NMI) of the micro processor core supply voltage.

Data Sheet 12 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

19 SYN Synchronization output signal:

Connect this output to the optional external switch mode post regulator
synchronization input. The signal delivers the step down regulator switching
frequency either in phase or shifted by 180° (selectable via SPI command). The
switch mode post regulator shall synchronize to the rising edge. If not used, leave
open.

Pin Symbol Function

20 ERR Error signal input:
Input for error signal from micro processor safety managing unit (SMU, internal
failure detection of the micro processor). Connect the “error signal output” of the
micro processor to this pin.
21 EVC Enable external post regulator for core supply:
Connect this pin to the enable input of the external post regulator. If not used,
leave open.
22 MPS Microcontroller programming support pin:
Pull down this pin to ground for operation. Optionally, this pin can be used for
microcontroller debugging and programming purposes. For details please refer to
Chapter 11.7.
23 SEC Configuration pin for external post regulator for core supply:
Connect this pin to ground if the option external post regulator is not used. If the
option external post regulator is used, leave open.
24 FRE Frequency adjustment pin:
Connect pin to ground for low frequency range or leave open for high frequency
range.
25 STU Configuration pin for step up converter:
Connect this pin to ground if the option step up pre regulator is not used. If the
option step up pre regulator is used, leave open.
26 VCI Input for optional external post regulator output voltage (core supply):
Connect an external resistor divider to adjust the over and under voltage
thresholds of reset output signal ROT.
If the option external post regulator is not used, leave open.
27 GST Gate stress pin:
Not for customer use. Connect this pin directly (low ohmic and low inductive) to
ground.
28 AG3 Analogue ground, pin 3:
Connect this pin directly (low ohmic and low inductive) to ground.
29 QVR Output voltage reference:
Connect a capacitor as close as possible to pin.
30 QUC Output LDO_uC supply (micro processor supply):
Connect a capacitor as close as possible to pin.
31 QCO Output LDO_communication supply:
Connect a capacitor as close as possible to pin.
32 QT2 Output tracker 2:
Connect a capacitor as close as possible to pin.

Data Sheet 13 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

33 QT1 Output tracker 1:

Connect a capacitor as close as possible to pin.
34 N.C. Internally not connected:
This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

Pin Symbol Function

35 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

36 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

37 FB1 Step down pre regulator feedback input plus input for linear post regulators
and trackers, pin 1:
Connect the capacitor of the step down pre regulator output filter with low ohmic
and low inductive connection straight to this pin. Always connect in parallel with
pin FB2.

38 FB2 Step down pre regulator feedback input plus input for linear post regulators
and trackers, pin 2:
Connect the capacitor of the step down pre regulator output filter with low ohmic
and low inductive connection straight to this pin. Always connect in parallel with
pin FB1.

39 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

40 PG2 Step down pre regulator power ground, pin 2:

Connect this pin straight (low ohmic and low inductive) to ground and pre regulator
output capacitor minus. Always connect in parallel with pin PG1.

41 PG1 Step down pre regulator power ground, pin 1:

Connect this pin straight (low ohmic and low inductive) to ground and pre regulator
output capacitor minus. Always connect in parallel with pin PG2.

42 SW1 Step down pre regulator power stage output:

Connect this pin straight (low ohmic and low inductive) to the pre regulator output
filter.

43 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

Data Sheet 14 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

44 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

45 VS1 Supply voltage step down pre regulator input:

Connect this input to the output of the step up pre regulator. If step up pre regulator
option is not used, connect to supply (battery) voltage with reverse protection
diode and capacitor between pin and ground. An EMC filter is recommended.

Pin Symbol Function

46 DRG Driver output for external step up regulator power stage, connect to gate:
Gate of low side switch of step up pre regulator: Connect to the gate of an external
N-channel mosfet, line to be straight and as short as possible. If step up pre
regulator option is not used, leave open.

47 RSH Sense resistor for external step up regulator power stage, high side:
Connect this pin to the high side of an external current sense resistor to determine
the maximum current threshold through the external N-channel mosfet. If step up
pre regulator option is not used, connect to ground.

48 RSL Sense resistor for external step up regulator power stage, low side:
Connect this pin to the low side of an external current sense resistor to determine
the maximum current threshold through the external N-channel mosfet. If step up
pre regulator option is not used, connect to ground.

EP1 Edge pin no 1:

Keep area below this pin free of ground or other signals, do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.

EP2 Edge pin no 2:

Keep area below this pin free of ground or other signals, do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.

EP3 Edge pin no 3:

Keep area below this pin free of ground or other signals, do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.

EP4 Edge pin no 4:

Keep area below this pin free of ground or other signals, do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.

Coolin GND Cooling Tab.

g Tab Connect externally to GND and heat sink area.

Data Sheet 15 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

3.3 Pin Assignment - PG-LQFP-64

Figure 3 Pin Configuration - PG-LQFP-64

3.4 Pin Definitions and Functions - PG-LQFP-64

Pin Symbol Function

1 RSL Sense resistor for external step up regulator power stage, low side:
Connect this pin to the low side of an external current sense resistor to determine
the maximum current threshold through the external N-channel mosfet. If step up
pre regulator option is not used, connect to ground.

2 BSG Boost driver ground:

Connect this pin to ground at the low side of an external current sense resistor to
decouple the driver noise from the sensitive ground. If step up pre regulator option
is not used, connect to ground.

3 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

Pin Symbol Function

Data Sheet 16 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

4 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

5 VST Supply voltage standby regulator, input:

Connect this input to supply (battery) voltage with reverse protection diode and
capacitor between pin and ground. An EMC filter is recommended.

6 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

7 ENA Enable Input:

A positive edge signal at this pin will wake the device. In case of not used, connect
to ground.

8 WAK Wake/Inhibit Input:

A high level signal of defined length at this pin will wake the device. In case of not
used, connect to ground.

9 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential

failures.
10 QST Output standby LDO:
Connect a capacitor as close as possible to pin.

11 AG1 Analogue ground, pin 1:

Connect this pin directly (low ohmic and low inductive) to ground.

12 AGS1 Analogue ground, safety, pin 1:

Connect this pin directly (low ohmic and low inductive) to ground.
In case a safety switch is used, connect directly to the source of the NMOS used.

13 AGS2 Analogue ground, safety, pin 2:

Connect this pin directly (low ohmic and low inductive) to ground.
In case a safety switch is used, connect directly to the source of the NMOS used.

14 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

15 SS2 Safe state signal 2:

Safe state output signal 2, sets the application into a safe state. Signal is delayed
against SS1, delay can be adjusted via SPI command.

16 SS1 Safe state signal 1:

Safe state output signal 1, sets the application into a safe state.

Data Sheet 17 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

17 SDI Serial peripheral interface, signal data input:

SPI signalling port, connect to SPI port “data output” of micro processor to receive
commands during SPI communication.

18 SDO Serial peripheral interface, signal data output:

SPI signalling port, connect to SPI port “data input” of micro processor to send
status information during SPI communication.

Pin Symbol Function

19 SCL Serial peripheral interface, signal clock:

SPI signalling port, connect to SPI port “clock” of micro processor to clock the
device for SPI communication.

20 SCS Serial peripheral interface, signal chip select:

SPI signalling port, connect to SPI port “chip select” of micro processor to address
the device for SPI communication.

21 WDI Watchdog input, trigger signal:

Input for trigger signal, connect the “trigger signal output” of the micro processor
to this pin. In case of not used, leave open (internal pull-down).

22 ROT Reset output:

Open drain structure with internal pull-up current source. A low signal at this pin
indicates a reset event.

23 INT Interrupt signal:

Push-pull-stage. A low pulse at this pin indicates an interrupt, the micro processor
shall read out the SPI status registers. Connect to a non maskable interrupt port
(NMI) of the micro processor core supply voltage.

24 SYN Synchronization output signal:

Connect this output to the optional external switch mode post regulator
synchronization input. The signal delivers the step down regulator switching
frequency either in phase or shifted by 180° (selectable via SPI command). The
switch mode post regulator shall synchronize to the rising edge. If not used, leave
open.

25 ERR Error signal input:

Input for error signal from micro processor safety managing unit (SMU, internal
failure detection of the micro processor). Connect the “error signal output” of the
micro processor to this pin.

26 EVC Enable external post regulator for core supply:

Connect this pin to the enable input of the external post regulator. If not used,
leave open.

27 MPS Microcontroller programming support pin:

Pull down this pin to ground for operation. Optionally, this pin can be used for
microcontroller debugging and programming purposes. For details please refer to
Chapter 11.7.

Data Sheet 18 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

28 SEC Configuration pin for external post regulator for core supply:
Connect this pin to ground if the option external post regulator is not used. If the
option external post regulator is used, leave open.

29 FRE Frequency adjustment pin:

Connect pin to ground for low frequency range or leave open for high frequency
range.

30 STU Configuration pin for step up converter:

Connect this pin to ground if the option step up pre regulator is not used. If the
option step up pre regulator is used, leave open.

31 VCI Input for optional external post regulator output voltage (core supply):
Connect an external resistor divider to adjust the over and under voltage
thresholds of reset output signal ROT.
If the option external post regulator is not used, leave open.

Pin Symbol Function

32 GST Gate stress pin:

Not for customer use. Connect this pin directly (low ohmic and low inductive) to
ground.

33 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

34 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

35 AG2 Analogue ground, pin 2:

Connect this pin directly (low ohmic and low inductive) to ground.

36 AG3 Analogue ground, pin 3:

Connect this pin directly (low ohmic and low inductive) to ground.

37 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

38 QVR Output voltage reference:

Connect a capacitor as close as possible to pin.

39 QUC Output LDO_uC supply (micro processor supply):

Connect a capacitor as close as possible to pin.

40 SQUC Sense connection for LDO_uC supply (micro processor supply):

Connect to QUC/LDO_uC externally.

41 QCO Output LDO_communication supply:

Connect a capacitor as close as possible to pin.

Data Sheet 19 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

42 QT2 Output tracker 2:

Connect a capacitor as close as possible to pin.

43 SQT2 Sense connection tracker 2:

Connect to QT2/tracker 2 externally.

44 SQT1 Sense connection tracker 1:

Connect to QT1/tracker 1 externally.

45 QT1 Output tracker 1:

Connect a capacitor as close as possible to pin.

46 FB1 Step down pre regulator feedback input plus input for linear post regulators
and trackers, pin 1:
Connect the capacitor of the step down pre regulator output filter with low ohmic
and low inductive connection straight to this pin. Always connect in parallel with
pin FB1 - FB4.

47 FB2 Step down pre regulator feedback input plus input for linear post regulators
and trackers, pin 2:
Connect the capacitor of the step down pre regulator output filter with low ohmic
and low inductive connection straight to this pin. Always connect in parallel with
pin FB1 - FB4.

Pin Symbol Function

48 FB3 Step down pre regulator feedback input plus input for linear post regulators
and trackers, pin 3:
Connect the capacitor of the step down pre regulator output filter with low ohmic
and low inductive connection straight to this pin. Always connect in parallel with
pin FB1 - FB4.

49 FB4 Step down pre regulator feedback input plus input for linear post regulators
and trackers, pin 4:
Connect the capacitor of the step down pre regulator output filter with low ohmic
and low inductive connection straight to this pin. Always connect in parallel with
pin FB1 - FB4.

50 AG4 Analogue ground, pin 4:

Connect this pin directly (low ohmic and low inductive) to ground.

51 PG2 Step down pre regulator power ground, pin 2:

Connect this pin straight (low ohmic and low inductive) to ground and pre regulator
output capacitor minus. Always connect in parallel with pin PG1.

52 PG1 Step down pre regulator power ground, pin 1:

Connect this pin straight (low ohmic and low inductive) to ground and pre regulator
output capacitor minus. Always connect in parallel with pin PG2.

53 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

Data Sheet 20 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

54 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

55 SW2 Step down pre regulator power stage output, pin 2:

Connect this pin straight (low ohmic and low inductive) to the pre regulator output
filter. Always connect in parallel with pin SW1.

56 SW1 Step down pre regulator power stage output, pin 1:

Connect this pin straight (low ohmic and low inductive) to the pre regulator output
filter. Always connect in parallel with pin SW2.

57 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

58 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

59 VS2 Supply voltage step down pre regulator, pin 2, input:

Connect this input in parallel with VS1 to the output of the step up pre regulator.
If step up pre regulator option is not used, connect in parallel with VS1 to supply
(battery) voltage with reverse protection diode and capacitor between pin and
ground. An EMC filter is recommended.

Pin Symbol Function

60 VS1 Supply voltage step down pre regulator, pin 1, input:

Connect this input in parallel with VS2 to the output of the step up pre regulator.
If step up pre regulator option is not used, connect in parallel with VS2 to supply
(battery) voltage with reverse protection diode and capacitor between pin and
ground. An EMC filter is recommended.

61 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

62 N.C. Internally not connected:

This pin is electrically not connected internally and can be kept open/floating,
connected to GND or any other signal. Consider neighboring signals for potential
failures.

63 DRG Driver output for external step up regulator power stage, connect to gate:
Gate of low side switch of step up pre regulator: Connect to the gate of an external
N-channel mosfet, line to be straight and as short as possible. If step up pre
regulator option is not used, leave open.

Data Sheet 21 Rev. 2.0, 2017-03-16

 TLF35584

Pin Configuration

64 RSH Sense resistor for external step up regulator power stage, high side:
Connect this pin to the high side of an external current sense resistor to determine
the maximum current threshold through the external N-channel mosfet. If step up
pre regulator option is not used, connect to ground.

Coolin GND Cooling Tab.

g Tab Connect externally to GND and heat sink area.

Data Sheet 22 Rev. 2.0, 2017-03-16

 TLF35584

General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Table 1 Absolute Maximum Ratings1)

Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Voltages
Boost driver ground VBSG -0.3 – 0.3 V – P_4.1.1
Input standby LDO VVST -0.3 – 40 V 2) 3) P_4.1.2
Input voltage pin 1 (pre VVS1 -0.3 – 40 V 2) 3) P_4.1.3
regulator)
Input voltage pin 2 (pre VVS2 -0.3 – 40 V 2) 3) P_4.1.4
regulator) PG-LQFP-64 only
External step up power stage, VDRG -0.3 – 40 V 2) 3) P_4.1.5
gate

External power stage, sense VRSH -0.3 – 40 V 2) 3) P_4.1.6

resistor high

External power stage, sense VRSL -0.3 – 6.0 V – P_4.1.7

resistor low
Enable -0.3 – 40 V 2) 3) P_4.1.8
VENA
Enable IENA -5 – – mA 4) P_4.1.9
Wake/Inhibit -0.3 – 40 V 2) 3) P_4.1.10
VWAK
Wake/Inhibit IWAK -5 – – mA 4) P_4.1.11
Reset output VROT -0.3 – 6.0 V – P_4.1.12
SPI: Chip select CS VSCS -0.3 – 6.0 V – P_4.1.13
SPI: Clock CLK VSCL -0.3 – 6.0 V – P_4.1.14
SPI: Data_In DI VSDI -0.3 – 6.0 V – P_4.1.15
SPI: Data_Out DO VSDO -0.3 – 6.0 V – P_4.1.16
Interrupt VINT -0.3 – 6.0 V – P_4.1.17
Window watchdog trigger VWDI -0.3 – 6.0 V – P_4.1.18
Error pin VERR -0.3 – 6.0 V – P_4.1.19

Data Sheet 23 Rev. 2.0, 2017-03-16

 TLF35584

General Product Characteristics

Safe state 1 VSS1 -0.3 – 6.0 V – P_4.1.20

Safe state 2 VSS2 -0.3 – 6.0 V – P_4.1.21
Output voltage reference VQVR -0.3 – 6.0 V – P_4.1.22
Output tracker 2 VQT2 -0.3 – 40 V – P_4.1.23
Sense Pin for tracker 2 VSQT2 -0.3 – 40 V PG-LQFP-64 only P_4.1.24
Output tracker 1 VQT1 -0.3 – 40 V – P_4.1.25
Table 1 Absolute Maximum Ratings (cont’d)
1)

Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Sense Pin for tracker 1 VSQT1 -0.3 – 40 V PG-LQFP-64 only P_4.1.26
Output LDO_Com VQCO -0.3 – 6.0 V – P_4.1.27
Output LDO_µC VQUC -0.3 – 6.0 V – P_4.1.28
Sense Pin for LDO_µC VSQUC -0.3 – 6.0 V PG-LQFP-64 only P_4.1.29
V_Core_Mon ext core supply VVCI -0.3 – 6.0 V – P_4.1.30
Select ext core supply VSEC -0.3 – 6.0 V – P_4.1.31
Sync_Out ext core supply VSYN -0.3 – 6.0 V – P_4.1.32
Enable ext core supply VEVC -0.3 – 6.0 V – P_4.1.33
FB_BUCK4 VFB4 -0.3 – 7.0 V PG-LQFP-64 only P_4.1.35
FB_BUCK3 VFB3 -0.3 – 7.0 V PG-LQFP-64 only P_4.1.36
FB_BUCK2 VFB2 -0.3 – 7.0 V – P_4.1.37
FB_BUCK1 VFB1 -0.3 – 7.0 V – P_4.1.38
BU_GND2 VPG2 -0.3 – 0.3 V – P_4.1.39
BU_GND1 VPG1 -0.3 – 0.3 V – P_4.1.40
SW2 -0.3 – 40 V PG-LQFP-64 only P_4.1.41

VSW2
SW1 VSW1 -0.3 – 40 V – P_4.1.42
Select step up pre regulator VSTU -0.3 – 6.0 V – P_4.1.43
FRE VFRE -0.3 – 6.0 V – P_4.1.44
Q_STBY VQST -0.3 – 6.0 V – P_4.1.45
MPS VMPS -0.3 – 6.0 V – P_4.1.46
Temperatures
Junction Temperature Tj -40 – 150 °C – P_4.1.47

Storage Temperature Tstg -55 – 150 °C – P_4.1.48

ESD Susceptibility

Data Sheet 24 Rev. 2.0, 2017-03-16

 TLF35584

General Product Characteristics

ESD Susceptibility to GND VESD -2 – 2 kV HBM5) P_4.1.49

ESD Susceptibility to GND VESD -500 – 500 V CDM6) P_4.1.50

ESD Susceptibility (corner VESD,Corner -750 – 750 V CDM6) P_4.1.51

pins) to GND
1) Not subject to production test, specified by design.
2) Maximum rating is 60 V, if rise time from 0 to 60 V is longer than 10 ms
3) Maximum rating is 49 V, for an overall time of 10 s (in the range of 40 V to 49 V) during the lifetime of the product
independent from the rise time.
4) Consider external series resistor for negative voltages < -0.3 V to ensure maximum rating of current
5) ESD susceptibility, HBM according to JEDEC HBM Human Body Model ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF)
6) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.

4.2 Functional Range

Note:Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics table.

Table 2 Functional Range

Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

Data Sheet 25 Rev. 2.0, 2017-03-16

 TLF35584

General Product Characteristics

Supply Voltage Range for VBat 3 – 40 V with step up pre P_4.2.1

Normal Operation at input of regulator active in
the step-up converter front of step down
pre regulator1)

Supply Voltage Range for VVS 6 – 40 V without step up pre P_4.2.2

Normal Operation at pin VSx regulator active in
front of step down
pre regulator

Junction Temperature Tj -40 – 150 °C – P_4.2.3

1) To start up the TLF35584 needs a minimum input voltage of 6.0V at the pin VSx.

Note:Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics table.

4.3 Thermal Resistance

Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.

Table 3 Thermal Resistance 1)

Parameter Symbol Values Unit Note / Test Condition Number

Min. Typ. Max.

Junction to Case RthJC – – 12.2 K/W – P_4.3.1
Junction to Soldering Point RthJSP 20.1 – 22.1 K/W JEDEC 2s2p, P_4.3.2
(pin) measured to pin:
VQFN: 1, 6, 7, 28 ;
LQFP: 2, 11, 35, 50
Junction to Soldering Point RthJSP 34.9 – 37.6 K/W JEDEC 1s0p, P_4.3.3
(pin) measured to pin:
VQFN: 1, 6, 7, 28 ;
LQFP: 2, 11, 35, 50
Junction to Soldering Point RthJSP 11.0 – 14.7 K/W JEDEC 2s2p P_4.3.4
(soldering pad)
Junction to Soldering Point RthJSP 13.1 – 18.0 K/W JEDEC 1s0p P_4.3.5
(soldering pad)

Junction to Ambient RthJA – 37 – K/W 2) P_4.3.6

1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 mm Cu, 2 × 35 mm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

Data Sheet 26 Rev. 2.0, 2017-03-16

 TLF35584

General Product Characteristics

4.4 Quiescent Current Consumption

Table 4 Quiescent current consumption 1)

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Test Condition Number

Min. Typ. Max.

INIT state Iq – – 45 mA 1)
Tj ≤ 85°C P_4.4.1

Step-Up Converter is
off,
fPREREG,BUCK = 2.2 MHz
NORMAL state Iq – – 45 mA 1)
Tj ≤ 85°C P_4.4.2

Step-Up Converter is
off,
fPREREG,BUCK = 2.2 MHz
STANDBY state Iq – – 70 µA 1) P_4.4.3
LDO_STBY is off
VVS = 14 V ; Tj ≤ 40°C
STANDBY state Iq – – 90 µA LDO_STBY is off P_4.4.4
1)
Tj ≤ 85°C

STANDBY state Iq – – 120 µA LDO_STBY is on P_4.4.5

1)
Tj ≤ 85°C
SLEEP state Iq – – 200 µA 1)
Tj ≤ 85°C P_4.4.6

WAKE state Iq – – 45 mA 1)
Tj ≤ 85°C P_4.4.7
Step-Up Converter is
off,
fPREREG,BUCK = 2.2 MHz
FAILSAFE state Iq – – 200 µA 1)
Tj ≤ 85°C; tFAILSAFE P_4.4.8
> tFAILSAFE,min
1) All quiescent current parameters are measured at Tj ≤ 85°C and 10 V ≤ VVS ≤ 28 V with zero load and all selectable
options (Outputs, Watchdog, Timers, Step-Up converter) switched off.
4.4.1 Typical Performance Characteristics

INIT, NORMAL and WAKE Current Consumption Iq INIT, NORMAL and WAKE Current Consumption Iq
versus Supply Voltage VVS (FRE-Pin: open) versus Supply Voltage VVS (various configuration)

Data Sheet 27 Rev. 2.0, 2017-03-16

 TLF35584

General Product Characteristics

V [V] V [V]
VS VS

STANDBY Current Consumption Iq STANDBY Current Consumption Iq versus Supply

Voltage VVS (QST disabled) versus Supply Voltage VVS (QST enabled)

5 10 15 20 25 30 5 10 15 20 25 30
V [V] V [V] VS VS

Data Sheet 28 Rev. 2.0, 2017-03-16

 TLF35584

Wake Function

5 Wake Function

5.1 Introduction
The TLF35584 is automatically turned on when connected to a battery (Power-On-Reset POR) and moves into
INIT-state, where the device will be configured. After successful configuration, the device will be sent to NORMAL
state via SPI command. From NORMAL or WAKE state, the device can be sent to a low power state (SLEEP or
STANDBY) via SPI commands. The WAK and ENA signal are external triggers to leave the low power states (or
the FAILSAFE state).

Wake (pin WAK - level triggered) / Enable (pin ENA - edge triggered)
The WAK and ENA input pins are battery voltage level capable. A signal, with a voltage higher than VWAK,hi applied
at pin WAK for tWAK,min represents a valid Wake-Signal. A positive going edge at pin ENA with a rise time tENA,rise
represents a valid Wake-Signal as well.
A valid Wake-Signal will bring the device from STANDBY to INIT state, from SLEEP to WAKE state or from
FAILSAFE to INIT state.
A low signal VWAK,lo at pin WAK as well as a negative going edge at pin ENA will have no impact on the state
machine and will not initiate a transition between states.
In case a valid Wake-Signal is detected during the transition phase from NORMAL to SLEEP state, the device will
initiate a transition to WAKE state and generate an interrupt.
In case a valid Wake-Signal is detected during the transition phase from NORMAL to STANDBY state, the device
will initiate a transition to INIT state and a Reset (ROT) will be generated.
Before sending a SPI transition command, pin ENA doesn’t have to be brought below VENA,thrlo. Even if pin ENA is
high (above VENA,thrhi), the SPI transition command will still send the device into SLEEP or STANDBY state.
For further details please refer to Chapter 11 State Machine.

ENA

State
≥1 Machine
WAK

Figure 4 Principle of the enable function

Data Sheet 29 Rev. 2.0, 2017-03-16

 TLF35584

Wake Function

5.2 Electrical Characteristics Enable Signal

V
VS

VENA,thrhi

VENA,thrlo
t

tENA,rise
Figure 5 Valid enable signal

Table 5 Electrical Characteristics: Enable signal

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Enable EN
Enable upper threshold VENA,thrhi – – 2.00 V VENAincreasing P_5.2.1

Enable lower threshold VENA,thrlo 0.8 – – V VENA decreasing P_5.2.2

Enable threshold hysteresis VENA,hyst – 400 – mV - P_5.2.3

Enable signal, rise time tENA,rise – – 10 µs – P_5.2.4

Enable signal, minimum high tENA,high 20 – – µs – P_5.2.5

time

Enable high input current IENA,hi – 8 11 µA VENA = 16 V P_5.2.6

Enable low input current IENA,lo – 0.1 2 µA VENA = 0.5 V P_5.2.7

Data Sheet 30 Rev. 2.0, 2017-03-16

 TLF35584

Wake Function

5.3 Electrical Characteristics Wake Signal

V WAK,hi

V WAK,lo
t
t WAK,min
V

V WAK,hi

V WAK,lo
t
t WAK,min
Figure 6 Valid wake signal

Table 6 Electrical Characteristics: Wake signal

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

Parameter Symbol Values Unit Note / Number

Test Condition
Min. Typ. Max.

(unless otherwise specified)

Wake/Inhibit
Wake upper threshold VWAK,hi – – 2.00 V VWAK increasing P_5.3.1

Wake lower threshold VWAK,lo 0.8 – – V VWAK decreasing P_5.3.2

Wake signal hysteresis VWAK,hyst – 400 – mV – P_5.3.3

Wake signal, minimum length tWAK,min 40 – – µs – P_5.3.4

Wake high input current IWAK,hi – 8 11 µA VWAK = 5.0V P_5.3.5

Wake low input current IWAK,lo – 0.1 2 µA VWAK = 0.5V P_5.3.6

Data Sheet 31 Rev. 2.0, 2017-03-16

 TLF35584

Wake Function

5.4 Typical Performance Characteristics

Enable Input Threshold Voltage VENA,th versus Wake Input Threshold Voltage VWAK,th versus
Junction Temperature Tj Junction Temperature Tj

Tj [°C] Tj [°C]

Data Sheet 32 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

6 Pre Regulators

6.1 Introduction
The pre regulator is mandatory to maintain a stabilized and constant intermediate circuit voltage to supply the
following post regulators. It consists of two independent regulators: A step up converter with an external power
stage in front to maintain a minimum input voltage to the following step down converter.
The step up converter can be deactivated (if not needed) by connecting pin STU to ground. Leaving pin STU open
activates the step up regulator.
The step down regulator frequency can be preset by leaving pin FRE open for the high switching frequency range
or connecting to GND for the low switching frequency range.
The step down converter is constantly on, providing a stabilized intermediate circuit voltage VPREREG to supply the
following post regulators. The step up converter is connected directly to the input voltage VBat. It only operates
during low input voltage condition (i.e. cranking) when the input voltage drops below the threshold
VPRE_REG,boost,UV, to maintain an input voltage high enough for the following step down regulator. Low input voltage
condition means, that the input voltage at pin VSx is too low to provide an intermediate circuit voltage VPREREG
within the specified limits. An internal comparator connected to the input voltage path detects the threshold when
to turn on the step up converter. In case the input voltage is above the step up converter output voltage (threshold
for switching on the step up converter), this regulator is deactivated by the internal comparator. An internal logic
switches the step up converter on (and off again) whenever it is needed.

Figure 7 Principle pre regulator stage

Data Sheet 33 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

6.2 Step Up Regulator

6.2.1 Functional description

The asynchronous step up pre regulator provides a higher output voltage than the input voltage when operating.
This will be the case whenever the supply voltage should be too low to allow nominal values at the post regulator
outputs. The boost pre regulator output voltage will be well below the nominal supply (battery) voltage to make
sure, that he only operates during low input voltage conditions.
If the step up feature should not be necessary for the application, the external power elements (Mosfet, diode)
could be skipped, the filter elements might be adjusted to the application requirements.

Figure 8 Step Up Regulator

6.2.2 Electrical characteristics

Table 7 Electrical Characteristics: Step up regulator

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Step up pre regulator
Pre regulator boost output 7.00 7.5 8.00 V – P_6.2.2.1
voltage
VPRE_REG,boo
st

Threshold external sense VRSH-RSL 190 210 230 mV – P_6.2.2.2

resistor for OC

Data Sheet 34 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

Low side sense input current IRSL -120 -60 -30 µA VRSL = 0 V P_6.2.2.3
High side sense input current IRSH -45 -30 -15 µA tested at VRSH = 0 V P_6.2.2.4
Input under voltage threshold 8 8.3 8.6 V – P_6.2.2.5
VPRE_REG,boo
st,UV

Input under voltage threshold 80 – 200 mV – P_6.2.2.6

hysteresis
V PRE_REG,boo
st,UV, hyst

Gate driver peak sourcing IDRG,SRC – 130 – mA 1) P_6.2.2.7

current

Gate driver peak sinking IDRG,SNK – 100 – mA 1) P_6.2.2.8

current

Gate driver output rise time tR,DRG 12 – 150 ns 10% to 90% P_6.2.2.9
CDRG = 470 pF
Gate driver output fall time tF,DRG 12 – 150 ns 90% to 10% P_6.2.2.10
CDRG = 470 pF
Gate driver output voltage VDRG 4.5 5 5.5 V – P_6.2.2.11
Maximum Duty Cycle DMAX 75 95 – % – P_6.2.2.12
Blanking time 240 ns – P_6.2.2.13
tBlank
1) Specified by design, not subject to production test.
6.3 Step Down Regulator

6.3.1 Functional description

The synchronous step down pre regulator is continuously in operation providing a stable intermediate circuit
voltage to supply the following post regulators. The internal power stage consists of synchronous P-channel (high
side) and N-channel (low side) Mosfets. For startup a soft start function is implemented.

The regulation loop operates in voltage mode.

Under normal load conditions the regulator operates in Pulse Width Modulation (PWM). Under light load conditions
it will operate in Pulse Frequency Modulation (PFM) to minimize the internal current consumption (only in SLEEP
state, not in NORMAL, WAKE or INIT state).
The output filter of the step down regulator has to be sized to ensure a maximum output voltage ripple of 100 mV
in order to be in line with the PSRR specified for the post regulators.

Data Sheet 35 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

Figure 9 Step Down Regulator

6.3.2 Electrical characteristics

Table 8 Electrical Characteristics: Step down pre regulator

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Step Down Pre Regulator
Output 5.65 5.8 5.95 V PWM-mode; P_6.
voltage
VPREREG,BUC
K VVS ≥ 6.5 V
Output 5.6 5.8 6.00 V PFM-mode; P_6.
voltage
VPREREG,BUC
K VVS ≥ 6.5 V
Power RON, HS 150 360 630 mΩ VVS ≥ 6 V P_6.
stage high
side switch
on
resistance
Power RON, LS 50 200 300 mΩ VVS ≥ 6 V P_6.
stage low
side switch
on
resistance

Data Sheet 36 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

Buck peak 1.578 1.857 2.135 A – P_6.

over current
limit IPREREG, max
SW rise 2 6 14 ns 1) P_6.
tR, Buck
time
6.5V ≤ VVS ≤
18 V;
IPREREG ≥ 0.5
A
SW fall time tF, Buck 2 9 18 ns 1) P_6.
6.5V ≤ VVS ≤
18 V;
IPREREG ≥ 0.5
A
- - 100 % –

20 80 ns ≥ 0.5 A P_6.
50
Soft start tSS, BUCK 70 190 380 µs P_6.
ramp 1)
VPRE_REG,BUCK
rising from 5%
to 95% of
VPREREG,nominal
;
2.2 MHz
switching
frequency, no
load
Soft start tSS, BUCK 0.7 2.0 3.5 ms P_6.
ramp 1)
VPRE_REG,BUCK
rising from 5%
to 95% of
VPRE_REG,nominal
;
400 kHz
switching
frequency, no
load
Current IPWM/PFM 26 57 90 mA – P_6.
threshold
for
transition
from PWM
to PFM
Current IPFM/PWM 100 145 190 mA – P_6.
threshold
for

Data Sheet 37 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

transition
from PFM
to PWM
Over Tj,OT, WRN 130 145 160 °C Tj increasing P_6.
temperature 1)
warning
threshold
Table 8 Electrical Characteristics: Step down pre regulator (cont’d)
VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Over temperature shutdown Tj,OT, 175 190 205 °C Tj increasing P_6.3.2.15
threshold shutdown 1)

Over temperature sensor Tj,OT, hyst – 10 – °C 1) P_6.3.2.16

hysteresis
1) Specified by design, not subject to production test

6.3.3 Typical Performance Characteristics

Pre Regulator Output Voltage VPreReg
versus
Junction Temperature Tj (FRE-Pin: open)
Pre Regulator Output Voltage VPreReg
versus

Data Sheet 38 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators
Junction Temperature Tj (FRE-Pin: GND)
5.9 5.9
VVS = 13.5 V VVS = 13.5 V
FRE−Pin: open FRE−Pin: GND
fOSC,step−down = 2.2 MHz fOSC,step−down = 400 kHz

5.85 5.85

5.8 5.8

5.75 5.75

5.7 5.7
Tj = −40 °C Tj = −40 °C
Tj = 25 °C Tj = 25 °C
Tj = 150 °C Tj = 150 °C
5.65 5.65
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
I [mA] PreReg I [mA] PreReg
5.9 5.9
VVS = 13.5V VVS = 13.5V
FRE−Pin: open FRE−Pin: GND
fOSC,step−down = 2.2 MHz fOSC,step−down = 400 kHz

5.85 5.85

5.8 5.8

5.75 5.75

IPreReg = 200 mA IPreReg = 200 mA

5.7 5.7
IPreReg = 500 mA IPreReg = 500 mA
IPreReg = 800 mA IPreReg = 800 mA
IPreReg = 1200 mA IPreReg = 1200 mA
5.65 5.65
−50 0 50 100 150 −50 0 50 100 150
T [°C] j Tj [°C]

Pre Regulator Output Voltage VPreReg Pre Regulator Output Voltage VPreReg
versus versus
Load Current IPreReg (FRE-Pin: open) Supply Voltage VVS (FRE-Pin: open)
Pre Regulator Output Voltage VPreReg Pre Regulator Output Voltage VPreReg
versus versus
Load Current IPreReg (FRE-Pin: GND) Supply Voltage VVS (FRE-Pin: GND)

Data Sheet 39 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators
5.9 5.9
IPreReg = 800mA IPreReg = 800mA
FRE−Pin: open FRE−Pin: GND
fOSC,step−down = 2.2 MHz fOSC,step−down = 400 kHz

5.85 5.85

5.8 5.8

5.75 5.75

5.7 5.7
Tj = −40 °C Tj = −40 °C
Tj = 25 °C Tj = 25 °C
Tj = 150 °C Tj = 150 °C
5.65 5.65
5 10 15 20 25 30 35 40 5 10 15 20 25 30 35
V [V] VVS [V]
VS

ON, LS versus
High-Side Switch ON resistance RON, HS 40
versus
Supply Voltage VVS Low-Side Switch ON resistance R
Supply Voltage VVS

Data Sheet 40 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

550 250

500

450
200

400

350
150
300

250
100
200

150

50
100 Tj = −40 °C Tj = −40 °C
Tj = 25 °C Tj = 25 °C
50
Tj = 150 °C Tj = 150 °C
0 0
5 10 15 20 25 30 35 40 5 10 15 20 25 30 35 40
V [V] V [V]
VS VS
PreReg Dynamic Load Response (2mA to 500mA) PreReg Dynamic Load Response (2mA to 500mA)
(FRE-Pin: open ; VPreReg,nom = 5.8 V) (FRE-Pin: GND ; VPreReg,nom = 5.8 V)

Data Sheet 41 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

6.4 Frequency setting

6.4.1 Introduction
The frequency source supplies the step up pre regulator and the step down pre regulator with a constant
frequency. The synchronous power switches of the step down pre regulator will switch directly with the frequency
fOSC.
The frequency range of the step down pre regulator can be set to the high switching frequency range by leaving
pin FRE open or to the low switching frequency range by connected the pin FRE to GND. The switching frequency
will be set to the default value of the chosen frequency range. Optionally it can be fine tuned by SPI command
(BCK_FREQ_CHANGE) or the spread-spectrum option can be activated (BCK_FRE_SPREAD).
The switching frequency range of the step up pre regulator is lower than the switching frequency range of the step
down pre regulator.
The switching frequency of the step down pre regulator is offered at pin SYN for the optional external switch mode
post regulator for the µC core supply, if the SEC pin is left open.
The synchronization function is not available in PFM mode.
The TLF35584 cannot be synchronized to an external frequency source.

6.4.2 Electrical characteristics frequency setting

Table 9 Electrical Characteristics: Oscillator

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Frequency Setting FREQ
Step-up frequency range fOSC,step-up 400 500 600 kHz – P_6.4.2.1

Step-down low frequency fOSC,step-down 300 400 500 kHz FRE pin connected P_6.4.2.2
range to GND

Step-down high frequency fOSC,step-down 2000 2200 2500 kHz FRE pin open P_6.4.2.3
range

6.4.3 Typical Performance Characteristics

Step-up Switching Frequency fOSC,step-upversus Step-down Switching Frequency fOSC,step-downversus

Junction Temperature Tj (FRE-Pin: open) Junction Temperature Tj (FRE-Pin: GND)

Data Sheet 42 Rev. 2.0, 2017-03-16

 TLF35584

Pre Regulators

525 415
FRE−Pin: GND
fOSC,step−down = 400 kHz

520

410

515

510 405

505

400

500

495 395
−50 0 50 100 150 −50 0 50 100 150 Tj [°C] Tj [°C]

Step-down Switching Frequency fOSC,step-downversus

Junction Temperature Tj (FRE-Pin: open)
2.29
FRE−Pin: open
fOSC,step−down = 2.2 MHz
2.28

2.27

2.26

2.25

2.24

2.23

2.22

2.21

2.2
−50 0 50 100 150
T [°C]
j

Data Sheet 43 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

7 Post Regulators

7.1 Introduction
The TLF35584 includes a number of linear low drop post regulators and trackers and offers the possibility to
connect an external post regulator for the µC core supply if needed.
The linear post regulators and trackers are supplied from pins FBx. The band gap 1 for regulator block provides
the reference values for the error amplifiers of µC supply LDO (pin QUC), the communications supply LDO (pin
QCO) and the reference voltage source (pin QVR). The trackers get their reference value from the reference
voltage source (pin QVR). The output voltage of trackers 1 and 2 (present at pins QT1 and QT2) is following the
reference voltage source Volt_Ref with a small drop.
An additional external post regulator can be added to deliver the core supply for the micro processor. If this option
is used the configuration pin SEC must be left open. If the option is not used, pin SEC must be connected to
ground.
The post regulator is to be connected external and uses its own reference voltage, the input is fed from the pre
regulator output voltage VPREREG (which is similar to the values at pins FBx). The post regulator is enabled by a
high signal at pin EVC and switched off with a low signal at pin EVC. A synchronization signal (in phase or shifted
by 180 degree with the step down pre regulator signal) is offered at pin SYN for usage of a switch mode post
regulator.
All output voltages of the post regulators are connected to the voltage monitoring function (please refer to chapter
Monitoring Function).
In case of an over voltage the related post regulator will be switched off, the shutdown signal is generated by the
voltage monitoring function.

Data Sheet 44 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Figure 10 Principle post regulators

7.2 µ-Processor Supply

7.2.1 Functional description

The linear low drop regulator LDO_µC offers a precise 3.3 V or 5.0 V output voltage for micro processor supply.

Data Sheet 45 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

The regulator is supplied from the intermediate circuit voltage VPREREG which provides a stabilized voltage. The
output voltage VQUC (at pin QUC) is controlled by the error amplifier. The actual value is compared to a reference
voltage derived from band gap 1 for regulators. The stability of the control loop depends on the load current, the
characteristics of the output capacitor and the chip temperature. To ensure a stable operation the output capacitor
should be chosen according the specified requirements (capacitance value and electrical series resistance ESR)
in Table 10 “Electrical characteristics”. The input capacitor shown in figure below is the output filter capacitor of
the step down pre regulator.
Protection circuitry is installed to prevent the regulator and the application from damage:
• To protect the pass element of the LDO_µC from overstress the current limitation will limit the output current
to the maximum specified limit. Current sensing is done via a current mirror, no sense resistor is used. In case
the maximum current condition is reached, the current will be limited, thus the output voltage will decrease.
The regulator is protected against short circuit to ground.
• The output voltage is monitored by the voltage monitoring. In case of over voltage at pin QUC, the LDO_µC
will be switched off and the device will move into FAILSAFE state. The event will be stored in the SPI status
register (MONSF1). In case of under voltage at pin QUC, the device will move into INIT state, pin ROT will be
pulled low and the event will be stored in an SPI status register (MONSF2). The regulator will not be switched
off in case of output under voltage, which is shorter than the short to ground detection time tStG. If the under
voltage should be present for more than tStG, the device will move into FAILSAFE state. This event will be
stored in an SPI status register as well (MONSF0).
• There is a dedicated temperature sensor for this regulator. In case the power stage temperature exceeds the
pre warning threshold, an interrupt will indicate this event and it will be stored in an SPI status register
(OTWRNSF). If the power stage temperature exceeds the temperature shutdown threshold, the device will
move into FAILSAFE state, the regulator will be switched off and the event will be stored in an SPI status
register (OTFAIL). The off time due to temperature shut down will be at least one second.
If the device enters FAILSAFE state the ROT is pulled low and all supplies are switched off.
If the device enters STANDBY state the LDO_µC is switched off For
further details please refer to Chapter 11 State Machine.

Data Sheet 46 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Reset *) internal connection

function depending on package
FB1
QUC
FB2
VPREREG VQUC
FB3 & FB4
Overvoltage (PG-VQFN-48 only
)
(PG-LQFP-64 only
) *)
shutdown

Thermal Current SQUC

(PG-LQFP-64 only
)
shutdown limitation

On/Off
VRef_LDO_μC
Gate Driver Error Amplifier
Bandgap 1 for
Regulator block

Figure 11 Low drop linear regulator for micro processor supply LDO_µC

7.2.2 Electrical characteristics

Table 10 Electrical characteristics: µProcessor supply

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
µ Processor supply
Output voltage VQUC 4.9 5.0 5.1 V 0 mA ≤ IQUC≤ 600 P_7.2.2.1
TLF35584xxVS1 mA

Data Sheet 47 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Output voltage VQUC 3.23 3.3 3.37 V 0 mA ≤ IQUC≤ 600 P_7.2.2.2

TLF35584xxVS2 mA
Output current limitation IQUC, max 650 – 1100 mA – P_7.2.2.3
Drop voltage Vdr, QUC – – 400 mV 1) P_7.2.2.4
TLF35584xxVS1
Drop voltage Vdr, QUC – – 500 mV 1) P_7.2.2.5
TLF35584xxVS2
Load regulation ΔVQUC – 45 81 mV IQUC = 100µA to 600 P_7.2.2.6
TLF35584xxVS1 mA
Load regulation ΔVQUC – 39 60 mV IQUC = 100µA to 600 P_7.2.2.7
TLF35584xxVS2 mA

Power supply ripple rejection PSRRQUC 26 – – dB 5.8 V ; P_7.2.2.8

2) VPREREG =
ESRCQUC ≤ 100mΩ
Output capacitor CQUC 2.2 – 47 µF 2) P_7.2.2.9
Output capacitor, ESR ESR CQUC 0 – 200 mΩ 2) P_7.2.2.10
Over temperature warning Tj,OT, WRN 130 145 160 °C Tj increasing P_7.2.2.11
threshold 2)

Over temperature shutdown Tj,OT, shutdown 175 190 205 °C Tj increasing P_7.2.2.12
threshold 2)

Over temperature sensor Tj,OT, hyst – 10 – °C 2) P_7.2.2.13

hysteresis
1) Dropout voltage is defined as the difference between input and output voltage when the output voltage decreases 100
mV from output voltage measured at VI = VQ,nom + Vdr,max + 100 mV.
2) Specified by design, not subject to production test
7.2.3 Typical Performance Characteristics

QUC Output Voltage VQUC versus QUC Output Voltage VQUC versus
Junction Temperature Tj (TLF35584xxVS1) Junction Temperature Tj
(TLF35584xxVS2)

Data Sheet 48 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

5.08 j
TLF35584xxVS1 3.36
VQUC,nom = 5.0V TLF35584xxVS2
5.06 VQUC,nom = 3.3V

3.34
5.04

5.02 3.32

5
3.3

4.98

3.28
4.96
IQUC = 10 µA
IQUC = 10 µA
IQUC = 120 mA
4.94 3.26 IQUC = 120 mA
IQUC = 360 mA
IQUC = 360 mA
IQUC = 600 mA
IQUC = 600 mA
4.92
−50 0 50 100 150 3.24
T [°C] −50 0 50 100 150
Tj [°C]
QUC Output Voltage VQUC versus Load Current IQUC
Load Current IQUC (TLF35584xxVS1) (TLF35584xxVS2)
QUC Output Voltage VQUC versus QUC Dropout Voltage Vdr,QUC versus

5.08 3.36
TLF35584xxVS1 TLF35584xxVS2
VQUC,nom = 5.0V VQUC,nom = 3.3V
5.06
3.34

5.04

3.32
5.02

5 3.3

4.98
3.28

4.96

Tj = −40 °C 3.26 Tj = −40 °C

4.94 Tj = 25 °C T = 25 °C
Data Sheet 49 Rev. j 2.0, 2017-03-16
Tj = 150 °C Tj = 150 °C
4.92 3.24
0 100 200 300 400 500 600 0 100 200 300 400 500 600
I [mA] QUC I [mA] QUC
 TLF35584

Post Regulators
Load Current IQUC (TLF35584xxVS1) QUC
Dropout Voltage Vdr,QUC versus

Load Current IQUC (TLF35584xxVS2)

Data Sheet 50 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

QUC Dynamic Load Response (1mA to 600mA) QUC Dynamic Load Response (1mA to 600mA)
TLF35584xxVS1 (VQUC,nom = 5.0 V) TLF35584xxVS2 (VQUC,nom = 3.3 V)

7.3 Communication Supply

7.3.1 Functional description

The linear low drop regulator LDO_Com offers a precise 5.0 V output voltage for communication supply.
The regulator is supplied from the intermediate circuit voltage VPREREG, which provides a stabilized voltage. The
output voltage VQCO (at pin QCO) is controlled by the error amplifier. The actual value is compared to a reference
voltage derived from band gap 1 for regulators. The stability of the control loop depends on the load current, the
characteristics of the output capacitor and the chip temperature. To ensure a stable operation the output capacitor

Data Sheet 51 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

should be chosen according the specified requirements (capacitance value and electrical series resistance ESR)
in Table 11 “Electrical characteristics”. The input capacitor shown in figure below is the output filter capacitor of
the step down pre regulator.
Protection circuitry is installed to prevent the regulator and the application from damage:
• To protect the pass element of the LDO_Com from overstress the current limitation will limit the output current
to the maximum specified limit. Current sensing is done via a current mirror, no sense resistor is used. In case
the maximum current condition is reached, the current will be limited, thus the output voltage will decrease.
The regulator is protected against short circuit to ground.
• The output voltage is monitored by the voltage monitoring. In case of over voltage at pin QCO, the LDO_Com
will be switched off, the event will be indicated by an interrupt and stored in an SPI status register (MONSF1).
In case of under voltage at pin QCO, the event will be indicated by an interrupt and stored in an SPI status
register (MONSF2). The regulator will not be switched off in case of output under voltage, which is shorter
than the short to ground detection time tStG. If the under voltage should be present for more than tStG, the
regulator will be switched off. This event will be stored in the SPI status register (MONSF0) and an interrupt
will be generated.
• There is a dedicated temperature sensor for this regulator. In case the power stage temperature exceeds the
pre warning threshold, an interrupt will indicate this event and it will be stored in an SPI status register
(OTWRNSF). If the power stage temperature exceeds the temperature shutdown threshold, this event will be
stored in an SPI status register (OTFAIL), the regulator will be switched off and an interrupt will be generated.
After a temperature shut down the LDO_Com can be re enabled via SPI command.
The regulator LDO_Com is switched off in STANDBY and FAILSAFE state. In INIT, SLEEP, NORMAL and WAKE
state LDO_Com is ON or OFF depending on the SPI configuration.
For further details please refer to Chapter 11 State Machine.

Data Sheet 52 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Reset
function
FB1 QCO
FB2
VPREREG VQCO
FB3 & FB4
Overvoltage
(PG-LQFP-64 only
)
shutdown

Thermal Current
shutdown limitation
SPI:
On/Off
VRef_LDO_COM
Gate Driver Error Amplifier
Bandgap 1 for
Regulator block

Figure 12 Low drop linear regulator for communications supply LDO_Com

7.3.2 Electrical characteristics

Table 11 Electrical characteristics: Communication supply

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

Data Sheet 53 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Communication supply
Output voltage VQCO 4.90 5.00 5.10 V 0 mA ≤ IQCO≤ 200 P_7.3.2.1
mA

Output current limitation IQCO, max 250 – 400 mA – P_7.3.2.2

Drop voltage Vdr, QCO – – 400 mV 1) P_7.3.2.3

Load regulation ΔVQCO – 40 70 mV IQCO = 100µ to P_7.3.2.4

200 mA
Power supply ripple rejection PSRRQCO 26 – – dB 5.8 V ; P_7.3.2.5
2) VPREREG =
ESRCQCO ≤ 100mΩ
Output capacitor CQCO 1 – 47 µF 2) P_7.3.2.6

Output capacitor, ESR ESR CQCO 0 – 200 mΩ 2) P_7.3.2.7

Over temperature warning Tj,OT, WRN 130 145 160 °C Tj increasing P_7.3.2.8
threshold 2)

Over temperature shutdown Tj,OT, shutdown 175 190 205 °C Tj increasing P_7.3.2.9
threshold 2)

Over temperature sensor Tj,OT, hyst – 10 – °C 2) P_7.3.2.10

hysteresis
1) Dropout voltage is defined as the difference between input and output voltage when the output voltage decreases 100
mV from output voltage measured at VI = VQ,nom + Vdr,max + 100 mV.
2) Specified by design, not subject to production test
7.3.3 Typical Performance Characteristics
QCO Output Voltage VQCO versus QCO Output Voltage VQCO versus
Junction Temperature Tj Load Current IQCO

Data Sheet 54 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators
5.08 QCO

5.08
5.06

5.06
5.04

5.04
5.02

5.02
5

5
4.98

4.98
4.96
IQCO = 10 µA
IQCO = 60 mA 4.96
4.94
IQCO = 120 mA Tj = −40 °C
IQCO = 200 mA 4.94 Tj = 25 °C
4.92
−50 0 50 100 150 Tj = 150 °C
T [°C] 4.92
j 0 50 100 150 200
IQCO [mA]
QCO Dropout Voltage Vdr,QCO
QCO Dynamic Load Response (1mA to 100mA)
versus
Load Current IQCO (VQCO,nom = 5.0 V)
200

180

160

140

120

100

80

60

40
Tj = −40 °C

20 Tj = 25 °C
Tj = 150 °C
0
0 50 100 150 200
I [mA]

7.4 Voltage Reference

7.4.1 Functional description

The linear low drop regulator Volt_Ref offers a highly precise 5.0 V output voltage as a voltage reference.
The regulator is supplied from the intermediate circuit voltage VPREREG, which provides a stabilized voltage. The
output voltage VQVR at pin QVR is controlled by the error amplifier. The actual value is compared to a reference
Data Sheet 55 Rev. 2.0, 2017-03-16
 TLF35584

Post Regulators

voltage derived from band gap 1 for regulators. The stability of the control loop depends on the load current, the
characteristics of the output capacitor and the chip temperature. To ensure a stable operation the output capacitor
should be chosen according the specified requirements (capacitance value and electrical series resistance ESR)
in Table 12 “Electrical characteristics”. The input capacitor shown in figure below is the output filter capacitor of
the step down pre regulator.
Protection circuitry is installed to prevent the regulator and the application from damage:
• To protect the pass element of the Volt_Ref from overstress the current limitation will limit the output current
to the maximum specified limit. Current sensing is done via a current mirror, no sense resistor is used. In case
the maximum current condition is reached the current will be limited, thus the output voltage will decrease.
The regulator is protected against short circuit to ground.
• The output voltage is monitored by the voltage monitoring. In case of over voltage at pin QVR, the LDO
Volt_Ref will be switched off and the device will move into FAILSAFE state. The event will be stored in an SPI
status register (MONSF1). In case of under voltage at pin QVR, the event will be indicated by an interrupt and
stored in an SPI status register (MONSF2). The regulator will not be switched off in case of output under
voltage, which is shorter than the short to ground detection time tStG. If the under voltage should be present
for more than tStG, the regulator will be switched off. This event will be stored in an SPI status register
(MONSF0) and an interrupt will be generated.
• There is no dedicated temperature sensor for this regulator. The temperature is sensed on the chip by other
temperature sensors located at LDO_µC and step down pre regulator. In case of the chip temperature will
exceed the pre warning threshold, an interrupt will indicate this event and it will be stored in a SPI status
register (OTWRNSF). If the chip temperature will exceed the temperature shutdown threshold, the regulator
will be switched off. The temperature switch off time will be at least one second. An overload at LDO Volt_Ref
(over current detected for more than 1ms) will be indicated by an interrupt and it will be stored in a SPI status
register (OTWRNSF).
If the device enters FAILSAFE state the ROT is pulled low and all supplies are switched off.
The regulator Volt_Ref is switched off in STANDBY and FAILSAFE state. In INIT, SLEEP, NORMAL and WAKE
state Volt_Ref is ON or OFF depending on the SPI configuration.
For further details please refer to Chapter 11 State Machine.

Data Sheet 56 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Reset
function
FB1 QVR
FB2
VPREREG VQVR
FB3 & FB4
Overvoltage
(PG-LQFP-64 only
)
shutdown

Current
limitation

SPI: On/Off
VRef_Volt_Ref
Gate Driver Error Amplifier
Bandgap 1 for
Regulator block

Figure 13 Precise low drop linear regulator as a voltage reference Volt_Ref

7.4.2 Electrical characteristics

Table 12 Electrical characteristics: Voltage reference

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Voltage reference
Output voltage VQVR 4.95 5.00 5.05 V 0 mA ≤ IQVR≤ 150 P_7.4.2.1
mA

Output current limitation IQVR, max 170 – 345 mA – P_7.4.2.2

Drop voltage Vdr, QVR – – 400 mV 1) P_7.4.2.3

Load regulation ΔVQVR – 4.5 9 mV IQVR = 100µ to P_7.4.2.4

150 mA
Power supply ripple rejection PSRRQVR 26 – – dB 5.8 V ; P_7.4.2.5
2) VPREREG =
ESRCQVR ≤ 100mΩ
Output capacitor CQVR 1 – 10 µF 2) P_7.4.2.6

Data Sheet 57 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Output capacitor, ESR ESR CQVR 0 – 200 mΩ 2) P_7.4.2.7

1) Dropout voltage is defined as the difference between input and output voltage when the output voltage decreases 100
mV from output voltage measured at VI = VQ,nom + Vdr,max + 100 mV.
2) Specified by design, not subject to production test
7.4.3 Typical Performance Characteristics
QVR Output Voltage VQVR versus QVR Output Voltage VQVR versus
Junction Temperature Tj Load Current IQVR
5.04 200

180
5.03

160
5.02
140

5.01
120

5 100

80
4.99

60
4.98
IQVR = 10 µA
40
IQVR = 45 mA Tj = −40 °C
4.97
IQVR = 90 mA 20 Tj = 25 °C
IQVR = 150 mA Tj = 150 °C
4.96 0
−50 0 50 100 150 0 50 100 150
T [°C] I [mA]
j QVR

5.04
QVR Dropout Voltage Vdr,QVR
versus
5.03
Load Current IQVR

5.02

5.01

4.99

4.98

Tj = −40 °C
4.97 Tj = 25 °C
Tj = 150 °C
4.96
0 50 100 150
IQVR [mA]

Data Sheet 58 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators
QVR Dynamic Load Response (1mA
to 100mA)
(VQVR,nom = 5.0 V)

7.5 Tracker 1 & 2

7.5.1 Functional description

The linear trackers 1 and 2 offer a sensor supply with a very high accuracy referred to voltage reference output
(pin QVR).
Both trackers are supplied by the intermediate circuit voltage VPREREG, which provides a stabilized voltage. The
output voltage VQTx at pin QTx is controlled by the error amplifier. The actual value is compared to a reference
voltage provided by the reference voltage VQVR at pin QVR. The tracker output voltages follow the Volt_Ref output
with a very small drop. The stability of the control loop depends on the load current, the characteristics of the
output capacitor and the chip temperature. To ensure a stable operation the output capacitor for each tracker
should be chosen according the specified requirements (capacitance value and electrical series resistance ESR)
in Table 13 “Electrical characteristics”. The input capacitor shown in figure below is the output filter capacitor of
the step down pre regulator.
Protection circuitry is installed to prevent damage to both trackers and the application:
• To protect the pass element of a tracker from overstress the current limitation will limit the output current to
the maximum specified limit. Current sensing is done via a current mirror, no sense resistor is used. In case
the maximum current condition is reached, the current will be limited and in consequence the output voltage
will decrease. A tracker is protected against short circuit to ground and short circuit to battery voltage.
• The output voltage is monitored by the voltage monitoring. In case of over voltage at pin QTx, the
corresponding tracker will be switched off, the event will be stored in an SPI status register (MONSF1) and an
interrupt will be generated. In case of under voltage at pin QTx, the event will be stored in an SPI status
register (MONSF2) and an interrupt will be generated. The tracker will not be switched off in case of output
under voltage, which is shorter than the short to ground detection time tStG. If the under voltage should be
present for more than tStG, the tracker will be switched off. This event will be stored in an SPI status register
(MONSF0) and an interrupt will be generated.
• The tracker is capable to withstand a short circuit either to ground or to battery voltage without receiving a
damage. In case of a short circuit to battery voltage and if the battery voltage is above the tracker over voltage
threshold, the tracker will be switched off, the event will be stored in the SPI status register (MONSF1).
Data Sheet 59 Rev. 2.0, 2017-03-16
 TLF35584

Post Regulators

• There is no dedicated temperature sensor for this regulator. The temperature is sensed on the chip by other
temperature sensors located at LDO_µC and step down pre regulator. In case of the chip temperature will
exceed the pre warning threshold, the event will be stored in an SPI status register (OTWRNSF) and an
interrupt will be generated. If the chip temperature exceeds the temperature shutdown threshold, the tracker
will be switched off. The temperature switch off time is at least one second.
Both trackers are switched off in STANDBY and FAILSAFE. In INIT, NORMAL, SLEEP and WAKE state each
tracker is ON or OFF depending on the SPI configuration.

Reset *) internal connection

function depending on package
FB1
QTx
FB2
VPREREG VQTx
FB3 & FB4
Overvoltage (PG-VQFN-48 only )
(PG-LQFP-64 only)
shutdown
CP
Current SQTx
(PG-LQFP-64 only )
limitation

VRef_TRx
Gate Driver Error Amplifier
SPI:
ON/OFF Voltage Reference
VQVR

Figure 14 Tracker 1 & 2 for sensor supply

7.5.2 Electrical characteristics

Table 13 Electrical characteristics: Tracker 1 & 2

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Sensor supply, Tracker 1 & 2
Output voltage tracking ΔVQTx – 10 – 10 mV 0 mA ≤ IQT1≤ 150 P_7.5.2.1
accuracy to voltage reference mA
1)

Output current limitation IQTx, max 170 – 320 mA – P_7.5.2.2

Drop voltage Vdr, QTx – – 400 mV 2) P_7.5.2.3

Data Sheet 60 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Power supply ripple rejection PSRRQTx 26 – – dB 5.8 V ; P_7.5.2.4

3) VPREREG =
ESRCQTx ≤ 100 mΩ
Output capacitor CQTx 1 – 10 µF 3) P_7.5.2.5

Output capacitor, ESR ESR CQTx 0 – 200 mΩ 3) P_7.5.2.6

1) The output voltage of the tracker (pin QTx) is derived from the output voltage of the voltage reference (pin QVR). If the
voltage reference is switched off (voltage at pin QVR = 0V), than the output voltage at pin QTx will also be 0V, if the
tracker should be switched on, as the tracker output voltage is derived from pin QVR. But if the tracker is switched on
and its output voltage is 0V (because voltage at pin QVR is 0V), an under voltage at pin QTx will be detected and an
interrupt will be issued.
2) Dropout voltage is defined as the difference between input and output voltage when the output voltage decreases 100
mV from output voltage measured at VI = VQ,nom + Vdr,max + 100 mV.
3) Specified by design, not subject to production test
7.5.3 Typical Performance Characteristics
QTx Output Voltage VQTx versus QTx Output Voltage VQTx versus
Junction Temperature Tj Load Current IQTx
2 300

1
250

0
200

−1

150

−2

100
−3

IQTx = 10 µA
IQTx = 45 mA 50 Tj = −40 °C
−4
IQTx = 90 mA Tj = 25 °C
IQTx = 150 mA Tj = 150 °C
−5 0
−50 0 50 100 150 0 50 100 150
T [°C] I [mA]
j QTx

QTx Dropout Voltage Vdr,QTx versus

Load Current IQTx

Data Sheet 61 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators
2 (VQTx,nom = 5.0 V)

−1

−2

−3

Tj = −40 °C
−4
Tj = 25 °C
Tj = 150 °C
−5
0 50 100 150
IQTx [mA]

QTx Dynamic Load Response

(1mA to 100mA)
7.6 External Post Regulator for Core Supply (optional)
An additional external post regulator may be added to the TLF35584 to provide the core supply voltage VCore_Supply
for the µC if needed.
In this case the configuration pin SEC has to be left open to indicate that the external core voltage supply option
is active. The configuration of the SEC pin will only be read during the power sequencing at the point the core
supply would be started (Movements to INIT, please refer to Figure 16 and Figure 17).
The regulator is fed from the intermediate circuit voltage VPREREG. The post regulator is enabled by a high signal
at pin EVC and switched off by a low signal at pin EVC. The EVC signal is controlled by the state machine. For
example a detection of over voltage at pin VCI will create a low signal at pin EVC and shut down the post regulator
to protect the µC core.
The device offers a synchronization signal of 50% duty cycle at pin SYN equal in phase (only with a very small
delay) and frequency or shifted by 180 degree to the internal step down pre regulator (the selection is done via
SPI command). It is highly recommended to synchronize the external switch mode post regulator to this signal to
avoid interferences. The external post regulator will be enabled as soon as the pre regulator output voltage
VPREREG is present and the LDO_µC output voltage VQUC is above the lower reset threshold.
The output voltage of the post regulator VCore_Supply will be monitored by the reset function of the device. To obtain
a proper monitoring the output voltage of the post regulator has to be connected to the voltage monitoring input
at pin VCI via a resistor divider. The resistor divider should be dimensioned to adjust the post regulator output
voltage VCore_Supply to the internal reset reference voltage VVCI.
The synchronization signal at pin SYN can be switched on via SPI command, default configuration is off.
Protection circuitry should be installed to prevent the external regulator and the application from damage:
• To protect the pass device(s) of the external post regulator from overstress a current limitation function should
limit the output current to the maximum specified limit. Current sensing should be done via a current mirror,
no sense resistor should be used. In case the maximum current should occur, it will be limited, thus the output
voltage will decrease. The regulator should be protected against short circuit to ground.
• The output voltage is monitored by the voltage monitoring of the TLF35584, no further reset function is required
on the external post regulator. In case such a reset function should be present, it will not be used or supported
Data Sheet 62 Rev. 2.0, 2017-03-16
 TLF35584

Post Regulators

by the reset function of the TLF35584. In case of over voltage at pin, VCI the external post regulator will be
switched off by pulling pin EVC to low and the TLF35584 will move into FAILSAFE state. The event will be
stored in an SPI status register (MONSF1). In case of under voltage at pin VCI, the device will move into INIT
state, pin ROT will be pulled low and the event will be stored in an SPI status register (MONSF2). The external
post regulator will not be switched off in case of output under voltage, which is shorter than the short to ground
detection time tStG. If the under voltage is present for more than tStG, the device will move into FAILSAFE state.
This event will be stored in an SPI status register as well (MONSF0).
• There should be a temperature shutdown function at the external post regulator. If the power stage
temperature should exceed the temperature shutdown threshold, the post regulator should be switched off by
its own temperature shutdown. The TLF35584 will recognize this as an under voltage and react as described
above.

VPREREG
SEC

EVC
SYN VCore_Supply

Parts in grey box belong to external switchmode post regulator

VCI

Figure 15 External switch mode post regulator for core supply

Table 14 Electrical characteristics: External post regulator

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Enable signal, pin EVC
Enable high level VEVC, high 4.0 – – V VQUC = 5.0 V, P_7.6.0.1
TLF35584xxVS1 IEVC = -9 mA
Enable high level VEVC, high 4.6 – – V VQUC ≥ 4.7 V, P_7.6.0.2
TLF35584xxVS1 IEVC = -0.5 mA

Data Sheet 63 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Enable low level VEVC, low – – 0.7 V VQUC = 5.0 V P_7.6.0.3

TLF35584xxVS1 IEVC = 7 mA
Enable high level VEVC, high 2.3 – – V VQUC = 3.3 V P_7.6.0.4
TLF35584xxVS2 IEVC = -7 mA
Enable high level VEVC, high 3.0 – – V VQUC ≥ 3.1 V, P_7.6.0.5
TLF35584xxVS2 IEVC = -0.5 mA
Enable low level VEVC, low – – 0.7 V VQUC = 3.3 V P_7.6.0.6
TLF35584xxVS2 IEVC = 5.5 mA
Enable rise time tEVC, rise – – 25 ns CEVC, load = 50 pF P_7.6.0.7
1)

Enable fall time tEVC, fall – – 25 ns CEVC, load = 50 pF P_7.6.0.8

1)

Synchronisation signal source

VSYN, high 4.0 – – V V = 5.0 V, P_7.6.0.9
QUC
TLF35584xxVS1 I = -9 mA
SYN
Sync out high level Table 14 Electrical characteristics: External post regulator (cont’d)
VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

Sync out high level VSYN, high 4.6 – – V VQUC ≥ 4.7 V, P_7.6.0.10
TLF35584xxVS1 ISYN = -0.5 mA
Sync out low level VSYN, low – – 0.7 V VQUC = 5.0 V P_7.6.0.11
TLF35584xxVS1 ISYN = 7 mA
Sync out high level VSYN, high 2.3 – – V VQUC = 3.3 V P_7.6.0.12
TLF35584xxVS2 ISYN = -7 mA
Sync out high level VSYN, high 3.0 – – V VQUC ≥ 3.1 V, P_7.6.0.13
TLF35584xxVS2 ISYN = -0.5 mA
Sync out low level VSYN, low – – 0.7 V VQUC = 3.3 V P_7.6.0.14
TLF35584xxVS2 ISYN = 5.5 mA
Sync out signal duty cycle DSYN – 50 – % – P_7.6.0.15

Synch out signal rise time tSYN, rise – – 25 ns CSYN ,load = 50 pF P_7.6.0.16
1)

Synch out signal fall time tSYN, fall – – 25 ns CSYN, load = 50 pF P_7.6.0.17
1)

Data Sheet 64 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

Core voltage supply monitoring input

VCI – 100 130 nA V = 0.8 V P_7.6.0.18
VCI
pull-up current
1) specified by design, not subject to production test
Core voltage monitoring input I
7.7 Power Sequencing

The TLF35584 includes a power sequencing function to ensure a proper ramping up of all output voltages. After
the internal Power-On-Reset (POR) is released the standby regulator and the pre regulator start to operate.
In case of one of the non microcontroller related voltages (Volt_Ref, LDO_Com, Tracker1 or Tracker2) cannot be
ramped up (e.g. short to GND), the power sequence is stopped, but the reset output is still released after the
power on reset delay time trd. The microcontroller should check the status of the outputs by reading the SPI status
register
(VMONSTAT).
In case the microcontroller is sending a SPI request to enable or disable any non microcontroller related LDO
(Volt_Ref, LDO_Com, Tracker1 or Tracker2) during the power sequencing, the sequence will be stopped and the
requested configuration will be executed.

Data Sheet 65 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

7.7.1 Power sequencing from POR to INIT state

POR

V RT,QST,low

Actual value
Q_STBY_LDO

V RT,FB1,low

Actual value
PreReg

V RT,QUC,low

Actual value
Q_LDO_μC

V RT,VCI,low

Actual value
Core_sup adj.

V RT,QVR,low

Actual value
Volt_Ref.

V RT,QCO,low

Actual value
LDO_Com

V RT,QT1,low

Actual value
Tracker 1

V RT,QT2,low

Actual value
Tracker 2

1 2 3 4
5 6 7
8
Reset output
ROT

V ROT,high

V ROT,low

Figure 16 Power sequencing POR to INIT state

Description:
1. After POR is released the standby regulator and the pre regulator start to operate.
2. When VFB is above the lower reset threshold VRT,FB,low, the LDO_µC starts to operate.
3. When VQUC is above the lower reset threshold VRT,QUC,low, the external core supply will be enabled, when
selected. If the external core supply is not selected, the voltage reference LDO starts to operate.
4. If the external core supply is selected and VVCI is above the lower reset threshold VRT,VCI,low, the voltage
reference LDO starts to operate.
5. When VQVR is above the lower reset threshold VRT,QVR,low, the LDO_Com starts to operate.
6. When VQCO is above the lower reset threshold VRT,QCO,low, the Tracker 1 starts to operate.
7. When VQT1 is above the lower reset threshold VRT,QTx,low, the Tracker 2 starts to operate.

Data Sheet 66 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

8. This is the time from the enabling of the standby regulator until its output VQST is above the lower reset
threshold VRT,QST,low.
9. The reset delay time tRD starts after LDO_STBY, LDO_µC and the external core supply (if selected) have
reached their lower reset threshold VRT,x,low. The reset delay time is programmable via SPI. After the rest
delay time is expired, the ROT pin is pulled to high. The figure shows the possibilities of the tRD starting time.
Once the ROT is high, the microcontroller can change the configuration of the selectable LDOs which might
change the power sequencing accordingly.

Data Sheet 67 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

7.7.2 Power sequencing STANDBY to INIT state

POR

VRT,QST,low

Actual value
Q_STBY_LDO

VRT,FB1,low

Actual value
PreReg

VRT,QUC,low

Actual value
Q_LDO_μC

VRT,VCI,low

Actual value
Core_sup adj.

VRT,QVR,low

Actual value
Volt_Ref.

VRT,QCO,low

Actual value
LDO_Com

VRT,QT1,low

Actual value
Tracker 1

VRT,QT2,low

Actual value
Tracker 2

1 2 3 4
5 6
Reset output 7
ROT

VROT,high

VROT,low

Figure 17 Power sequencing STANDBY to INIT state

Description: Input voltage is present, device is in STANDBY state, LDO_STBY is active.
1. After a valid Wake-Signal or an expired wake-up timer the pre regulator starts to operate.
2. When VFB is above the lower reset threshold VRT,FB,low, the LDO_µC starts to operate.
3. When VQUC is above the lower reset threshold VRT,QUC,low, the external core supply will be enabled, when
selected. If the external core supply is not selected, the voltage reference LDO starts to operate.
4. If the external core supply is selected and VVCI is above the lower reset threshold VRT,VCI,low, the voltage
reference LDO starts to operate.

Data Sheet 68 Rev. 2.0, 2017-03-16

 TLF35584

Post Regulators

5. When VQVR is above the lower reset threshold VRT,QVR,low, the LDO_Com starts to operate.
6. When VQCO is above the lower reset threshold VRT,QCO,low, the Tracker 1 starts to operate.
7. When VQT1 is above the lower reset threshold VRT,QTx,low, the Tracker 2 starts to operate.
8. The reset delay time tRD starts after LDO_µC and the external core supply (if selected) have reached their
lower reset threshold VRT,x,low. The reset delay time is programmable via SPI. After the rest delay time is
expired the ROT pin is pulled to high. The figure shows the possibilities of the tRD starting time.

7.7.3 Power sequencing SLEEP to WAKE state

Enable signal
ENA

VRT,QST,low

Actual value
Q_STBY_LDO

VRT,FB1,low

Actual value
PreReg

VRT,QUC,low

Actual value
Q_LDO_μC

VRT,QVR,low

Actual value
Volt_Ref.

VRT,QCO,low

Actual value
LDO_Com

VRT,QT1,low

Actual value
Tracker 1

VRT,QT2,low

Actual value
Tracker 2

1 2
3 4
Reset output
ROT

VROT,high

VROT,low

Figure 18 Power sequencing SLEEP to WAKE state

Description: Input voltage is present, device is in SLEEP state, all selectable LDOs switched off in SLEEP state,
all selectable LDOs were switched on in previous NORMAL state:
1. After a valid Wake-Signal or an expired wake-up timer the voltage reference starts to operate.
2. When VQVR is above the lower reset threshold VRT,QVR,low, the LDO_Com starts to operate.
3. When VQCO is above the lower reset threshold VRT,QCO,low, the Tracker 1 starts to operate.
4. When VQT1 is above the lower reset threshold VRT,QTx,low, the Tracker 2 starts to operate.
Data Sheet 69 Rev. 2.0, 2017-03-16
 TLF35584

Post Regulators

The reset output ROT is high in SLEEP state and will be kept high for WAKE state.
In case a selectable LDO was switched off in the previous NORMAL state, it will not be enabled during the
transition from SLEEP to WAKE, the power sequencing will follow up with the next LDO. In case a LDO was
enabled during SLEEP state and was enabled in the previous NORMAL state, it will be kept enabled.

Data Sheet 70 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

8 Monitoring Function

8.1 Introduction

The TLF35584 includes an independent voltage monitoring function of all output voltages, including the optional
external post regulator for µC core supply, if in use.
The monitoring function consists of two comparators for each output voltage. One is for detecting over voltage,
the other is for detecting under voltage. Both comparators get their reference value from an independent bandgap
only used for the voltage monitoring block. This bandgap is independent from the voltage regulator bandgap. The
bandgap provides the reference value for over voltage detection (highvoltage reset threshold VRT,xxx,high) and for
under voltage detection (low voltage reset threshold VRT,xxx,low). Under normal operation conditions the output
voltage of the related regulator has to stay within the voltage window defined by the upper limit VRT,xxx,high and the
lower limit VRT,xxx,low.
There is a dedicated temperature sensor for the monitoring block. If the power stage temperature exceeds the
temperature shutdown threshold, the device will move into FAILSAFE state, the regulator will be switched off and
the event will be stored in an SPI status register (OTFAIL). The off time due to temperature shut down will be at
least one second.

Characteristics:
The behavior of the over and under voltage comparators is as following:
• The upper limits VRT,xxx,high and the lower limits VRT,xxx,low are fixed for every regulator and cannot be
programmed or varied by SPI command.
• An over voltage will be detected if the regulator output voltage is higher than the related over voltage reset
threshold VRT,xxx,high for more than the reset reaction time tRR. An over voltage higher than the related over
voltage reset threshold VRT,xxx,high which is present for shorter than the reset reaction time tRR will be regarded
as a spike and will not be detected.
An under voltage will be detected if the regulator output voltage is lower than the related under voltage reset
threshold VRT,xxx,low for more than the reset reaction time tRR. An under voltage lower than the related under
voltage reset threshold VRT,xxx,low which is present for shorter than the reset reaction time tRR will be
regarded as a spike and will not be detected.
• The reset reaction time tRR is not valid for the internal voltage supplies in case of under and over voltage.
• The detection of an over voltage will shut down the related regulator immediately to protect the loads from
harm or destruction. This shut down may lead (depending on the affected regulator) to further action, please
refer to chapter State Machine for details.
• The detection of an under voltage will not shut down the related regulator.
• The post regulators (including the optional external post regulator for µC core supply) have a short to ground
detection. If the detected under voltage is present for more than the short to ground detection time tStG, the
related regulator will shut down to protect himself and the chip from over heating. This shut down may lead
(depending on the affected regulator) to further action, please refer to chapter State Machine for details. (It is
mandatory that the external post regulator for µC core supply has an enable or inhibit function).
• The over and under voltage detection is active only if the related regulator is in use (including the external post
regulator for µC core supply) and switched on.

Data Sheet 71 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

Indication of over and under voltage:

Depending on the related regulator the indication of over and under voltage will be different, either by reset signal
or by interrupt indication:
• Every over and under voltage detection will be stored in the SPI status register (MONSF0, MONSF1,
MONSF2).
• For µC related output voltages (VQST , VQUC , VVCI), over and under voltage are indicated by the hardware
reset pin ROT. In case of an over or under voltage, pin ROT is pulled to low.
• In case of over voltage or a detection of a short to ground at the external post regulator for µC core supply,
the pin EVC will be pulled to low to shut down the regulator.
• For the pre regulator output (VFB) and the voltage reference output (VQVR) only over voltage is indicated by the
hardware reset pin ROT. In case of an over voltage, pin ROT is pulled to low.
• For the pre regulator output and the voltage reference output, only under voltage is indicated by an interrupt.
• For all not µC related output voltages (VQCO , VQT1 , VQT2), over and under voltage are indicated by an interrupt.
• For the internal supply voltages, over and under voltage are indicated by the hardware reset pin ROT. In case
of an over or under voltage, pin ROT is pulled to low.

This introduction is an overview, for details please refer to the following sub chapters.

8.2 Shutdown Function

A short to ground detection time tStG at the pre regulator output is only active during the power sequence in INIT
state. If the output voltage of the pre regulator should not be within the specified limits within a certain time frame,
the device will move into FAILSAFE state. There will be no reaction on a detected short to ground once the
VPREREG,BUCK is in a valid range after crossing the first time its UV threshold (step 1 completed according to the
power sequencing described in Chapter 7.7). If the output voltage of the pre regulator should be too low in other
cases, the behavior of the device will depend on the voltage monitoring of the post regulators.
The detection of an over voltage at output voltages VQUC, VVCI, VQST, VQVR or VFB will shut down all regulators to
protect the loads from harm or destruction and moves the device to FAILSAFE.
The detection of an over voltage at output voltages VQCO, VQT1 and VQT2 will shut down the related regulator to
protect the loads from harm or destruction and generate an interrupt event.
If the detected under voltage at output voltages VQUC, VVCI or VQST should be present for more than the short to
ground detection time tStG, all regulators will shut down to protect themselves and the chip from over heating and
move the device to FAILSAFE.
If the detected under voltage at output voltages VQVR, VQCO, VQT1 or VQT2 should be present for more than the
short to ground detection time tStG, the related regulator will shut down to protect himself and the chip from over
heating and generate an interrupt event.

8.3 Reset Function

The reset generator starts to operate as soon as the internal POR is released.

Distinguish between “Soft Reset” and “Hard Reset”

Data Sheet 72 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

It is called a “Soft Reset” if pin ROT goes below VROT,low, but the pre and post regulator output voltages are not
switched off.
It is called a “Hard Reset” if pin ROT goes below VROT,low and the post regulator output voltages are switched off.
The power sequencing will be restarted after a delay of tSDT.(Applicable to the second initialization timeout in a
row)

Safe State Control trigger event

The safe state control function is connected to the monitoring block. In case of a safe state control trigger event
is detected, pins Safe State Control Outputs (SS1 and SS2) and ROT will be pulled to ground. The safe state
control trigger event will be stored in a SPI register (respective bits in SYSFAIL, INITERR, MONSF1, MONSF2,
MONSF3 or OTFAIL). For trigger conditions of safe state signal SS1 please refer to chapter Safe State Control
Function.

Reset output pin

The reset output pin ROT is an open drain structure. As soon as a reset condition occurs, the ROT pin is pulled
below VROT,low. An internal pull up current is pulling the output towards VQUC.

Data Sheet 73 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

Figure 19 Principle reset function

Detailed description of the reset function (Figure 19):
The following regulators contribute to the reset function:
• Internal supply monitoring (not visible externally)
• The standby regulator (Q_STBY_LDO): VQST
• The LDO for supplying the µC (Q_LDO_µC): VQUC
• The external post regulator for µC core supply (Core_sup adj.): VVCI
• The voltage reference (Volt_Ref.): VQVR - only over voltage, not under voltage, not short to ground
• The pre regulator (PreReg.): VFB - only over voltage, not under voltage
The actual values of these outputs are taken directly at the output pins and are monitored by two comparators for
each regulator, one for over voltage (named OV), the other for under voltage (named UV). The reference values
VRT,XXX,high and VRT,XXX,low are provided by an independent band gap 2 only related to the monitoring functions.

Data Sheet 74 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

The “Internal supply voltage regulator monitoring” of over and under voltage events and IBIAS monitoring are
contributing to trigger a reset. If one or both of the internal supply voltages should be out of their specified windows,
the proper function of the device cannot be guaranteed any more. The IBIAS monitor fault is stored in a status bit
(BIASHI or BIASLOW). The fault of the internal supplies will trigger a “Move to Powerdown” event (please refer
to chapter State Machine for details).

Description:
• VXXX = Output voltage monitored by reset generator: VQUC , VVCI, VQST, VQVR or VFB
• VRT,XXX,high= Over voltage reset threshold: VRT,QUC,high, VRT,VCI,high, VRT,QST,high, VRT,QVR,high or VRT,FB,high
• VRT,XXX,low= Under voltage reset threshold: VRT,VCI,low, VRT,QUC,low or VRT,QST,low
• tRD = Reset delay time, adjustable by SPI command
• tRR = Reset reaction time, time between detecting over voltage and pulling ROT to low
• < tRR = Not detectable, because shorter than reset reaction time
• > tStG = Short to ground detection time, time after an under voltage is considered as a short to ground
• tFAILSAFE,min = System shutdown time (FAILSAFE), time between pulling ROT to low and restart of the device,
for details please refer to chapter State Machine
• VROT = Hardware reset signal, ROT
• VROT,high = Hardware reset signal, high level

Data Sheet 75 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

• VROT,low = Hardware reset signal, low level

• VXXX,OV = Over voltage detected for VXXX and stored in SPI register (MONSF1)
• VXXX,UV = Under voltage detected for VXXX and stored in SPI register (MONSF2)
• VXXX,StG = Short to ground detected for VXXX and stored in SPI register (MONSF0)
• Applies as well to bias current violations, supply overvoltage (MONSF3), temperature shutdown (OTFAIL)
contributing to the reset function. Please refer to Figure 43 and Figure 50
8.4 Interrupt Function

The interrupt generator starts to operate as soon as the internal POR is released.

The voltage monitoring function supervises the values of the non µC related post regulator output voltages VQCO,
VQT1 and VQT2, the pre regulator output voltage VFB (under voltage only) and the voltage reference output VQVR
(under voltage and short to ground only). The result is written in a SPI status register (IF and MONSF0, MONSF1
or MONSF2) and indicated via interrupt (pin INT). The connection of all these monitoring signals is a logic OR.
The interrupt pin INT does not only indicate the result of the voltage monitoring, but also interrupts due to other
events in the device.

Interrupt output pin

The interrupt output pin INT is a push pull structure. An interrupt is indicated by pulling the INT pin to ground.

Data Sheet 76 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

Figure 21 Principle indication of voltage monitoring via interrupt

Detailed description of the voltage monitoring via interrupt function (Figure 21):
The following regulators contribute to the voltage monitoring via interrupt function:
• The pre regulator (PreReg.): VFB , just under voltage
• The voltage reference (Volt_Ref.): VQVR , just under voltage and short to GND
• The LDO for supplying the communication (LDO_Com): VQCO
• The sensor supply 1 (Tracker 1): VQT1
• The sensor supply 2 (Tracker 2): VQT2
The actual values of these outputs are taken directly at the output pins and monitored by two comparators for
each regulator, one for over voltage (named OV), the other for under voltage (named UV). The reference values
VRT,XXX,high and VRT,XXX,low are provided by an independent band gap 2 only related to the monitoring functions.

Data Sheet 77 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

Figure 22 Timing diagram interrupt indication for output voltages

Description:
• VXXX = Output voltage monitored by interrupt indication: VFB , VQVR, VQCO , VQT1 or VQT2
• VRT,XXX,high= Over voltage interrupt indication: VRT,QCO,high, VRT,QT1,high or VRT,QT2,high
• VRT,XXX,low= Under voltage interrupt indication: VRT,FB,low, VRT,QVR,low, VRT,QCO,low, VRT,QT1,low or VRT,QT2,low
• tRR = Reset reaction time, time between detecting overvoltage and an interrupt is generated
• < tRR = Not detectable, because shorter than reset reaction time
• > tStG = Short to ground detection time, time after an under voltage is considered as a short to ground
• VXXX,OV = Over voltage detected for VXXX and stored in SPI register (MONSF1)
• VXXX,UV = Under voltage detected for VXXX and stored in SPI register (MONSF2)
• VXXX,StG = Short to ground detected for VXXX and stored in SPI register (MONSF0)
• Applies as well to detection of bandgap 1 to 2 variations (MONSF3), over load and temperature events
(OTWRNSF, OTFAIL) contributing to the interrupt function. Please refer to Figure 42
8.5 Electrical Characteristics Voltage Monitoring and Reset Function

Table 15 Electrical Characteristics: Hardware reset signals

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number

Data Sheet 78 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

Min. Typ. Max. Test Condition

Timing
Reset cycle time tCYCLE 9.4 10 10.65 µs – P_8.5.1

Reset delay time, default tRD – 1000 – tCYCLE – P_8.5.2

value

Reset delay time, adjustable tRD 20 – 1500 tCYCLE 1) P_8.5.3

range by SPI command

Reset reaction time tRR 8 – 20 µs – P_8.5.4

Reset reaction time, standby tRR, STBY 8 – 40 µs – P_8.5.5

regulator

Short to ground detection tStG 2.7 3 3.3 ms P_8.5.6

time

Step-down regulator short to tStG,HF 2.7 3.3 ms step down pre P_8.5.7
ground detection time 3 regulator 2.2 MHz
switching
frequency
Step-down regulator short to tStG,LF 5.4 6 6.6 ms step down pre P_8.5.8
ground detection time regulator 400 kHz
switching
frequency
System shutdown time tSDT 9 – 20 ms – P_8.5.9
Reset thresholds standby regulator, pin QST
Over voltage reset threshold VRT,QST,high 5.25 5.35 5.45 V VQST increasing P_8.5.10
TLF35584xxVS1

Over voltage reset hysteresis 30 – 90 mV – P_8.5.11

VRT,QST,OV
TLF35584xxVS2 hyst

Under voltage reset threshold VRT,QST,low 4.2 4.3 4.4 V VQST decreasing P_8.5.12
TLF35584xxVS1

Under voltage reset 30 – 70 mV – P_8.5.13

hysteresis TLF35584xxVS1
VRT,QST,UV
hyst

Over voltage reset threshold VRT,QST,high 3.46 3.53 3.6 V VQST increasing P_8.5.14
TLF35584xxVS2

Over voltage reset hysteresis 20 – 55 mV – P_8.5.15

VRT,QST,OV
TLF35584xxVS2 hyst

Under voltage reset threshold VRT,QST,low 2.9 2.97 3.05 V VQST decreasing P_8.5.16
TLF35584xxVS2

Under voltage reset 20 – 50 mV – P_8.5.17

hysteresis TLF35584xxVS2
VRT,QST,UV
hyst
Reset thresholds LDO_µC, pin QUC

Data Sheet 79 Rev. 2.0, 2017-03-16

 TLF35584

Parameter Symbol Values Unit Note / Monitoring Function

Number
Test Condition
Table 15 Electrical Characteristics: Hardware
Min. reset Max.(cont’d)
Typ. signals
V VS =6.0
Over V toreset
voltage Tj = -40°C to
40 V,threshold +150°C, all5.25
VRT,QUC,high voltages5.35
with respect
5.45to ground,
V positive
VLDO_µCcurrent flowingP_8.5.18
increasing into pin
(unless otherwise specified)
TLF35584xxVS1

Over voltage reset hysteresis 30 – 90 mV 2) P_8.5.19

VRT,QUC,OV
TLF35584xxVS1 hyst

Under voltage reset threshold VRT,QUC,low 4.2 4.3 4.4 V VLDO_µC decreasing P_8.5.20
TLF35584xxVS1

Under voltage reset 30 – 70 mV 2) P_8.5.21

hysteresis TLF35584xxVS1
VRT,QUC,UV
hyst

Over voltage reset threshold VRT,QUC,high 3.46 3.53 3.6 V VQUC increasing P_8.5.22
TLF35584xxVS2

Over voltage reset hysteresis 20 – 55 mV 2) P_8.5.23

VRT,QUC,OV
TLF35584xxVS2 hyst

Under voltage reset threshold VRT,QUC,low 2.9 2.97 3.05 V VQUC decreasing P_8.5.24
TLF35584xxVS2

Under voltage reset 20 – 50 mV 2) P_8.5.25

hysteresis TLF35584xxVS2
VRT,QUC,UV
hyst
Reset thresholds external core supply, pin VCI
Over voltage reset threshold VRT,VCI,high 860 872 884 mV VVCI increasing P_8.5.26

Over voltage reset hysteresis 5 – 15 mV 2) P_8.5.27

VRT,VCI,OV
hyst

Under voltage reset threshold VRT,VCI,low 716 728 740 mV VVCI decreasing P_8.5.28

Under voltage reset 5 – 15 mV 2) P_8.5.29

hysteresis
VRT,VCI,UV
hyst
Reset thresholds V_PreReg, pins FBx
Over voltage reset threshold VRT,FB,high 6.46 6.58 6.7 V VFB increasing P_8.5.30

Over voltage reset hysteresis VRT,FB,OV 40 – 120 mV – P_8.5.31

hyst

Under voltage reset threshold VRT,FB,low 5.0 5.1 5.2 V VFB decreasing P_8.5.32

Under voltage reset VRT,FB,UV hyst 30 – 90 mV – P_8.5.33

hysteresis
Reset thresholds LDO_Com, pin QCO
Over voltage reset threshold VRT,QCO,high 5.4 5.5 5.6 V VQCO increasing P_8.5.34

Over voltage reset hysteresis 30 – 90 mV – P_8.5.35

VRT,QCO,OV
hyst

Under voltage reset threshold VRT,QCO,low 4.4 4.5 4.6 V VQCO decreasing P_8.5.36

Under voltage reset 20 – 80 mV – P_8.5.37

hysteresis
VRT,QCO,UV
hyst
Reset thresholds voltage reference, pin QVR

Data Sheet 80 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

Table 15 Electrical Characteristics: Hardware reset signals (cont’d)

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Over voltage reset threshold VRT,QVR,high 5.25 5.35 5.45 V VQVR increasing P_8.5.38

Parameter Symbol Values Unit Note / Number

Test Condition
Min. Typ. Max.

Over voltage reset hysteresis 30 – 80 mV – P_8.5.39

VRT,QVR,OV
hyst

Under voltage reset threshold VRT,QVR,low 4.2 4.3 4.4 V VQVR decreasing P_8.5.40

Under voltage reset 30 – 70 mV – P_8.5.41

hysteresis
VRT,QVR,UV
hyst
Reset thresholds tracker 1, pin QT1
Over voltage reset threshold VRT,QT1,high 5.4 5.5 5.6 V VQT1 increasing P_8.5.42

Over voltage reset hysteresis 30 – 90 mV – P_8.5.43

VRT,QT1,OV
hyst

Under voltage reset threshold VRT,QT1,low 4.4 4.5 4.6 V VQT1 decreasing P_8.5.44

Under voltage reset 20 – 80 mV – P_8.5.45

hysteresis
VRT,QT1,UV
hyst
Reset thresholds tracker 2, pin QT2
Over voltage reset threshold VRT,QT2,high 5.4 5.5 5.6 V VQT2 increasing P_8.5.46

Over voltage reset hysteresis 30 90 mV – P_8.5.47

VRT,QT2,OV –
hyst

Under voltage reset threshold VRT,QT2,low 4.4 4.5 4.6 V VQT2 decreasing P_8.5.48

Under voltage reset 20 – 80 mV – P_8.5.49

hysteresis
VRT,QT2,UV
hyst
Input Voltage VSx Monitoring, pin VSx
Input over voltage reset
VVS,OV 45 47 49 V P_8.5.50
threshold
Overtemperature Protection of Monitoring
Over temperature shutdown Tj,OT, 175 190 205 °C Tj increasing P_8.5.51
threshold shutdown 2)

Over temperature shutdown Tj,OT, hyst – 10 – °C 2) P_8.5.52

hysteresis
Reset output ROT
Reset output, pull-up current IROT, pu -175 -110 -15 µA VROT <= 2.0 V P_8.5.53

Data Sheet 81 Rev. 2.0, 2017-03-16

 TLF35584

Monitoring Function

Table 15 Electrical Characteristics: Hardware reset signals (cont’d)

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)

Parameter Symbol Values Unit Note / Number

Test Condition
Min. Typ. Max.

Reset output, low level VROT, low – – 0.7 V VQUC = 5.0 V, P_8.5.54
TLF35584xxVS1 IROT = 7 mA
Reset output, low level VROT, low – – 0.4 V VQUC = 5.0 V, P_8.5.55
TLF35584xxVS1 IROT = 3.5 mA
Reset output, low level VROT, low – – 0.7 V VQUC = 3.3 V, P_8.5.56
TLF35584xxVS2 IROT = 5.5 mA
Reset output, low level VROT, low – – 0.4 V VQUC = 3.3 V, P_8.5.57
TLF35584xxVS2 IROT = 3 mA
Reset output fall time 2) tROT, fall – – 25 ns CROT,load = 50 pF P_8.5.58
Interrupt output INT
Interrupt output, high level VINT, high 4.0 – – V VQUC = 5.0 V, P_8.5.59
TLF35584xxVS1 IINT = -9 mA
Interrupt output, low level VINT, low – – 0.7 V VQUC = 5.0 V P_8.5.60
TLF35584xxVS1 IINT = 7 mA
Interrupt output, high level VINT, high 2.3 – – V VQUC = 3.3 V P_8.5.61
TLF35584xxVS2 IINT = -7 mA
Interrupt output, low level VINT, low – – 0.7 V VQUC = 3.3 V P_8.5.62
TLF35584xxVS2 IINT = 5.5 mA
Interrupt output rise time 2) tINT, rise – – 25 ns CINT,load = 50 pF P_8.5.63

Interrupt output fall time 2) tINT, fall – – 25 ns CINT,load = 50 pF P_8.5.64

1) Due to internal delays the reset delay time can be enlarged by max 50µs. Please consider the transition time into INIT
state tr,INIT specified in Table 11-8 prior to the power sequencing started by entering INIT state.
2) Specified by design, not subject to production test

Data Sheet 82 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

9 Standby LDO and Internal Supplies

9.1 Standby LDO:

9.1.1 Functional description

The standby regulator LDO_STBY is independent from the pre regulator stage and the other post regulators. It
might be switched ON or OFF in all states (for details please refer to chapter State Machine). The linear low drop
regulator LDO_STBY offers a precise 3.3 V (or 5.0 V, equal to LDO_µC) output voltage for standby supply.
The LDO_STBY will keep its state by leaving the STANDBY state according to its previous configuration. For
STANDBY state, the status of LDO_STBY (ON or OFF) has to be defined in previous states.
The regulator is supplied from pin VST. Depending on the needs of the application pin VST might be connected
directly to battery voltage (protected by reverse polarity diode) or to the output of the step up pre regulator (pin
VSx). The output voltage VQST (at pin QST) is controlled by the error amplifier. The actual value is compared to a
reference voltage derived from band gap 1 for regulators. The stability of the control loop is depending on the load
current, the characteristics of the output capacitor and the chip temperature. To ensure stable operation the output
capacitor should be chosen according the specified requirements (capacitance value and electrical series
resistance ESR) in table “Electrical characteristics”.
Protection circuitry is installed to prevent the regulator and the application from damage:
• To protect the pass element from overstress the current limitation will limit the output current to the maximum
specified limit. Current sensing is done via a current mirror, no sense resistor is used. In case the maximum
current should occur, it will be limited., thus the output voltage will decrease. The regulator is protected against
short circuit to ground.
• The output voltage is monitored by the voltage monitoring. In case of over voltage at pin QST, the LDO_STBY
will be switched off and the device will move into FAILSAFE state. The event will be stored in an SPI status
register (MONSF1). In case of under voltage at pin QST, the device will move into INIT state, pin ROT will be
pulled low and the event will be stored in an SPI status register (MONSF2). The regulator will not be switched
off in case of output under voltage, which is shorter than the short to ground detection time tStG. If the under
voltage should be present for more than tStG, the device will move into FAILSAFE state. This event will be
stored in an SPI status register as well (MONSF0).
• There is no dedicated temperature sensor for this regulator. The temperature is sensed on the chip by other
temperature sensors located at LDO_µC and step down pre regulator. In case of the chip temperature will
exceed the pre warning threshold, an interrupt will indicate this event and it will be stored in an SPI status
register (OTFAIL). If the chip temperature will exceed the temperature shutdown threshold, the post regulator
will be switched off. The temperature switch off time will be at least one second. An overload at LDO STBY
(over current detected for more than 1ms) will be indicated by interrupt, except if the device is in
STANDBYstate and the event will be stored in SPI status register (OTWRNSF).
The regulator LDO_STBY may be configured to be ON or OFF in every state, except FAILSAFE. The selection
for STANDBY state shall be done by SPI command before entering this state.

For further details please refer to Chapter 11 State Machine.

Data Sheet 83 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

Reset
function
VST QST

VVS or VBat VQST

Overvoltage
shutdown

Current
limitation

SPI: On/Off
VRef_LDO_STBY
Gate Driver Error Amplifier
Bandgap 1 for
Regulator block

Figure 23 Low drop linear regulator for standby supply

9.1.2 Electrical characteristics

Table 16 Electrical characteristics: Standby LDO

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Standby LDO
Output voltage VQST 4.8 5.0 5.2 V 0 mA ≤ IQST≤ 10 mA P_9.1.1
TLF35584xxVS1

Output voltage VQST 3.17 3.3 3.43 V 0 mA < IQST< 10 mA P_9.1.2

TLF35584xxVS2

Output current limitation IQST, max 15 – 40 mA – P_9.1.3

Drop voltage Vdr, QST – – 400 mV – P_9.1.4

Load regulation ∆VQST, load – 25 40 mV IQST = 100 µA to P_9.1.5

TLF35584xxVS1 10 mA

Load regulation ∆VQST, load – 20 40 mV IQST = 100 µA to P_9.1.6

TLF35584xxVS2 10 mA

Data Sheet 84 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

Line regulation ∆VQST, line – 0.1 0.5 mV/V – P_9.1.7

TLF35584xxVS1

Line regulation ∆VQST, line – 0.1 0.5 mV/V – P_9.1.8

TLF35584xxVS2
Table 16 Electrical characteristics: Standby LDO (cont’d)
VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

Power supply ripple rejection PSRRQST 40 – – dB fripple = 100 kHz P_9.1.9

1)

ESRCQST ≤ 100mΩ
Output capacitor CQST 0.47 – 10 µF 1) P_9.1.10

Output capacitor, ESR ESR CQST 0 – 200 mΩ 1) P_9.1.11

1) Specified by design, not subject to production test

9.1.3 Typical Performance Characteristics

QST Output Voltage VQST versus
Junction Temperature Tj (TLF35584xxVS1)
QST Output Voltage VQST versus

Data Sheet 85 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

Junction Temperature Tj (TLF35584xxVS2)
QST Output Voltage VQST versus QST Output Voltage VQST versus
Supply Voltage VVS (TLF35584xxVS1) Supply Voltage VVS (TLF35584xxVS2)

5.05 3.33
TLF35584xxVS1 TLF35584xxVS2
5.04 VQST,nom = 5.0V VQST,nom = 3.3V
VVS = 14 V VVS = 14 V
3.32
5.03

5.02 3.31

5.01
3.3
5

4.99
3.29
4.98

4.97 3.28

IQST = 1 mA IQST = 1 mA
4.96
IQST = 3 mA IQST = 3 mA
3.27
4.95 IQST = 6 mA IQST = 6 mA
IQST = 10 mA IQST = 10 mA
3.26
−50 0 50 100 150 −50 0 50 100 150
Tj [°C] Tj [°C]

Data Sheet 86 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

5.05 3.33
TLF35584xxVS1 TLF35584xxVS2
5.04 VQST,nom = 5.0V VQST,nom = 3.3V
IQST = 1mA IQST = 1mA
3.32
5.03

5.02 3.31

5.01
3.3
5

4.99
3.29
4.98

4.97 3.28

4.96 Tj = −40 °C Tj = −40 °C

3.27
Tj = 25 °C Tj = 25 °C
4.95
Tj = 150 °C Tj = 150 °C
3.26
5 10 15 20 25 30 35 40
5 10 15 20 25 30 35 40 V [V]
V [V] VS
VS
QST Output Voltage VQST versus
Load Current IQST (TLF35584xxVS1)
QST Output Voltage VQST versus
Load Current IQST (TLF35584xxVS2)
5.05 3.33
TLF35584xxVS1 TLF35584xxVS2
5.04 VQST,nom = 5.0V VQST,nom = 3.3V
VVS = 14 V VVS = 14 V
3.32
5.03

5.02 3.31

5.01
3.3
5

4.99
3.29
4.98

4.97 3.28

4.96 Tj = −40 °C Tj = −40 °C

3.27
Tj = 25 °C Tj = 25 °C
4.95
Tj = 150 °C Tj = 150 °C
3.26
0 2 4 6 8 10
0 2 4 6 8 10 IQST [mA]
I [mA]
QST dr,QST versus
QST Dropout Voltage V
QST Dropout Voltage Vdr,QST versus Load
Current IQST (TLF35584xxVS1)

Data Sheet 87 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

Load Current IQST (TLF35584xxVS2) QST
Dynamic Load Response (0mA to 5mA)
TLF35584xxVS1 (VQST,nom = 5.0 V)
QST Dynamic Load Response (0mA to 5mA)

180 350
TLF35584xxVS1 TLF35584xxVS2
VQST,nom = 5.0V VQST,nom = 3.3V
160
300

140
250
120

200
100

80
150

60
100
40
Tj = −40 °C Tj = −40 °C
50
20 Tj = 25 °C Tj = 25 °C
Tj = 150 °C Tj = 150 °C
0 0
0 2 4 6 8 10 0 2 4 6 8 10
I [mA] QST I [mA] QST

Data Sheet 88 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

TLF35584xxVS2 (VQST,nom = 3.3 V)

Data Sheet 89 Rev. 2.0, 2017-03-16

 TLF35584

Standby LDO and Internal Supplies

9.2 Internal Supplies
The TLF35584 includes internal voltage supplies and bias currents to operate all regulators, monitoring and logic
functions. These internal supplies are monitored internally to ensure proper functionality of the functional blocks
the TLF35584 provides. The device will react on internal failure conditions as described in the State Machine,
Monitoring Function, Interrupt Generation and Safe State Control Function.
The internal regulators do not require external components (i.e capacitors). The internal voltages are not visible
at any pin.

Data Sheet 90 Rev. 2.0, 2017-03-16

 TLF35584

Wake Up Timer

10 Wake Up Timer

10.1 Description
The wake up timer is a function to wake up the TLF35584.
The wake up timer value may be set by SPI in INIT, NORMAL and WAKE state. The value is stored in the 24 bit
wide wake up timer register (WKTIMCFG0, WKTIMCFG1, WKTIMCFG2).
The wake up timer is implemented as a 24 bit counter which is clocked by a 100 kHz or 100 Hz clock (time-base).
The time-base may be selected via SPI.
For the chosen time-base of 100 kHz the timer resolution is 10 µs and a wake up time between 10 µs to 168 s
can be configured via SPI.1)
For the chosen time-base of 100 Hz the timer resolution is 10 ms and a wake up time between 10 ms to 1.9 days
can be configured via SPI.
When entering STANDBY or SLEEP state, the counter is loaded with the value of the wake up timer register and
starts decrementing. At underflow, the timer will wake up the device from either SLEEP or STANDBY state. When
leaving SLEEP state, an interrupt will be generated.

Interrupt

100 kHz 24 bit counter

System
/1000 wake up

Time-base Run Counter value

SPI

Figure 24 Wake up timer principle

Wake Up Timer

1 ) An additional activation delay time for the start of the wake up timer of max. 40 µs has to be considered after entering
SLEEP or STANDBY state.

Data Sheet 91 Rev. 2.0, 2017-03-16

 TLF35584

State Machine
10.2 Electrical Characteristics

Table 17 Electrical Characteristics: Wake up timer

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
Wake up timer
Time base, resolution 9.5 10 10.5 µs 1) P_10.2.1
tWakeUpTimer
Time base, resolution tWakeUpTimer 9.5 10 10.5 ms – P_10.2.2

Counter - 24 - bit 2) P_10.2.3

C
1) Due to internal delays the wake-up time can be enlarged by max 50µs.
2) Specified by design, not subject to production test

11 State Machine

11.1 Introduction
The state machine describes the different states of operation, the device may get into. The following figure shows
the state machine flow diagram, for detailed information please refer to following pages.

Data Sheet 92 Rev. 2.0, 2017-03-16

 TLF35584

Figure 25 Flow Diagram State Machine

Data Sheet 93 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Description:
• ON /OFF:= Switched ON or OFF, not configurable by SPI command
• ON*:= Switched ON by entering the INIT state, then selectable via SPI
• SELECTED:= May be configured (switched ON or OFF) by SPI command in previous state or is selected by
the state transition request (DEVCTRL) in case of LDO configuration for SLEEP state.
• SELECTABLE:= May be switched ON or OFF by SPI command in this state
• SELECTABLE**:= Switched ON by default after POR, then selectable via SPI
• ADJUSTED:= Defined present or not present by configuration pin, not configurable by SPI command
• ACTIVE:= as described in INIT-State
• SSC, SS1&2:= Safe State Control signals 1 and 2
• LOW:= Signal is low
• HIGH:= Signal is high
• OV:= Over voltage
• UV:= Under voltage
• StG:= Short to ground
• TSD:= Thermal shut down
• OC:= Over current
• ABIST:= Analog built in self test
• Comp BG1 <-> BG2 > 4%: The difference between both band gaps 1 and 2 is more than 4%

11.2 Description of States

11.2.1 POWERDOWN-state
The device is in POWERDOWN-state as long the Power-on-Reset (POR) is not released.

POWERDOWN
LDO_Stby Error Monitoring PreReg

OFF OFF OFF

LDO_μC LDO_Com Core_Sup adj

OFF OFF OFF

Volt_Ref Tr 1 & 2 Wakeup-T
OFF OFF OFF
WatchDogs RESET SSC, SS1&2
OFF LOW LOW
Figure 26 POWERDOWN-state

Table 11-1 POWERDOWN-state Settings

Part/Function Value Description

Data Sheet 94 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

LDO_Stby OFF • The LDO_Stby is off

PreReg OFF • The pre regulators are off
LDO_µC OFF • The LDO_µC is off
LDO_Com OFF • The LDO_Com is off
Core_Sup adj. OFF • The function Core_Sup adj. is off
Volt_Ref OFF • The voltage reference is off
Tr.1 & 2 OFF • Both trackers 1 & 2 are off
Wake-up-T. OFF • The wake-up timer is off
Watchdogs OFF • The watchdogs are off
Error monitoring OFF • The Error monitoring is off
RESET LOW • The reset output is low
SSC, SS1&2 LOW • Both safe state signals are LOW and the application is in safe state
11.2.2 INIT-state
During INIT-state the device expects valid communication with the µC within the INIT timer. Otherwise an
initialization timeout will occur. The INIT timer starts with the rising edge of ROT. The INIT timer is stopped as
soon as three boundary conditions are fulfilled:
• Valid SPI communication received from µC
• Watchdog(s) serviced once according to default configuration or according to reconfiguration
• ERR monitoring serviced properly (minimum 3 periods provided) or configured to be OFF

INIT
LDO_Stby Error Monitoring PreReg
SELECTABLE** ON* ON
LDO_μC LDO_Com Core_Sup adj

ON ON* ADJUSTED
Volt_Ref Tr 1 & 2 Wakeup-T
ON* ON* OFF
WatchDogs RESET SSC, SS1&2
ON* ACTIVE LOW
Figure 27 INIT-state

Part/Function Value Description

LDO_Stby SELECTAB • The LDO_Stby is switched on when entering from POWERDOWN-state

LE** • It may be switched on or off by SPI command. This configuration is kept
through all states, except POWERDOWN-state
PreReg ON • The step down pre regulator is on
• Step up pre regulator is active depending on the input voltage and this
option is selected by pin STU.

Data Sheet 95 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

LDO_µC ON • The LDO_µC is on

LDO_Com ON* • The LDO_Com is switched on per default

• The LDO_Com may be switched off and on by SPI
Core_Sup adj. ADJUSTED • The Core_Sup adj. is switched ON or OFF depending on pin SEC
(SEC pin considered only during power-sequencing)
Volt_Ref ON* • The Volt_Ref is switched on per default
• The Volt_Ref may be switched off and on by SPI
Tr.1 & 2 ON* • Both trackers 1 & 2 are switched on per default
• Both trackers 1 & 2 may be switched off and on by SPI independently
Wake-up-T. OFF • The wake-up timer is off

Watchdogs ON* • The window watchdog is switched on per default in SPI triggered mode
• The functional watchdog is switched off per default
• The watchdogs may be configured and switched ON or OFF by SPI
Error monitoring ON • The Error monitoring is switched on per default
• The Error monitoring may be configured and switched ON or OFF by SPI

Table 11-2 INIT-state Settings

Table 11-2 INIT-state Settings (cont’d)
Part/Function Value Description

RESET ACTIVE • The reset output goes HIGH as soon as all µC related output voltages
VQST, VQUC and VVCI are above their under voltage reset
threshold,VRT,XXX,low delayed by the reset delay time tRD.
SSC, SS1&2 LOW • Both safe state signals are LOW and the application is in safe state

11.2.3 NORMAL -state

In NORMAL-state the device is supplying the µC and the applications. Safety and monitoring functions (like
resetblock and safe state control) are active. The µC may configure several post regulators of the device and the
wakeup-timer via SPI command for this state.

NORMAL
LDO_Stby Error PreReg
SELECTABLE Monitoring
ON
SELECTABLE
LDO_μC LDO_Com Core_Sup adj

ON SELECTABLE ADJUSTED
Volt_Ref Tr 1 & 2 Wakeup-T
SELECTABLE SELECTABLE OFF
WatchDogs RESET SSC, SS1&2
SELECTABLE HIGH HIGH

Data Sheet 96 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Figure 28 NORMAL-state

Table 11-3 NORMAL-state Settings

Part/Function Value Description
LDO_Stby SELECTAB • The LDO_Stby may be switched on or off by SPI command.
LE
PreReg ON • The step down pre regulator is on
• Step up pre regulator is active depending on the input voltage and this
option is selected by pin STU.
LDO_µC ON • The LDO_µC is on
LDO_Com SELECTAB • The LDO_Com may be switched on of off by SPI command
LE
Core_Sup adj. ADJUSTED • The Core_Sup adj. is switched ON or OFF depending on pin SEC
(SEC pin considered only during power-sequencing)
Volt_Ref SELECTAB • The Volt_Ref may be switched on of off by SPI command
LE
Tr.1 & 2 SELECTAB • Both trackers 1 & 2 may be switched off and on by SPI independently
LE
Wake-up-T. OFF • The wake-up timer is switched off
Watchdogs SELECTAB • The watchdogs may be configured and switched ON or OFF by SPI
LE
Error monitoring SELECTAB • The Error monitoring may be configured and switched ON or OFF by SPI
LE
RESET HIGH • The reset output is HIGH
SSC, SS1&2 HIGH • Both safe state signals are HIGH
11.2.4 STANDBY-state
The STANDBY-state is a low power state which the µC may enter to reduce the current consumption to a minimum
when the application is not used for a long time. The application is in a safe state.

STANDBY
LDO_Stby Error PreReg
SELECTED Monitoring
OFF
OFF
LDO_μC LDO_Com Core_Sup adj

OFF OFF OFF

Volt_Ref Tr 1 & 2 Wakeup-T
OFF OFF SELECTED
WatchDogs RESET SSC, SS1&2
INACTIVE LOW LOW
Figure 29 STANDBY-state

Table 11-4 STANDBY-state Settings

Data Sheet 97 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Part/Function Value Description

LDO_Stby SELECTED • The LDO_Stby is ON or OFF depending on its configuration
PreReg OFF • The pre regulator are off
LDO_µC OFF • The LDO_µC is off
LDO_Com OFF • The LDO_Com is off
Core_Sup adj. OFF • The function Core_Sup adj. is off
Volt_Ref OFF • The voltage reference is off
Tr.1 & 2 OFF • Both trackers 1 & 2 are off
Wake-up-T. SELECTED • The wake-up timer is ON or OFF depending on its configuration
Watchdogs OFF • The watchdogs are off
Error monitoring OFF • The Error monitoring is off
RESET LOW • The reset output is low
SSC, SS1&2 LOW • Safe state signals 1 and 2 are low
• The application is in a safe state
11.2.5 SLEEP-state
The SLEEP-state is a low power state which the µC may enter to reduce the current consumption when the
application is not used (e.g. micro controller is in STOP mode). The µC may configure the status of regulators and
the safety functions via SPI command in the previous state. The application is in a safe state

SLEEP
LDO_Stby Error Monitoring PreReg
SELECTED SELECTED ON
LDO_μC LDO_Com Core_Sup adj

ON SELECTED ADJUSTED
Volt_Ref Tr 1 & 2 Wakeup-T
SELECTED SELECTED SELECTED
WatchDogs RESET SSC, SS1&2
SELECTED HIGH LOW
Figure 30 SLEEP-state

Table 11-5 SLEEP-state Settings

Part/Function Value Description
LDO_Stby SELECTED • The LDO_Stby is switched ON or OFF according to previous configuration.
PreReg ON • The step down pre regulator is on
• Step up pre regulator is active depending on the input voltage and this
option is selected by pin STU
LDO_µC ON • The LDO_µC is switched on
• In SLEEP-state the device is monitoring the output current of LDO_µC: If
the LDO_µC current exceeds a certain threshold ILDO_µC,att, an interrupt
will be generated and the device will move to WAKE state

Data Sheet 98 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

LDO_Com SELECTED • The LDO_Com is switched ON or OFF depending on the configuration by

the state transition request to move into SLEEP and cannot be changed
in SLEEP state.
Core_Sup adj. ADJUSTED • The Core_Sup adj. is switched ON or OFF depending on pin SEC
(SEC pin considered only during power-sequencing)
Volt_Ref SELECTED • The Volt_Ref is switched ON or OFF depending on the configuration by the
state transition request to move into SLEEP and cannot be changed in
SLEEP state.
Tr.1 & 2 SELECTED • The trackers are switched ON or OFF depending on the configuration by the
state transition request to move into SLEEP and cannot be changed in
SLEEP-state
Wake-up-T. SELECTED • The wake-up timer is ON or OFF depending on its configuration
Watchdogs SELECTED • The watchdogs are ON or OFF depending on their configuration for SLEEP
Error monitoring SELECTED • The Error monitoring is ON or OFF depending on its configuration for
SLEEP
RESET HIGH • The reset output is HIGH
SSC, SS1&2 LOW • Both safe state signals are LOW and the application is in safe state
11.2.6 WAKE-state
The WAKE-state is an intermediate state between NORMAL and the low power states SLEEP and STANDBY.
This state provides the same functionality as the NORMAL state, but shall ensure the application being in safe
state by keeping low the safe state outputs. It should be used to prepare the system for a correct and safe reentry
to the NORMAL state by servicing the watchdogs and the error monitoring (minimum 3 periods) according to the
selected configuration. Furthermore it provides the possibility to move the device into the low power states SLEEP
and STANDBY.
The TLF35584 moves from SLEEP or from the transition to SLEEP into WAKE state, if the output current from
LDO_µC exceeds a certain threshold ILDO_µC,att, an valid ENA or WAK signal is recognized or the SPI command
GoToWake is sent. Another transition into WAKE state is initiated by the usage of the ABIST in NORMAL state.
By entering the state an interrupt is generated and the supervision functions (watchdogs and ERR monitoring) will
become active according to their previous configuration in NORMAL state. Upon entering the WAKE-state the
configuration of the LDOs resumes to the one of the previous NORMAL state. The application is in a safe state

WAKE
LDO_Stby Error PreReg
SELECTABLE Monitoring
ON
SELECTABLE
LDO_μC LDO_Com Core_Sup adj

ON SELECTABLE ADJUSTED
Volt_Ref Tr 1 & 2 Wakeup-T
SELECTABLE SELECTABLE OFF
WatchDogs RESET SSC, SS1&2
SELECTABLE ACTIVE LOW
Figure 31 WAKE-state

Data Sheet 99 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Table 11-6 WAKE-state Settings

Part/Function Value Description

LDO_Stby SELECTAB • The LDO_Stby may be switched ON or OFF by SPI command.

LE
PreReg ON • The step down pre regulator is on
• Step up pre regulator is active depending on the input voltage and this
option is selected by pin STU.
LDO_µC ON • The LDO_µC is on

LDO_Com SELECTAB • The LDO_Com will be switched ON or OFF depending on its

LE configuration in the NORMAL-state prior to SLEEP-state when entering
WAKE-state
• It may be switched on of off by SPI command
Core_Sup adj. ADJUSTED • The Core_Sup adj. is switched ON or OFF depending on pin SEC
(SEC pin considered only during power-sequencing)
Volt_Ref SELECTAB • The voltage reference will be switched ON or OFF depending on its
LE configuration in NORMAL-state prior to SLEEP-state when entering
WAKE-state
• It may be switched on of off by SPI command
Table 11-6 WAKE-state Settings (cont’d)
Part/Function Value Description

Tr.1 & 2 SELECTAB • Both trackers 1 & 2 will be switched ON or OFF depending on their
LE configuration in NORMAL-state prior to SLEEP-state when entering
WAKE-state
• It may be switched on of off by SPI command
Wake-up-T. OFF • The wake-up timer is switched off

Watchdogs SELECTAB • The watchdogs will be switched ON or OFF depending on their

LE configuration in NORMAL-State prior to SLEEP-state when entering
WAKE-State
• The watchdogs may be configured and switched ON or OFF by SPI
Error monitoring SELECTAB • The Error monitoring will be switched ON or OFF depending on the
LE configuration in NORMAL-state prior to SLEEP-state when entering
WAKE-state
• The Error monitoring may be configured and switched ON or OFF by SPI
RESET HIGH • The reset output is HIGH

SSC, SS1&2 LOW • Both safe state signals are LOW and the application is in safe state

11.2.7 FAILSAFE-state
FAILSAFE-state occurs after the detection of a severe failure. In FAILSAFE-state all regulators are switched off.
The application is in a safe state.

Data Sheet 100 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

FAILSAFE
LDO_Stby Error Monitoring PreReg

OFF OFF OFF

LDO_μC LDO_Com Core_Sup adj

OFF OFF OFF

Volt_Ref Tr 1 & 2 Wakeup-T
OFF OFF OFF
WatchDogs RESET SSC, SS1&2
OFF LOW LOW
Figure 32 Fail safe-state

Table 11-7 FAILSAFE-state Settings

Part/Function Value Description
LDO_Stby OFF • The LDO_Stby is off
PreReg OFF • The pre regulators are off
LDO_µC OFF • The LDO_µC is off
LDO_Com OFF • The LDO_Com is off
Core_Sup adj. OFF • The function Core_Sup adj. is off
Volt_Ref OFF • The voltage reference is off
Tr.1 & 2 OFF • Both trackers 1 & 2 are off
Wake-up-T. OFF • The wake-up timer is off
Watchdogs OFF • The watchdogs are off
Error monitoring OFF • The Error monitoring is off
RESET LOW • The reset output is low
SSC, SS1&2 LOW • Both safe state signals are LOW and the application is in safe state
11.3 Transition Between States
State transitions requested via SPI command are initiated with a valid positive going edge of the chip select (SCS).

11.3.1 POWERDOWN -> INIT-state

The device moves from POWERDOWN to INIT-state when the Power-on-Reset (POR) is released. The POR is
only released when all of the following conditions are met:
• VVS above VPD,hi when increasing
• no under or over voltage on internal supplies

Data Sheet 101 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.3.2 INIT -> NORMAL-state

Prerequisites:
• Watchdog(s) need to be serviced once according to default configuration or according to reconfiguration within
the INIT timer
• ERR monitor needs to be serviced with a valid signal (minimum 3 periods) or disabled within the INIT timer.
• If functional watchdog is activated, a valid FWD triggering needs to be provided.
• A delay of 60µs after the provided services has to be considered to ensure proper release of internal validation
signals.

Triggering Events:
• State transition is only initiated by the SPI command “Go to NORMAL”.

Exceptions:
• none

Timing Description:

Data Sheet 102 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

INIT NORMAL

SCS
> 60μs

Open Window Closed Window Closed Window

WWD

Error
monitoring

ROT

SS1

SS2

Figure 33 Transition from INIT to NORMAL state

• A valid SPI command “Go to NORMAL” (valid with chip select high at pin SCS) will move the device from INIT
state to NORMAL state.
• Reset pin ROT stays HIGH as the post regulators are already active in INIT state.
• With the positive edge of chip select high (at pin SCS) the safe state signals SS1 and SS2 are pulled to HIGH
at same time. (Internal reaction time for the safe state outputs according to Table 18 has to be considered)
11.3.3 Movements between NORMAL and SLEEP state

11.3.3.1 NORMAL -> SLEEP-state

Prerequisites:
• Selection of LDO_µC current monitor or absolute transition timer.
• Transition delay timer ttr,del needs to be configured or default is used.
• Optionally LDO_µC current threshold needs to be defined or default is used.

Triggering Events:

Data Sheet 103 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• State transition is only initiated by the SPI command “Go to SLEEP”.

Exceptions:
• If a valid ENA (edge) or WAK (level) signal is detected in the transition state to SLEEP state, the device will
move to the WAKE state and send an interrupt (at pin INT)
• If the LDO_µC current monitor is activated and the current consumption of the microcontroller is not below the
selected LDO_µC current threshold before the transition delay timer ttr,del has expired, the device will move to
the WAKE state and send an interrupt (at pin INT)
Timing Diagram
NORMAL Transition SLEEP

FWD Service
FWD
Open
Closed Window
Window
WWD

SCS

Error
monitoring

ROT

I LDO_μC,att
I LDO_μC

SS1

SS2

t
Δt SS2
Last
Watchdog
Service t tr,del

Figure 34 Transition from NORMAL to SLEEP state

• Before the SPI command “Go to SLEEP” is applied, the watchdog(s) - if in use should be serviced, so that the
positive edge of SCS signal is well in between the “closed window” of the window watchdog. This is
recommended to avoid interference between a missing watchdog trigger and the transition command “Go to
SLEEP”
• The positive edge of chip select (pin SCS) after the SPI command “Go to SLEEP” initiates the transition. With
chip select high the safe state signal SS1 is pulled to zero and the device leaves NORMAL state and enters
the transition state (to SLEEP state). (Internal reaction time for the safe state outputs according to Table 18
has to be considered)

Data Sheet 104 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• With chip select (pin SCS) high the error monitoring (pin ERR) is stopped - the toggling may end with the
positive edge at pin SCS. If the error monitoring should be selected to be active in SLEEP state continuos
toggling is mandatory.
• The monitoring of window watchdog and functional watchdog is stopped with the positive edge at pin SCS. If
one or both watchdogs should be selected to be active in SLEEP state continuos watchdog service is
mandatory.
• Reset pin ROT stays HIGH as the post regulators are not switched off.
• In case the absolute transition timer is selected, the device moves from transition state to SLEEP state after
the transition delay time ttr,del. The transition time ttr,del can be determined by SPI command between 100 µs
to 1.6 ms, the default setting is 900 µs. After this transition time it should be ensured that the µC current
consumption has fallen below the LDO_µC monitoring threshold ILDO_µC,att to keep the device in SLEEP state.
• If the LDO_µC current monitor is enabled the µC current out of pin QUC must fall below the LDO_µC
monitoring threshold ILDO_µC,att within the configured maximum transition time ttr,del in DEVCFG0.TRDEL. The
time for the transition is depending, how long it takes that the µC current falls below the LDO_µC monitoring
threshold ILDO_µC,att , if it is below the transition is done.
• After delay time ΔtSS2 the safe state signal SS2 goes to zero. The adjusted delay time ΔtSS2 is independent
from the transition delay time ttr,del.

11.3.3.2 SLEEP -> WAKE-state

Prerequisites:
• none

Triggering Events:
• SPI command “Go to WAKE”.
• Valid Wake-Signal (ENA or WAK).
• Current of LDO_µC exceeding the configured threshold.
• Wake-up timer expired, if enabled

Data Sheet 105 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Exceptions:
• none

Timing Diagram

SLEEP WAKE

I LDO_μC,att
I LDO_μC

INT

FWD Service
FWD

First Open Window Closed Window

WWD

Error
monitoring

ROT

SS1

SS2

ERR Pin Timeout ~10ms

FIrst
Watchdog
Service

Figure 35 Transition from SLEEP to WAKE state

• The state transition is completed without a transition time and is indicated by an interrupt at pin INT. The
triggering event for the transition from SLEEP can be read from the status register WKSF.
• All three monitoring functions (window watchdog, functional watchdog and error monitoring) will recover to the
condition active or inactive (switched off) as they were in the NORMAL state previous to the SLEEP state.
• The configuration of the LDOs will recover to the condition active or inactive (switched off) as they were in the
NORMAL state previous to the SLEEP state.
• In case the window watchdog was active in the previous NORMAL state, with the negative edge of interrupt
signal (at pin INT) the window watchdog will open the first Open Window, the time of this first Open Window
depends on the configured cycle time and is 600 ms (WDCYC = 1) or 60 ms (WDCYC = 0) (if the window
watchdog has not been active in SLEEP state) and requires service. If the window watchdog has been active
in SLEEP state continuos service is mandatory.
• In case the functional watchdog was active in the previous NORMAL state, with the negative edge of interrupt
signal (at pin INT) the functional watchdog will start the heartbeat timer and require service. If the functional
watchdog has been active in SLEEP state continuos service is mandatory.

Data Sheet 106 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• In case the ERR pin monitoring was active in the previous NORMAL state, with the negative edge of interrupt
signal (at pin INT) the error monitoring will become active again. Latest 10 ms after the activation a toggling
signal (with at least three periods past) at pin ERR is required. If the error monitoring has been active in SLEEP
state continuos toggling is mandatory.
• Reset pin ROT stays HIGH as the post regulators are active in SLEEP state and in WAKE state.
• The safe signals SS1 and SS2 will stay LOW in SLEEP and in WAKE state.
• If all active monitoring functions (window watchdog, functional watchdog and error monitoring) are serviced
properly in WAKE state, you may stay in WAKE state as long as you want.
• If all three monitoring functions (window watchdog, functional watchdog and error monitoring) are inactive
(switched off) in WAKE state, you may stay in WAKE state as long as you want.
11.3.3.3 WAKE -> SLEEP state

Prerequisites:
• Selection of LDO_µC current monitor or absolute transition timer.
• Transition delay timer ttr,del needs to be configured or default is used.
• Optionally LDO_µC current threshold needs to be defined or default is used.

Triggering Events:
• State transition is only initiated by the SPI command “Go to SLEEP”.

Exceptions:
• If a valid ENA (edge) or WAK (level) signal is detected in the transition state to SLEEP state, the device will
move back to the WAKE state and send an interrupt (at pin INT)
• If the LDO_µC current monitor is activated and the current consumption of the microcontroller is not below the
selected LDO_µC current threshold before the transition delay timer ttr,del has expired, the device will move
back to the WAKE state and send an interrupt (at pin INT)

Timing Diagram

Data Sheet 107 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

WAKE Transition SLEEP

FWD Service
FWD
Open
Closed Window
Window
WWD

SCS

Error
monitoring

ROT

I LDO_μC,att
I LDO_μC

SS1

SS2

t
Last t tr,del
Watchdog
Service
Figure 36 Transition from WAKE to SLEEP state

• Before the SPI command “Go to SLEEP” is applied, the watchdog(s) - if in use should be serviced, so that the
positive edge of SCS signal is well in between the “closed window” of the window watchdog. This is
recommended to avoid interference between a missing watchdog trigger and the transition command “Go to
SLEEP”
• The positive edge of chip select (pin SCS) after the SPI command “Go to SLEEP” initiates the transition. With
chip select high the device leaves WAKE state and enters the transition state (to SLEEP state).
• With chip select (pin SCS) high the error monitoring (pin ERR) is stopped - the toggling may end with the
positive edge at pin SCS. If the error monitoring should be selected to be active in SLEEP state continuos
toggling is mandatory.
• The monitoring of window watchdog and functional watchdog is stopped with the positive edge at pin SCS. If
one or both watchdogs should be selected to be active in SLEEP state continuos watchdog service is
mandatory.
• Reset pin ROT stays HIGH as the post regulators are not switched off.
• If the LDO_µC current monitor is enabled the µC current out of pin QUC must fall below the LDO_µC
monitoring threshold ILDO_µC,att within the configured maximum transition delay time ttr,del. The time for the
transition is depending, how long it takes that the µC current falls below the LDO_µC monitoring threshold
ILDO_µC,att , if it is below the transition is done.
• Safe state signals SS1 and SS2 stay LOW all the time.

Data Sheet 108 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.3.4 Movements between NORMAL and STANDBY state

11.3.4.1 NORMAL -> STANDBY-state

Prerequisites:
• Selection of LDO_µC current monitor or absolute transition timer.
• Transition timer needs to be configured or default is used.
• Optionally LDO_µC current threshold needs to be defined or default is used.

Triggering Events:
• State transition is only initiated by the SPI command “Go to STANDBY”.

Exceptions:
• If a valid ENA (edge) or WAK (level) signal is detected in the transition state to STANDBY state, the device
will move to the INIT state and a reset (ROT) is generated.
• If the LDO_µC current monitor is activated and the current consumption of the microcontroller is not below the
selected LDO_µC current threshold before the transition delay timer ttr,del has expired, the device will move to
the INIT state and a reset (ROT) is generated.
Timing Diagram:

Data Sheet 109 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

NORMAL Transition STANDBY

FWD Service
FWD
Open
Window
WWD

SCS

Error
monitoring

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2

t
t tr,del
Last
Watchdog
Service

Figure 37 Transition from NORMAL to STANDBY state

• Before the SPI command “Go to STANDBY” is applied, the watchdog(s) - if in use should be serviced, so that
the positive edge of SCS signal is well in between the “closed window” of the window watchdog. This is
recommended to avoid interference between a missing watchdog trigger and the transition command “Go to
STANDBY”
• The positive edge of chip select (pin SCS) after the SPI command “Go to STANDBY” initiates the transition.
With chip select high the safe state signals SS1 and SS2 are pulled to zero without delay between SS1 and
SS2. The device leaves NORMAL state and enters the transition state (to STANDBY state).
(Internal reaction time for the safe state outputs according to Table 18 has to be considered)
• With chip select (pin SCS) high the error monitoring (pin ERR) is stopped - the toggling may end with the
positive edge at pin SCS.
• The monitoring of window watchdog and functional watchdog is stopped with the positive edge at pin SCS.
• With a successful transition from NORMAL to STANDBY state the reset (ROT) is pulled to LOW after the
transition time after chip select (pin SCS) going high.
• All pre regulators and all post regulators (with the exception of the standby LDO - it may be ON or OFF in
STANDBY state) are switched off at the point when the transition is completed after the reset (ROT) is pulled
low.

Data Sheet 110 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• In case the absolute transition timer is selected, the device moves from transition state to STANDBY state
after the transition delay time ttr,del. The transition time ttr,del can be determined by SPI command between 100
µs to
1.6 ms, the default setting is 900 µs.
• In case the LDO_µC current monitor is selected for the transition, the device moves from transition state to
STANDBY state at the point the current consumption measured at the LDO_µC drops below the selected
threshold before the transition delay timer ttr,del has expired.

11.3.4.2 STANDBY -> INIT state

Prerequisites:
• none

Triggering Events:
• Valid ENA (edge) or WAK (level) signal.
• Wake-up timer expired, if enabled

Exceptions:
• none

Timing Diagram

Data Sheet 111 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

STANDBY Transition INIT NORMAL

t ENA,rise

ENA

t WAK,min

WAK

V RT,xxx,low
V QUC and V VCI

ROT

SS1

SS2

t RD t

Figure 38 Transition from STANDBY to INIT state

• All pre regulators and all post regulators are switched on according to the power sequencing, except the
LDO_Stby is kept ON or OFF according to its configuration (simplified in figure above).
• The power on reset delay time is started as soon as the latest of the µC related regulators VQUC or VVCI (if
enabled) crosses the related under voltage reset threshold VRT,xxx,low on the way up.
• After the power on reset delay time has expired the reset (ROT) is set to HIGH.
• The safe signals SS1 and SS2 will stay LOW in STANDBY state and in INIT state.
11.3.4.3 INIT -> NORMAL state

For this state transition please refer to the Chapter 11.3.2.

Data Sheet 112 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.3.5 NORMAL -> WAKE state

For this state transition please refer to the description of ABIST in Chapter 11.6.1.

11.3.6 WAKE -> NORMAL-state

Prerequisites:
• The activated supervision functions (e.g. window watchdog, functional watchdog, ERR pin monitoring) need
to be serviced at least once (minimum 3 periods for ERR monitoring) in the active WAKE state, if they are
restarted/reinitialized in WAKE state (e.g. watchdog being inactive in previous SLEEP state)

Triggering Events:
• State transition is only initiated by the SPI command “Go to NORMAL”.

Exceptions:
• none

Timing Diagram

Data Sheet 113 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

WAKE Transition NORMAL

SCS

FWD Service FWD Service

FWD
Open Open
Closed Window Closed Window
Window Window
WWD

Error
monitoring

ROT

SS1

SS2

t
Figure 39 Transition from WAKE to NORMAL state

• The enable signal will be disregarded. A valid enable (edge) signal will not move the device from WAKE to
NORMAL state.
• The state of wake signal will be disregarded. A valid wake (level) signal will not move the device from WAKE
to NORMAL state.
• The window watchdog (if active in WAKE state) will require continuos service - not synchronized to the
transition from WAKE state to NORMAL state.
• The functional watchdog (if active in WAKE state) will require continuos service - not synchronized to the
transition from WAKE state to NORMAL state.
• The error monitoring (at pin ERR) (if active in WAKE state) will require a continuos toggling signal - not
synchronized to the transition from WAKE state to NORMAL state - but minimum 3 periods detected to enter
accept the movement into NORMAL state.
• Reset pin ROT stays HIGH as the post regulators are active in WAKE state and in NORMAL state.
• With the positive edge of chip select high (at pin SCS) the safe state signals SS1 and SS2 are pulled to HIGH
at same time. (Internal reaction time for the safe state outputs according to Table 18 has to be considered)
11.3.7 WAKE -> STANDBY state

Prerequisites:
• Selection of LDO_µC current monitor or absolute transition timer.
• Transition timer needs to be configured or default is used.

Data Sheet 114 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• Optionally LDO_µC current threshold needs to be defined or default is used.

Triggering Events:
• State transition is only initiated by the SPI command “Go to STANDBY”.

Exceptions:
• If a valid ENA (edge) or WAK (level) signal is detected in the transition state to STANDBY state, the device
will move to the INIT state and a reset (ROT) is generated.
• If the LDO_µC current monitor is activated and the current consumption of the microcontroller is not below the
selected current threshold before the transition timer has expired, the device will move to the INIT state and a
reset (ROT) is generated.

Timing Diagram:

WAKE Transition STANDBY

FWD Service
FWD
Open
Window
WWD

SCS

Error
monitoring

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2

t
t tr,del
Last
Watchdog
Service

Figure 40 Transition from WAKE to STANDBY state

Data Sheet 115 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• Before the SPI command “Go to STANDBY” is applied, the watchdog(s) - if in use should be serviced, so that
the positive edge of SCS signal is well in between the “closed window” of the window watchdog. This is
recommended to avoid interference between a missing watchdog trigger and the transition command “Go to
STANDBY”
• The positive edge of chip select (pin SCS) after the SPI command “Go to STANDBY” initiates the transition.
In the WAKE state the safe state signals SS1 and SS2 are LOW and will be kept LOW for the transition to
STANDBY. The device leaves WAKE state and enters the transition state (to STANDBY state).
• With chip select (pin SCS) high the error monitoring (pin ERR) is stopped - the toggling may end with the
positive edge at pin SCS.
• The monitoring of window watchdog and functional watchdog is stopped with the positive edge at pin SCS.
• With a successful transition from WAKE to STANDBY state the reset (ROT) is pulled to LOW after the transition
time after chip select (pin SCS) going high.
• All pre regulators and all post regulators (with the exception of the standby LDO - it may be ON or OFF in
STANDBY state) are switched off at the point when the transition is completed after the reset (ROT) is pulled
low.
• In case the absolute transition timer is selected, the device moves from transition state to STANDBY state
after the transition time ttr,del. The transition time ttr,del can be determined by SPI command between 100 µs to
1.6 ms, the default setting is 900 µs.
• In case the LDO_µC current monitor is selected for the transition, the device moves from transition state to
STANDBY state at the point the current consumption measured at the LDO_µC drops below the selected
threshold before the transition delay timer ttr,del has expired.

11.3.8 FAILSAFE -> INIT state

Prerequisites:
• FAILSAFE timer has expired.

Triggering Events:
• Self triggered transition after the prerequisite is fulfilled.

Data Sheet 116 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• Valid ENA (edge) or WAK (level) signal (only needed if exception true)

Exceptions:
• In case the FAILSAFE is entered three times in a row with the same failure the self-triggered transition is
blocked.

Timing Diagram

FAILSAFE
SLEEP INIT

t ENA,rise

ENA

t WAK,min

WAK

Timer
expired

V RT,xxx,low
V QUC , V VCI and V QST ( if enabled )

ROT

SS1

SS2
t
t FAILSAFE,min t RD

Figure 41 Transition from FAILSAFE to INIT state

• The device transition from FAILSAFE state to INIT state happens earliest after the minimum FAILSAFE time
tFAILSAFE,min, which is 20 ms for all failures except a thermal shutdown. In case of a thermal shutdown the
minimum FAILSAFE time tFAILSAFE,min is 1s. A command to transition before the minimum FAILSAFE time
tFAILSAFE,min has expired, will not be executed.
• After entering INIT state the voltage regulators will ramp up according to the power sequencing.
• The power on reset delay time is started as soon as the latest of the µC related regulators VQUC, VVCI or VQST
(according to the previous configuration) crosses the related under voltage reset threshold VRT,xxx,low on the
way up.
• After the power on reset delay time has expired the reset (ROT) is set to HIGH.
• The device needs to be configured and initiated. All settings done in the configuration registers before the
device went into FAILSAFE state are lost, except the configuration of the LDO_Stby (RSYSPCFG0) and the
reset delay time (DEVCFG1).
• The safe state signal SS1 and SS2 are LOW in FAILSAFE state and will be LOW in INIT state

Data Sheet 117 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.4 Reaction on detected faults

Errors are classified according to their severity into 4 different error classes:
• Stay in Current State - Failures affecting peripherals without direct risk for the microcontroller, that are
indicated by an interrupt to allow analysis by the microcontroller without changing the state.
• Move to INIT - Medium severity errors that brings the device back to INIT state and generate a reset for the
microcontroller.
• Move to FAILSAFE - Critical error with high risk of damaging the microcontroller.
• Move to POWERDOWN - Most critical error with high risk of damaging ourself plus the microcontroller
The error classes are overruled according to their severity, e.g. movement to POWERDOWN takes precedence
over movement to FAILSAFE which takes precedence over movement to INIT.
The move to INIT, FAILSAFE and POWERDOWN errors are named “error triggered state transitions” in this
document.

11.4.1 Stay in current State

Stay in current State

Volt_Ref: UV, StG, OC
Tr 1 & 2: OV, UV, StG
LDO_Com: OV,UV,StG, TSD
PreReg: UV
LDO_Stby: OC
Watchdog Error Counter (WWD/FWD)
increased
Error Monitoring Recovery delay time active
TSD prewarning
Comp BG1 <-> BG2 > 4%

Figure 42 Stay in current State

The following failures will not trigger a movement of the device to another state by themselves, but will indicate
the failure by an interrupt event:
• Detection of under voltage or a short to ground or overload detection at voltage reference
• Detection of over voltage, under voltage or a short to ground at trackers 1 or 2
• Detection of over voltage, under voltage, a short to ground or thermal shutdown at LDO_Com
• Detection of under voltage at pre regulator.
• Detection of overload at standby regulator
• Increase of window/functional watchdog status counter, but actual value still stays below the threshold
• Error monitoring recovery delay time is active and ERR signal stops toggling.
• Thermal shutdown pre warning (Step down pre regulator or/and LDO_µC or/and LDO_Com)
• Bandgap monitoring: If the deviation between both bandgaps is larger than 4%

Data Sheet 118 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

The interrupt may not be visible on the INT pin in STANDBY and FAILSAFE state due to microcontroller supplies
being switched off. The event is stored in the status flags (IF, SYSSF, MONSF0, MONSF1, MONSF2, OTWRNSF,
OTFAIL).
11.4.2 Transition into INIT State

Move to INIT State

LDO_μC: UV
CORE_Sup adj.: UV
LDO_Stby: UV
Watchdog Error
Counter (WWD/FWD) Overflow
Error Monitoring triggered
INIT timer expired

Figure 43 Move to INIT State

The following failures will bring the device from any state to INIT-state:
• Detection of under voltage at LDO_µC, Core_Sup adj. or LDO_Stby
• Detection of window/functional watchdog status counter overflow
• Stop of error signal detected (immediate reaction mode) or stop or error signal detected for more than recovery
delay time (recovery mode)
• One or two consecutive expires of the INIT timer (configuration in INIT state failed)
11.4.2.1 INIT -> INIT state due to detected fault

11.4.2.1.1 INIT -> INIT-state due to INIT timer expired for the first time

SLEEP
INIT Transition INIT NORMAL

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2

t RD t

Figure 44 Transition from INIT to INIT state - first movement

Description:

Data Sheet 119 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• The device transition from INIT to INIT state (or stays in INIT state) for the first time is issuing a “soft reset”.
Pin ROT is pulled to LOW for the reset delay time tRD in case all µC related voltages are in valid range. The
power sequence is started after entering the INIT state: the disabled outputs are re-activated, the other ones
are kept enabled, except the LDO_Stby will keep its configuration being ON or OFF.
11.4.2.1.2 INIT -> INIT-state due to INIT timer expired for the second time

SLEEP
INIT Transition INIT NORMAL

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2

t SDT t RD t

Figure 45 Transition from INIT to INIT state - second movement

Description:
• The device transition from INIT to INIT state (or stays in INIT state) for the second time is issuing a “hard reset”
- pin ROT is pulled to LOW and all outputs are disabled for the time t and restarted according to the power
sequencing (Please refer to Chapter 8.3), except the LDO_Stby will restore its configuration being ON or OFF.
• The ROT pin will be released according to the power sequencing using the reset delay time trd.
Note:Please refer also to the transition INIT to FAILSAFE

Data Sheet 120 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.4.2.2 NORMAL -> INIT state due to detected fault

Timing Diagram

NORMAL Transition INIT NORMAL

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2

t
< t StG t RD

Δt SS2

Figure46 Transition from NORMAL to INIT state

Description:
• The device transitions from NORMAL into INIT state issuing a “soft reset” - pin ROT is pulled to LOW and all
the outputs are enabled, except the LDO_Stby will keep its configuration being ON or OFF. Outputs that where
disabled in NORMAL state will get switched on again.
• This might be issued by an undervoltage of the µC related voltages VQUC, VQST or VVCI as shown in the figure.
The under voltage is shorter than the short to ground detection time tStG. The reset delay time tRD is started as
soon as all µC related voltages VQUC, VQST or VVCI are back in the valid range. The ROT pin is released
accordingly. An under voltage longer than the short to ground detection time tStG would first lead to a transition
from NORMAL to INIT state and then, after the short to ground detection time tStG has expired, to a transition
from INIT to FAILSAFE state.
• The “soft reset” can also be initiated by a window watchdog error counter overflow (> Σ WWD), a functional
watchdog error counter overflow (> Σ FWO), an error indication (immediate or recovery delay time mode), if
these monitoring functions are in use. In this case the reset delay time tRD will be started falling edge of the
ROT pin. Please consider the state transition time to INIT state in Table 11-8.
• SS1 will be pulled to LOW immediately with pin ROT, SS2 will be pulled to LOW after the selected ΔtSS2.
• Please mind that in case of an UV event on QUC, a delayed SS2 signal will follow VQUC as it is supplied from
QUC.
Note:In case the device is sent back to NORMAL state before the configured ΔtSS2 has expired the SS2 will be
kept HIGH without being set to LOW.

Data Sheet 121 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.4.2.3 STANDBY -> INIT state due to detected fault

Timing Diagram

STANDBY Transition INIT NORMAL

V RT,xxx,low
V QST

ROT

SS1

SS2
t
< t StG t RD

Figure47 Transition from STANDBY to INIT state

Description:
• The device transitions from STANDBY into INIT because of an under voltage of the µC related voltage VQST
as shown in the figure. The under voltage is shorter than the short to ground detection time tStG. An under
voltage longer than the short to ground detection time tStG would first lead to a transition from STANDBY to
INIT state and then, after the short to ground detection time tStG has expired, to a transition from INIT to
FAILSAFE state.
• The power sequence is started after entering the INIT state: the disabled outputs are re-activated, except the
LDO_Stby will keep its configuration being ON or OFF.
• The power on reset delay time is started according to the power sequencing and releases the ROT accordingly.
• The safe state signals SS1 and SS2 are LOW in STANDBY state and will be LOW in INIT state Exception:
• Exception: In case of an over or undervoltage of the internal supply voltages a “hard reset” is always initiated.
Please refer to Chapter 8.3.

Data Sheet 122 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.4.2.4 SLEEP -> INIT state due to detected fault

Description:
Timing Diagram

SLEEP Transition INIT NORMAL

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2
t
< t StG t RD

Figure48 Transition from SLEEP to INIT state

• The device transitions from SLEEP into INIT state issuing a “soft reset” - pin ROT is pulled to LOW for a certain
time tRD and all the outputs are kept enabled. Outputs that where disabled in SLEEP state will get switched
on again, except the LDO_Stby will keep its configuration being ON or OFF.
• This might be issued by an undervoltage of the µC related voltages VQUC, VQST or VVCI as shown in the figure.
The under voltage is shorter than the short to ground detection time tStG. The reset delay time tRD is started as
soon as all µC related voltages VQUC, VQST or VVCI are back in the valid range. The ROT pin is released
accordingly. An under voltage longer than the short to ground detection time tStG would first lead to a transition
from SLEEP to INIT state and then, after the short to ground detection time tStG has expired, to a transition
from INIT to FAILSAFE state
• The “soft reset” can also be initiated by a window watchdog error counter overflow (> Σ WWO), a functional
watchdog error counter overflow (> Σ FWO), an error indication (immediate or recovery delay time mode), if
these monitoring functions are in use. In this case the reset delay time tRD will be started falling edge of the
ROT pin. Please consider the state transition time to INIT state in Table 11-8.
• The safe state signals SS1 and SS2 are LOW in SLEEP state and will be LOW in INIT state Exception:
• Exception: In case of an over or undervoltage of the internal supply voltages a “hard reset” is always initiated.
Please refer to Chapter 8.3.

Data Sheet 123 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.4.2.5 WAKE -> INIT state due to detected fault

Timing Diagram

WAKE Transition INIT NORMAL

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2
t
< t StG t RD

Figure49 Transition from WAKE to INIT state

Description:
• The device transitions from WAKE into INIT state issuing a “soft reset” - pin ROT is pulled to LOW for a certain
time tRD and all the outputs are kept enabled. Outputs that where disabled in WAKE state will get switched on
again, except the LDO_Stby will keep its configuration being ON or OFF.
• This might be issued by an undervoltage of the µC related voltages VQUC, VQST or VVCI as shown in the figure.
The under voltage is shorter than the short to ground detection time tStG. The reset delay time tRD is started as
soon as all µC related voltages VQUC, VQST or VVCI are back in the valid range. The ROT pin is released
accordingly. An under voltage longer than the short to ground detection time tStG would first lead to a transition
from WAKE to INIT state and then, after the short to ground detection time tStG has expired, to a transition
from INIT to FAILSAFE state.
• The “soft reset” can also be initiated by a window watchdog error counter overflow (> Σ WWO), a functional
watchdog error counter overflow (> Σ FWO), an error indication (immediate or recovery delay time mode), if
these monitoring functions are in use. In this case the reset delay time tRD will be started falling edge of the
ROT pin. Please consider the state transition time to INIT state in Table 11-8.
• The safe state signals SS1 and SS2 are LOW in WAKE state and will be LOW in INIT state.
Exception:
• Exception: In case of an over or undervoltage of the internal supply voltages a “hard reset” is always initiated.
Please refer to Chapter 8.3.

Data Sheet 124 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.4.3 Transition into FAILSAFE State

Move to FAILSAFE State

LDO_μC: OV, StG, TSD
CORE_Sup adj.: OV, StG
LDO_Stby: OV, StG
Volt_Ref: OV
PreReg: OV, TSD, StG
Three initialization failures consecutively
BIAS-current Monitor
TSD of Monitoring block
Monitor of fuse selection
Supply voltage (VS) above functional range
(except for STANDBY)

Figure 50 Move to FAILSAFE State

The following failures will bring the device from any state to FAILSAFE-state:
• Detection of over voltage, a short to ground or thermal shutdown at LDO_µC
• Detection of over voltage or a short to ground at Core_Sup adj. or LDO_Stby
• Detection of over voltage at voltage reference
• Detection of over voltage, short to ground1) (only during startup phase in INIT state) or thermal shutdown at
pre regulator
• Three consecutive initialization failures(e.g. configuration in INIT state failed)
• A BIAS current monitor failure
• A over temperature shutdown due to exceeded temperature in the monitoring block.
• A fuse selection monitor failure
• An over voltage at the supply pins (VS) will trigger the overvoltage protection and move the device into
FAILSAFE-state (except for STANDBY state)
11.4.3.1 INIT -> FAILSAFE state due to detected fault

Timing Diagram

1 ) A detected short to GND of the pre regulator after the power sequencing in INIT state (once above the UV threshold) will
not be considered as a Move to FAILSAFE event, but the event will be stored in MONSF0.PREGSG without an interrupt.

Data Sheet 125 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

NORMAL
INIT FAILSAFE

V RT,xxx,low
V PREREG , V QUC , V QST,
V VCI and V QVR

ROT

SS1

SS2
t

Figure 51 Transition from INIT to FAILSAFE state

Description:
• The transition from INIT state into FAILSAFE state will be initiated by any failure (external or internal) case
mentioned in Chapter 11.4.3.
• Pin ROT will be pulled to LOW as soon as one of the MoveToFailsafe failures is detected, if is not already
LOW due to an undervoltage on a µC related regulator.
• All regulators will be switched off, when the device turns from INIT into FAILSAFE state, regardless if they are
in over voltage condition or not.
• The safe state signals SS1 and SS2 are LOW in INIT state and will be LOW in FAILSAFE state.

Data Sheet 126 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

11.4.3.2 XXXX -> INIT -> FAILSAFE state due to detected fault

Timing Diagram

XXXX INIT FAILSAFE

V RT,xxx,low
V QUC , V QST and V VCI

ROT

SS1

SS2
t
t StG

Δt SS2

Figure52 Transition from XXXX to INIT to FAILSAFE state after detection of short to ground

Description:
• The detection of an under voltage of the µC related voltages VQUC, VQST or VVCI as shown in the figure will
initiate the transition into INIT state. (please refer to previous chapter Transition into INIT state)
• Pin ROT will be pulled to LOW as soon as the under voltage is detected (at one or more of the regulators
mentioned above - whichever is the first)
• The safe state signal SS1 will be pulled to LOW together with pin ROT going to low
• If the short to ground maintains for longer than the short to ground detection time tStG a short to ground event
is detected.
• All regulators will be switched off as soon as the short to GND is detected, regardless if they are in under
voltage condition or not.
• The device moves from INIT state to FAILSAFE state
• The safe state signal SS2 will be pulled to LOW together with the transition from INIT to FAILSAFE state, even
if the delay time ΔtSS2 has not expired yet, because LDO_µC is switched off (LDO_µC is switched on in INIT
state, but switched off in FAILSAFE state).
11.4.3.3 NORMAL -> FAILSAFE state due to detected fault

Timing Diagram

Data Sheet 127 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

NORMAL FAILSAFE

V RT,xxx,high
V PREREG , V QUC , V QST,
V VCI and V QVR

ROT

SS1

SS2
t

Figure 53 Transition from NORMAL to FAILSAFE state

Description:
• The detection of an over voltage of the preregulator voltage VPREREG or the µC related voltages VQUC, VQST,
VVCI or VQVR as shown in the figure will initiate the transition from NORMAL state to FAILSAFE state.
• Pin ROT will be pulled to LOW as soon as the over voltage event is detected (at one or more of the regulators
mentioned above - whichever is the first).
• All regulators will be switched off, when the device turns from NORMAL into FAILSAFE state, regardless if
they are in over voltage condition or not.
• The safe state signals will be pulled to LOW immediately with pin ROT going to low, because the LDO_µC is
switched off.
• The transition from NORMAL state into FAILSAFE state will be initiated by any failure (external or internal)
case mentioned in Chapter 11.4.3.
• The detection of a short to ground of the µC related voltages VQUC, VQST or VVCI as shown in the Figure 52
will first be detected as an under voltage event and move the device from NORMAL state to INIT state. After
the short to ground detection time tStG the device will then move from INIT state to FAILSAFE state (please
refer to transition from INIT state to FAILSAFE state).
11.4.3.4 STANDBY -> FAILSAFE state due to detected fault

Timing Diagram

Data Sheet 128 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

STANDBY
NORMAL FAILSAFE

V RT,xxx,high
V QST

ROT

SS1

SS2
t

Figure 54 Transition from STANDBY to FAILSAFE state

Description:
• The detection of an over voltage of the µC related voltage VQST as shown in the figure will initiate the transition
from STANDBY state to FAILSAFE state.
• Pin ROT is LOW in STANDBY state and will stay LOW in FAILSAFE state.
• The safe state signals SS1 and SS2 are LOW in STANDBY state and will be LOW in FAILSAFE state.
• Beside the example above the transition from STANDBY state into FAILSAFE is initiated by an internal BIAS
current monitor failure.
• The detection of a short to ground of the µC related voltages VQUC, VQST or VVCI as shown in the Figure 52
will first be detected as an under voltage event and move the device from STANDBY state to INIT state. After
the short to ground detection time tStG the device will then move from INIT state to FAILSAFE state (please
refer to transition from INIT state to FAILSAFE state).
11.4.3.5 SLEEP -> FAILSAFE state due to Fault

Timing Diagram

NORMAL
SLEEP FAILSAFE

V RT,xxx,high
V PREREG , V QUC , V QST,
V VCI and V QVR

ROT

SS1

SS2
t

Figure 55 Transition from SLEEP to FAILSAFE state

Data Sheet 129 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Description:
• The detection of an over voltage of the preregulator voltage VPREREG or the µC related voltages VQUC, VQST,
VVCI or VQVR as shown in the figure will initiate the transition from SLEEP state to FAILSAFE state.
• Pin ROT will be pulled to LOW as soon as the over voltage event is detected (at one or more of the regulators
mentioned above - whichever is the first).
• All regulators will be switched off, when the device turns from SLEEP into FAILSAFE state., regardless if they
are in over voltage condition or not.
• The safe state signals will stay at LOW as in the SLEEP state.
• The transition from SLEEP state into FAILSAFE state will be initiated by any failure (external or internal) case
mentioned in Chapter 11.4.3.
• The detection of a short to ground of the µC related voltages VQUC, VQST or VVCI as shown in the Figure 52
will first be detected as an under voltage event and move the device from SLEEP state to INIT state. After the
short to ground detection time tStG the device will then move from INIT state to FAILSAFE state (please refer
to transition from INIT state to FAILSAFE state).
11.4.3.6 WAKE -> FAILSAFE state due to detected fault

Timing Diagram

NORMAL
WAKE FAILSAFE

V RT,xxx,high
V PREREG , V QUC , V QST,
V VCI and V QVR

ROT

SS1

SS2
t

Figure 56 Transition from WAKE to FAILSAFE state

Description:
• The detection of an over voltage of the preregulator voltage VPREREG or the µC related voltages VQUC, VQST,
VVCI or VQVR as shown in the figure will initiate the transition from WAKE state to FAILSAFE state.
• Pin ROT will be pulled to LOW as soon as the over voltage event is detected (at one or more of the regulators
mentioned above - whichever is the first).
• All regulators will be switched off, when the device turns from WAKE into FAILSAFE state., regardless if they
are in over voltage condition or not.
• The safe state signals will stay at LOW as in the WAKE state.
• The transition from WAKE state into FAILSAFE state will be initiated by any failure (external or internal) case
mentioned in Chapter 11.4.3.

Data Sheet 130 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• The detection of a short to ground of the µC related voltages VQUC, VQST or VVCI as shown in the Figure 52
will first be detected as an under voltage event and move the device from WAKE state to INIT state. After the
short to ground detection time tStG the device will then move from INIT state to FAILSAFE state (please refer
to transition from INIT state to FAILSAFE state).
11.4.3.7 Transition into FAILSAFE state due to thermal shutdown

Timing Diagram

NORMAL
XXXX FAILSAFE

V RT,xxx,low
V PREREG , V QUC , V QST,
V VCI and V QVR

ROT

SS1

SS2
t

Figure 57 Transition into to FAILSAFE state due to thermal shutdown

Description:
• The transition from any state into FAILSAFE state will be initiated by a thermal shutdown (TSD).
• Pin ROT will be pulled to LOW as soon as the thermal shutdown will be detected.
• All regulators will be switched off, when the device turns from xxx into FAILSAFE state. regardless if they are
in over temperature condition or not
• Out of NORMAL state the safe state signals SS1 and SS2 will be pulled to LOW immediately with pin ROT
going to low, because the LDO_µC is switched off. Out of any other state the safe state signals SS1 and SS2
are LOW and will stay low.
• The device will stay in FAILSAFE state after a thermal shutdown (TSD) at least for 1 s.
11.4.4 Transition into POWERDOWN-state

Move to POWERDOWN
Internal Supplies UV, OV
Supply VS UV

Figure 58 Move to POWERDOWN-state

The following failures/event will bring the device always with highest priority to POWERDOWN-state:
• VVS below VPD,lo,min when decreasing

Data Sheet 131 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• Detection of over- or under voltage on internal supplies

11.5 Electrical Characteristics

Table 11-8 Electrical characteristics: State machine

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
INIT timer / Initialization tINIT 550 600 650 ms – P_11.5.1
time-out
FAILSAFE time 18 20 22 ms – P_11.5.2
tFAILSAFE,
min

FAILSAFE time TSD 0.9 1 1.1 s for thermal P_11.5.3

tFAILSAFE, shutdown TSD
min

Transition delay timer ttr,del -20 – +20 % 1) P_11.5.4

accuracy
Configurable value
DEVCFG0.TRDEL
LDO_µC current monitoring ILDO_µC, -30 – +30 % Configurable value P_11.5.5
for low power states att DEVCFG2.CTHR ;
VPREREG > VQUC +
Vdr,QUC
State transition time ttr – – 100 µs except transitions P_11.5.6
to SLEEP, to
STANDBY2) or
from STANDBY

State transition time to INIT ttr,INIT – – 150 µs valid for “Move to P_11.5.7
INIT” events
excluding
transitions from
STANDBY,
FAILSAFE and
POWERDOWN

Data Sheet 132 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

State transition time to INIT ttr,INIT – – 250 µs valid for transitions P_11.5.8
from STANDBY,
FAILSAFE and
interrupted
transition to
STANDBY
Internal start-up time from ttr,pwrd – 0.4 2 ms from first VS P_11.5.9
POWERDOWN connection to INIT/
power sequence

PowerDown threshold high VPD,hi – – 6 V VVS increasing P_11.5.10

(Power-On-Reset POR)
PowerDown threshold low VPD,lo 2 – 3.5 V VVS decreasing P_11.5.11
(Power-On-Reset POR)
1) Due to internal delays the transition delay time can be enlarged by max 30 µs.
2) For transition times into SLEEP or STANDBY please refer to the transition delay timer configurable by register
DEVCFG0.TRDEL and its accuracy specified in Table 11-8.

11.6 Built In Self Test (BIST) Features

TLF35584 provides the option to test certain observation functions with the assistance of the external µC via built
in self-test features. These features are described in the following chapters.

11.6.1 Analog Built In Self Test (ABIST)

TLF35584 provides the option to test the comparator and evaluation logic related to the monitoring functions
contributing to the activation of the secondary safety shutdown path and the generation of an interrupt. Further on
additional comparators and evaluation logic related to the safe state control itself can be tested (SSC overvoltage
watchdog and toggling monitor). This is accomplished via an internal ABIST controller which performs tests on
each comparator generating artificial undervoltage and overvoltage (or current) conditions, is checking the result

Data Sheet 133 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

and generates the information which needs to be evaluated by the µC to judge, if the ABIST operation has been
performed successfully or not.
The following status information on ABIST operation is generated by the system:
• In case an ABIST operation has been requested by the µC, a status is provided after the ABIST has been
performed (ABIST_CTRL0.STATUS). This status needs to be evaluated by the µC. The provided status is
just a GO-NOGO information, which means information about a particularly tested path is provided. The basic
comparator function is tested, but not the respective threshold values.
The test of the monitoring and safety relevant output functions is run on three different areas in the system:
• The functionality of a comparator and its corresponding deglitching logic can be tested by a “comparator only”
test. This test is performed by generating the failure condition for a time shorter than the deglitching time,
accordingly the secondary safety shutdown path nor the interrupt is triggered due to the detected failure.
During this test only the selected comparator(s) are tested. In case more than one comparator is selected, the
test is performed with a fixed sequence of comparators to be tested. The completion of the test is indicated by
an interrupt.
• The functionality of a comparator including its corresponding deglitching logic and the contribution to the
respective safety measure can be tested. The safety measure is either the activation of the secondary safety
shutdown path or the generation of an interrupt. This test is performed in a time longer than the deglitching
time.
• While the device provides information about the status for the first and the second ABIST, further
microcontroller cooperation is required for the third area. The µC is responsible to check if the secondary
safety shutdown path has been activated successfully (SS1/SS2 are set low) or an interrupt event has been
detected by the µC.
11.6.1.1 How to run the ABIST
During ABIST, servicing of the watchdog(s) and error monitoring is required to be performed according to the
configuration by the microcontroller. Error in not doing so will lead to failure events in these functions and will lead
to the assertion of interrupt, reset or safe state output events accordingly, which is disturbing the proper analysis
of the ABIST results. Optionally watchdog functionality and/or error monitoring can be disabled during ABIST
operation via a protected register access. In this case, no servicing is required.
During a performed ABIST including the deglitching logic the FLAG registers (SYSFAIL, INITERR, IF) as well as
the status information (MONSF1, MONSF2, MONSF3) are triggered and updated by out of range conditions
caused by the ABIST functionality, which has to be considered beside the results provided in the ABIST related
registers (ABIST_CTRL0 to ABIST_SELECT2).
During the time, when the ABIST is performed by internal hardware, the assertion of ROT due to the occurrence
of any event which is supposed to trigger the respective action and is part of the logic which is affected by the
ABIST control is blocked. In addition, the state machine will not change its state according to the reaction on
detected faults described in Chapter 11.4. In case an ABIST contributing to the secondary safety shutdown path
is started and the device is in NORMAL state, the state machine will move from NORMAL to WAKE state.
Furthermore, all voltages will be kept enabled regardless of any out of range detection caused by ABIST itself.

The test of a single functionality is basically always performed in the same way:
• All comparators are assumed to be enabled in case they are selected to be tested, while this is true for any
µC related voltage it might not be the case for non µC related voltages. Accordingly, configurable LDO’s have
to be enabled before they can be tested. On the other hand the ABIST test on a comparator which is not used
by the system is not required to be performed.
• The comparators to be tested shall be selected by setting the individual bit(s) in the respective register(s)
(ABIST_SELECT0, ABIST_SELECT1 and ABIST_SELECT2). For this selection it is necessary to

Data Sheet 134 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

differentiate by the contribution to the different safety measure. The differentiation can be derived from Table
11-9.
• The microcontroller shall configure the register ABIST_CTRL0 according to the functionality to be tested. The
configuration consist of the tested safety measure (ABIST_CTRL0.INT), the tested area/coverage by the
ABIST (ABIST_CTRL0.PATH) and the configuration whether a sequence or a single comparator shall be
tested (ABIST_CTRL0.SINGLE).
• The microcontroller shall set the global ABIST start bit (ABIST_CTRL0.START) to start the ABIST.
• The global ABIST start bit shall be read by the µC. If this bit is still set, ongoing ABIST functionality is
performed. Upon completion of the selected ABIST operation(s) the start bit is cleared and an interrupt event
is generated.
• Each bit which has been set to select the test of a dedicated comparator (ABIST_SELECT0,
ABIST_SELECT1 and ABIST_SELECT2) is cleared once a successful ABIST operation has been performed
on the particular comparator. Each bit which has been set to select the test of a dedicated comparator is kept
unchanged if the ABIST operation on this particular comparator has not been performed successfully.
In this way the µC can determine which comparator failed in case the ABIST status information shows a failing
ABIST operation.

Table 11-9 Contribution of comparators to safety measures

Comparator Secondary Safety Interrupt ABIST_Select register bit
Shutdown Path

LDO_µC Overvoltage X ABIST_SELECT0.UCOV

Core_Sup Overvoltage X ABIST_SELECT0.VCOREOV

LDO_Stby Overvoltage X ABIST_SELECT0.STBYOV

Table 11-9 Contribution of comparators to safety measures (cont’d)

Comparator Secondary Safety Interrupt ABIST_Select register bit
Shutdown Path
Volt_Ref Overvoltage X ABIST_SELECT0.VREFUV

PreReg Overvoltage X ABIST_SELECT0.PREGOV

LDO_µC Undervoltage X ABIST_SELECT1.UCUV

Core_Sup Undervoltage X ABIST_SELECT1.VCOREUV

LDO_Stby Undervoltage X ABIST_SELECT1.STBYUV

BIAS current low X ABIST_SELECT2.BIASLOW

BIAS current high X ABIST_SELECT2.BIASHI

Supply VS Overvoltage X ABIST_SELECT2.VBATOV

Internal Supply Overvoltage X 1) ABIST_SELECT2.INTOV

Tracker 1 Overvoltage X ABIST_SELECT0.TRK1OV

Tracker 2 Overvoltage X ABIST_SELECT0.TRK2OV

LDO_Com Overvoltage X ABIST_SELECT0.COMOV

Data Sheet 135 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Volt_Ref Undervoltage X ABIST_SELECT1.VREFUV

Tracker 1 Undervoltage X ABIST_SELECT1.TRK1UV

Tracker 2 Undervoltage X ABIST_SELECT1.TRK2UV

LDO_Com Undervoltage X ABIST_SELECT1.COMUV

Pre_Reg Undervoltage X ABIST_SELECT1.PREGUV

VBG1 - 4% ≤ VBG2 X ABIST_SELECT2.BG12UV

VBG1 + 4% ≥ VBG2 X ABIST_SELECT2.BG12OV

1) This comparator must be tested only by “comparator only” test
11.6.1.2 Testing the comparator logic only
During the ABIST operation the comparators are triggered by the ABIST controller for a time shorter than the
internal deglitching time trr (reset reaction time). A properly working comparator signals an out of range condition
to its output for the time the failure condition is applied.
The provided information of each comparator is checked against the expected value. If the comparator output
value matches the expected value this is considered as a passing test by the ABIST controller. If any of the
provided output values do not match the expected value, this is considered as a failing test. The general result of
the ABIST is provided by the STATUS in the register ABIST_CTRL0. The detailed result for each selected
comparator can be checked by the registers ABIST_SELECT0, ABIST_SELECT1 and ABIST_SELECT2. In case
the previously selected bits are reset after the test is finished, it can be considered as pass. A bit which is still set,
would indicated the failing comparator(s), that makes the overall STATUS to be failed.
Accordingly the maximum selection1) (including possible ones) for the comparator test would be the following:
Secondary safety shutdown path (SS1/2) related:
• ABIST_SELECT0 : 00101111B (2FH)
• ABIST_SELECT1 : 00001110B (0EH)
• ABIST_SELECT2 : 11001001B (C9H)
• Start of the test by ABIST_CTRL0 : 00000001B (01H) Interrupt (INT) related:
• ABIST_SELECT0 : 11010000B (D0H)
• ABIST_SELECT1 : 11110001B (F1H)

• ABIST_SELECT2 : 00110000B (30H)

• Start of the test by ABIST_CTRL0 : 00001001B (09H)
This type of ABIST can be performed in the following states of the State Machine: INIT, NORMAL, WAKE. In
case of an successful ABIST there shall be no reaction of secondary safety shutdown path SS1/2 and only an
interrupt generated due to the finished ABIST (IF.ABIST set and IF.MON not set, considering cleared interrupt
flags prior to the ABIST and no real failure events during the ABIST).
11.6.1.3 Testing the comparator logic and the corresponding deglitching logic
During the ABIST operation the comparators are triggered by the the ABIST controller for a time longer than the
internal deglitching time trr (reset reaction time). A properly working comparator signals an out of range condition
to its output for the time the failure condition is applied. The deglitching logic will forward the failure trigger after trr
and makes the device react on the recognized failure event. This reaction consists the storage of the respective
monitoring failure flags and as well the triggering of the respective output function, which is either the interrupt INT

1
) Please mind that for a test of a comparators the corresponding output has to be enabled.

Data Sheet 136 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

or the secondary safety shutdown path SS1/2. The reaction of the safe state outputs SS1/2 can only be observed
in case the test is started in NORMAL state.
Furthermore the provided information of each deglitching logic output is checked against the expected value. If
the deglitching logic output value matches the expected value this is considered as a passing test by the ABIST
controller. If any of the provided output values do not match the expected value, this is considered as a failing
test. The general result of the ABIST is provided by the STATUS in the register ABIST_CTRL0. The detailed
result for each selected comparator can be checked by the registers ABIST_SELECT0, ABIST_SELECT1 and
ABIST_SELECT2. In case the previously selected bits are reset after the test is finished, it can be considered as
pass recognized by the ABIST controller. A bit which is still set, would indicated the failing comparator(s), that
makes the overall STATUS to be failed.
Beside the results read from the ABIST controller related registers, the result provided in the failure/interrupt flags
(SYSFAIL, INITERR and IF) and monitoring status flags (MONSF1, MONSF2 or MONSF3) have to be read and
checked by the microcontroller against the expected result considering the configuration set before the start of
the ABIST.
INTOV located in register ABIST_SELECT2 cannot be tested in this way, testing of the comparator logic only is
required according to Chapter 11.6.1.2.

The maximum selection1) for the comparator and deglitching logic test would be the following:
Secondary safety shutdown path (SS1/2) related:
• ABIST_SELECT0 : 00101111B (2FH)
• ABIST_SELECT1 : 00001110B (0EH)
• ABIST_SELECT2 : 11000001B (C1H)
• Start of the test by ABIST_CTRL0 : 00000011B (03H) Interrupt (INT) related:
• ABIST_SELECT0 : 11010000B (D0H)
• ABIST_SELECT1 : 11110001B (F1H)
• ABIST_SELECT2 : 00110000B (30H)
• Start of the test by ABIST_CTRL0 : 00001011B (0BH)
The analysis based on the maximum possible selection would consist the following:
Secondary safety shutdown path (SS1/2) related:
• IF : 01000000B (40H)
• INITERR : 00000100B (04H)
• SYSFAIL : 00000100B (04H)
• MONSF1 : 00101111B (2FH)
• MONSF2 : 00001110B (0EH)
• MONSF3 : 11000001B (C1H)
• Start of the test by ABIST_CTRL0 : 00000011B (03H) Interrupt (INT) related:
• IF : 01001000B (48H)
• INITERR : 00000000B (00H)

1
) Please mind that for a test of a comparators the corresponding output has to be enabled.

Data Sheet 137 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• SYSFAIL : 00000000B (00H)

• MONSF1 : 11010000B (D0H)
• MONSF2 : 11110001B (F1H)
• MONSF3 : 00110000B (30H)
• Start of the test by ABIST_CTRL0 : 00001011B (0BH)

This type of ABIST can be performed in the following states of the State Machine: INIT, WAKE, NORMAL. If
this test is run in NORMAL state on comparators contributing to the secondary safety shutdown path the device
will switch low the safe state outputs SS1/2 and the State Machine will move to WAKE state, without triggering
a reset ROT.
It has to be considered that testing the complete monitoring chain till the respective output (SS1/2 or INT) in this
way will cover only the first comparator in the sequence, as this one will trigger the output reaction. For further
details, please refer to Chapter 11.6.1.4.
If this test is run in INIT or WAKE state, contribution to activation of the secondary safety shutdown path cannot
be tested. The system is in a safe state already and the secondary safety shutdown path is already activated. In
any way the proper behavior of the secondary shutdown p3ath as well as the interrupt signal needs to be checked
by the microcontroller.
11.6.1.4 Testing the complete monitoring chain (comparators, deglitching and output)
The testing of the complete monitoring chain from the comparator till the respective output function has to be
divided into the two functions available in TLF35584. First the secondary safety shutdown path called SS1/2 for
severe microcontroller related failure events and secondly the interrupt function INT for peripheral related failure
events in terms of voltage and current monitoring.

11.6.1.4.1 Testing the activation of the secondary safety shutdown path

To test the activation of the secondary safety shutdown path, the device has to be brought into NORMAL state.
The µC shall check if the secondary safety shutdown path has been de-activated successfully (SS1/2 high).
Once in NORMAL state a single comparator contributing to the secondary safety shutdown path shall be selected.
A single bit (‘x’) has to be set for a corresponding comparator in registers ABIST_SELECT0 (00x0xxxxB),
ABIST_SELECT1 (0000xxx0B) or ABIST_SELECT2 (xx00000xB). A randomized selection by the microcontroller
ensures maximum coverage of the contributions to the secondary safety shutdown path. Then a single comparator
ABIST operation on the full path of the secondary safety shutdown path needs to be started (register
ABIST_CTRL0: 00000111B (07H) ). Upon completion of the requested ABIST operation the device will
autonomously move into WAKE state and an interrupt event is generated. The interrupt event will indicate the
completion of the ABIST (IF.ABIST). Furthermore the respective monitoring failure flag for the selected
comparator will be set (either INITERR.VMONF for “Move to INIT State” failures or SYSFAIL.VMONF for “Move
to FAILSAFE State” failures) which has to be checked and cleared by the microcontroller.
The secondary safety shutdown path shall be activated (SS1/2 low), it is the responsibility of the µC to check the
activation of the secondary safety shutdown path. If SS2 delay is enabled, this delay will be applied when the
ABIST operation is performed, i.e. the activation of the shutdown path connected to SS2 will be delayed according
to the programmed value for failure cases not leading to FAILSAFE.
The µC needs to read and check the status of the requested ABIST operation (ABIST_CTRL0.STATUS), the
respective monitoring status flag (MONSF1, MONSF2 or MONSF3) to be set according to the previous selection
and ABIST_SELECT0, ABIST_SELECT1 and ABIST_SELECT2 bits to be cleared.
Furthermore, the microcontroller has to proceed with the following steps to check the safe state control and the
safe state outputs:
• Check that the secondary safety shutdown path has been activated successfully (SS1/2 low)

Data Sheet 138 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

• Enable overvoltage trigger of the safe state control (set ABIST_CTRL1.OV_TRIG)

• Wait for 50µs and check that the secondary safety shutdown path is still activated successfully (SS1/2 low)
• Select generation of valid toggling signal for the safe state control (set ABIST_CTRL1.ABIST_CLK_EN)
• Wait for 50µs and check that the secondary safety shutdown path is still activated successfully (SS1/2 low)
• De-select generation of toggling signal for the safe state control (reset ABIST_CTRL1.ABIST_CLK_EN)
• Wait for 50µs and check that the secondary safety shutdown path is still activated successfully (SS1/2 low)
• Disable overvoltage trigger of the safe state control (set ABIST_CTRL1.OV_TRIG)
• Wait for 50µs and check that the secondary safety shutdown path is still activated successfully (SS1/2 low)
Afterwards a test of all comparators which contribute to the activation of the secondary safety shutdown path shall
be configured and started according to Chapter 11.6.1.3.
11.6.1.4.2 Testing the generation of an interrupt event
The test of the generation of an interrupt event can be done in the states INIT, NORMAL and WAKE state. Even
though it is recommended to have the application in safe state (INIT or WAKE state).
For this test first a single comparator contributing to the interrupt function shall be selected. A single bit (‘x’) has
to be set for a corresponding comparator in registers ABIST_SELECT0 (xx0x0000B), ABIST_SELECT1
(xxxx000xB) or ABIST_SELECT2 (00xx0000B). A randomized selection by the microcontroller ensures maximum
coverage of the contributions to the interrupt function. Then a single comparator ABIST operation on the full path
of the interrupt needs to be started (register ABIST_CTRL0: 00001111B (0FH) ). The artificial failure, triggered by
the ABIST controller, on the selected comparator will generate an interrupt (INT) event. It is the responsibility of
the µC to check the generation of this interrupt event on the triggered failure. As this is a test of the generation of
an interrupt based on a failure event, there is no dedicated ABIST completion event, nor the ABIST bit in the
interrupt flags will be set. Accordingly it is recommended to store the information about the started ABIST in the
firmware. After the interrupt has been generated the interrupt flag register shall be checked for the monitoring bit
(IF.MON) set and the ABIST completion bit (IF.ABIST) not set.
The µC needs to read and check the status of the requested ABIST operation (ABIST_CTRL0.STATUS), the
respective monitoring status flag (MONSF1, MONSF2 or MONSF3) to be set according to the previous selection
and ABIST_SELECT0, ABIST_SELECT1 and ABIST_SELECT2 bits to be cleared.
Afterwards a test of all comparators which contribute to the interrupt generation shall be configured and started
according to Chapter 11.6.1.3.

11.6.1.5 Abort conditions for ABIST operation

In case of an severe monitoring failure event (contribution to the secondary safety shutdown path) detected on a
not selected comparator1) or a severe failure event not related to the voltage or bias current monitoring function
during the proceeding of an ABIST operation on the comparators only (ABIST_CTRL0.PATH not set), the
device will react as it is supposed to do in normal operation. Accordingly the monitoring, reset and safe state
control are reacting. Bringing the device into safe state and trigger the State Machine to move into FAILSAFE
or INIT state. The ABIST is aborted in this case.
In case of an ABIST operation on the full path (ABIST_CTRL0.PATH set) the comparators for voltage and bias
current monitoring are blind for the time of the ABIST operation. Therefore it is recommended to do the test in
safe state unless it is needed to start the test in NORMAL state (e.g. test of activation of secondary safety
shutdown path described in Chapter 11.6.1.4.1). Severe failure events not related to the voltage and bias current

1 ) Please mind that selected comparators might be blind for the time of the ABIST operation. Therefore it is recommended to
do the test in safe state unless it is needed to start the test in NORMAL state (e.g. test of activation of secondary safety
shutdown path described in Chapter 11.6.1.4.1).

Data Sheet 139 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

monitoring will trigger the same device reaction as in usual condtion. Bringing the device into safe state and trigger
the State Machine to move into FAILSAFE or INIT state. The ABIST is aborted in this case.
This ABIST abort will be shown by the TLF35584 in the register SYSFAIL.ABISTERR. The artificial failure events,
that have been generated until the abort of the ABIST due to the detected real failure, will be stored as well in the
monitoring registers.
11.6.2 Logic Built In Self Test
No dedicated Built In Self Test for the digital logic exists in the device. It is therefore assumed that any test which
is related to the digital logic is performed by the µC.
The following blocks inside the digital logic can be tested by the µC:
• FWD/WWD
• Error monitoring
In order to verify correct functionality of these blocks and to check their contribution to ROT/INT and finally SS1/2
the µC shall generate an error condition on the particular block and check for the occurrence of the expected
system behavior.
• For the watchdog functionality this basically means either stop triggering the WD(s) and/or generate false
trigger events. This will either generate and interrupt or even assert the reset. Finally the secondary safety
shutdown path will be activated, the µC will be reset and the device will move into INIT state. In order to verify
the activation of the secondary shutdown path, this kind of test shall only be executed after the device has
been moved into NORMAL state.
• For the error monitoring block, this means that the toggling at the ERR pin needs to be stopped in order to
observe the required system behavior. It is up to the µC to make use of the error recovery mechanism or not.

11.7 Microcontroller Programming Support

The TLF35584 offers a microcontroller programming support feature, that can be used to avoid periodic reset
triggering due to missing triggering of the window watchdog and error monitoring within the INIT timer. The
activation of the microcontroller programming support feature shall be done by pulling the MPS pin to 5 V. The
voltage shall be provided earliest with the enabling of the voltage reference. Therefore it would be one option to
connect the MPS pin to the output QVR during microcontroller programming.
The active microcontroller programming support feature includes the following changes to the normal operation
of the device:
• The INIT timer will be stopped.
• The contribution of the window watchdog failure counter overflow to the reset ROT will be blocked.
• The contribution of the functional watchdog failure counter overflow to the reset ROT will be blocked.
• The contribution of the error monitoring to the reset ROT will be blocked.
As only the contribution of the watchdogs and the error monitoring to the reset function is blocked/disconnected,
the state machine and safe state control function are not affected. Accordingly an overflow of the window or
functional watchdog failure counter will trigger a “Move to INIT” event, but without issuing a reset of the
microcontroller.
The microcontroller programming support feature offers as well the possibility to move the TLF35584 to any other
state according to the state machine. E.g. in case MPS pin is high in NORMAL and there is a watchdog error
counter overflow the device would move into INIT without issuing a reset.

Data Sheet 140 Rev. 2.0, 2017-03-16

 TLF35584

State Machine

Data Sheet 141 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

12 Safe State Control Function

12.1 Introduction
The safe state control monitors safety related signals and controls the safe state signals SS1 and SS2.
The following description summarizes the contributors to the safe state control function and the possibilities to
adjust them.

Principle of operation:
The safe state control function monitors the following inputs:
• Result of the Error Monitoring. “Error”-signal at pin ERR is expected to be a toggling signal. A permanent low
or high signal will be detected as an error.
• Over and under voltage of the micro processor related regulators (for details please refer to chapter
Monitoring Function)
• Result of Window Watchdog Failure Counter Threshold Comparator. Whether threshold Σ WWO for “Invalid
window watchdog triggering” has been exceeded.
• Result of Functional Watchdog Failure Counter Threshold Comparator: Whether threshold Σ FWO for “Invalid
functional watchdog triggering” has been exceeded.
• Thermal shutdown signal (TSD) for relevant events moving the device into FAILSAFE state.
• Internal clock
• SPI state transition request. A valid GoToNORMAL command triggers the signals SS1/2 to switch high in case
the other boundary conditions are fulfilled. Moving the device out of NORMAL state by SPI command will
switch the signals SS1 and 2 (optionally delayed by tSS2) to low.

The following parameters of the safe state control function are programmable via SPI, this settings can be done
during INIT, NORMAL, SLEEP and WAKE state, WWD and FWD configuration and error pin configuration
including disabling of individual functionality via protected register (for description of states please refer to chapter
State Machine):
• Number of invalid watchdog triggers, that lead to activating SS1 and SS2: There are two watchdog trigger
failure counters implemented, one for the window watchdog the other for the functional watchdog. Every
counter increments by two at every invalid watchdog triggering and decrements by one at every valid watchdog
triggering. (valid and invalid triggering is described in chapter functional and window watchdog). An
incrementing change is indicated by an interrupt. A decrementing change is not indicated by an interrupt. The
thresholds can be programmed by SPI command for each counter individually. This function might be used to
test the watchdog function.
• Immediate reaction or recovery delay reaction, only related to input signal ERR: This parameter determines
whether the safe state control will immediately react to an error indicated by SMU or react after a certain delay,
if the error indication is still present. In recovery delay reaction the safe state control will generate an interrupt
and start the programmed recovery delay time. If within this time the error should disappear (means the error
signal should toggle again, before the recovery delay time has ended), the safe state control will keep the safe
state output SS1/2 high. If within this time the error signal should not disappear and maintain the error
indication (means the error signal should not toggle again, before the recovery delay time has ended), the safe
state control will activate the safe state signals SS1 and SS2 after the recovery delay time has ended.
Immediate reaction means reaction after signal detection delay time.

Data Sheet 142 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

• Recovery delay time ΔtREC, only related to input signal ERR: An error (violation of valid ERR signal) has to be
longer than this delay time to lead to activating the safe state signals SS1 and SS2. This delay time is only
active if recovery delay time mode was selected.
• Delay time ΔtSS2 between safe state signal 1 and safe state signal 2
The safe state function offers two output signals, both of them as output stages to drive external switches
(additional driver stage is necessary):
• Safe state signal 1 (present at pin SS1)
• Safe state signal 2 (present at pin SS2), it may be delayed to safe state signal 1 by an adjustable delay time
ΔtSS2 (via SPI)

Error signal from microcontroller safety management unit (SMU) at pin ERR:
The error monitoring function requires a toggling signal at pin ERR with a determined timing in case of fault-free
operation of the microcontroller by its SMU. This toggling signal is considered as a “being alive” indication. An
error should be indicated by a constant low signal. A constant high signal will also be regarded as a failure
indication, probably caused by a short circuit. The result is given to the safe state control.

Figure 59 Principle safe state control function

Description:
• State Transition Request= Micro processor can request a de-activation of the Secondary Safety Shutdown
path (SS1/2 high) via SPI. Being in NORMAL state the micro processor can activate the Secondary Safety
Shutdown path (SS1/2 low) by moving the device out of NORMAL state by SPI.
• ERR = Error pin connected to safety management unit (SMU) of micro processor
• TSD = Thermal shutdown
• ROT = Reset output

Data Sheet 143 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

• Σ WWO = Number of “Invalid WWD triggering”, after safe state control shall activate the safe state signal SS1
and SS2, located in window watchdog block
• Σ FWO = Number of “Invalid FWD triggering”, after safe state control shall activate the safe state signal SS1
and SS2, locked in functional watchdog block
• IMMEDIATE/RECOVERY = Distinguish between immediate reaction to SMU signal or recovery delay time,
located in error monitoring block
• ΔtREC = Recovery delay time for SMU signal at pin ERR, located in error monitoring block
• ΔtSS2 = Delay time between safe state signal 1 and safe state signal 2
• SS1 = Safe state signal 1
• SS2 = Safe state signal 2

12.2 Electrical Characteristics

Table 18 Electrical Characteristics: Safe State Control

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
ERR pin
ERR valid high level VERR,hi 3.6 – – V VERR increasing, P_12.2.1
VQUC = 5.0 V
ERR valid low level VERR,lo – – 0.8 V VERR decreasing, P_12.2.2
VQUC = 5.0 V
ERR hysteresis VERR,hyst – 350 – mV VQUC = 5.0 V P_12.2.3
ERR valid high level VERR,hi 2.0 – – V VERR increasing, P_12.2.4
VQUC = 3.3 V
ERR valid low level VERR,lo – – 0.8 V VERR decreasing, P_12.2.5
VQUC = 3.3 V
ERR hysteresis VERR,hyst – 160 – mV VQUC = 3.3 V P_12.2.6

Data Sheet 144 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

ERR pull-down current IERR – 150 330 µA VERR = VQUC P_12.2.7

ERR input capacitance – 15 pF 1) P_12.2.8
CERR 4
Valid ERR input signal fERR,valid 10 – 45 kHz considering a duty P_12.2.9
frequency cycle of 50%
Invalid ERR input signal fERR,invalid,LF 0 – 5 kHz considering a duty P_12.2.10
frequency (low frequency) cycle of 50%
Invalid ERR input signal fERR,invalid,HF 96.2 – 500 kHz considering a duty P_12.2.11
frequency (high frequency) cycle of 50%
Invalid ERR input signal ΔtDET,LF 50.1 – 99.9 µs derived from fERR,valid P_12.2.12
detection time (low and fERR,invalid,LF
frequency)
Invalid ERR input signal ΔtDET,HF 5.2 – 11.1 µs derived from fERR,valid P_12.2.13
detection time (high and fERR,invalid,HF
frequency)
ERR reactivation time-out tERR,TO 9 10 11 ms after SLEEP P_12.2.14
ERR reactivation time-out tERR,ren 50.1 – 110 µs after reenabling via P_12.2.15
(first edge expected) SPI 2)
Safe state signal 1 pin SS1
SS1 output, high level VSS1,hi 3.6 4.8 VQUC V ISS1 ≥ -1 mA; P_12.2.16
TLF35584xxVS1 VQUC = 5.0 V
SS1 output, high level VSS1,hi 3.0 4.3 VQUC V ISS1 ≥ -5 mA; P_12.2.17
TLF35584xxVS1 VQUC = 5.0 V
SS1 output, high level VSS1,hi 2.9 3.2 VQUC V ISS1 ≥ -1 mA; P_12.2.18
TLF35584xxVS2 VQUC = 3.3 V
Table 18 Electrical Characteristics: Safe State Control (cont’d)
VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

SS1 output, high level VSS1,hi 2.0 2.8 VQUC V ISS1 ≥ -5 mA; P_12.2.19
TLF35584xxVS2 VQUC = 3.3 V
SS1 pull-down resistor 70 100 130 kΩ P_12.2.20
RSS1,pd
SS1 output, low level VSS1,lo – 0 0.8 V 3) 4) P_12.2.21

RSS1,pd ≤ 100 kΩ ;
CSS1 ≥ 50 pF ;
LDO_µC active ;
VQUC ≥ 2 V
SS1 internal reaction time – 12 30 µs P_12.2.22
tSS1,act
Safe state signal 2 pin SS2

Data Sheet 145 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

SS2 output, high level VSS2,hi 3.6 4.8 VQUC V ISS2 ≥ -1 mA; P_12.2.23
TLF35584xxVS1 VQUC = 5.0 V
SS2 output, high level VSS2,hi 3.0 4.3 VQUC V ISS2 ≥ -5 mA; P_12.2.24
TLF35584xxVS1 VQUC = 5.0 V
SS2 output, high level VSS2,hi 2.9 3.2 VQUC V ISS2 ≥ -1 mA; P_12.2.25
TLF35584xxVS2 VQUC = 3.3 V
SS2 output, high level VSS2,hi 2.0 2.8 VQUC V ISS2 ≥ -5 mA; P_12.2.26
TLF35584xxVS2 VQUC = 3.3 V
SS2 pull-down resistor 70 100 130 kΩ P_12.2.27
RSS2,pd
SS2 output, low level VSS2,lo – 0 0.8 V 3) 4) P_12.2.28

RSS2,pd ≤ 100 kΩ ;
CSS2 ≥ 50 pF ;
LDO_µC active ;
VQUC ≥ 2 V
SS2 internal reaction time – 12 30 µs P_12.2.29
tSS2,act
Adjustable parameters
SSC time base accuracy tSSC -10 – 10 % timebase for ∆tREC P_12.2.30
and ∆tSS2

adjustable recovery delay ∆tREC 0 – 10 ms selectable 0, 1.0, P_12.2.31

time 2.5, 5.0 and 10 ms;
tSSC to be
considered
adjustable delay time ∆tSS2 0 – 250 ms selectable 0, P_12.2.32
between SS1 and SS2 10,50, 100 and 250
ms; tSSC to be
considered
1) Specified by design, not subject to production test
2) It is recommended to provide the ERR signal to the ERR pin before activating the function again via SPI.
3) Internal and external pull-down resistors have to be considered for failure cases with QUC being off.
4) Considering loss of analog safety ground (AGS1 and AGS2).
12.3 Reaction On Microprocessor Safety Management Unit (SMU - Pin ERR):

12.3.1 Immediate reaction on ERR monitoring failure

The micro processor safety management unit (SMU) indicates a serious error by stopping the toggling signal at
pin ERR, immediate reaction to error signal is set:

Data Sheet 146 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

ERR

SS1

SS2

Δt DET,LF Δt SS2

Figure 60 Flow diagram reaction on SMU signal (ERR signal remains low)
Description:
• The ERR signal stops toggling and remains low.
• This is detected as an error after the expiration of the detection time ΔtDET,LF.
• ΔtDET,LF is measured from the last recognized falling edge.
• The safe state signal 1 (at pin SS1) is pulled to low
• The safe state signal 2 (at pin SS2) is pulled to low after an optional delay time ΔtSS2

ERR

SS1

SS2

Δt DET,LF Δt SS2

Figure 61 Flow diagram reaction on SMU signal (ERR signal remains high)
Description:
• The ERR signal stops toggling and remains high.
• This is detected as an error after the expiration of the detection time ΔtDET,LF.
• ΔtDET,LF is measured from the last recognized rising edge.
• The safe state signal 1 (at pin SS1) is pulled to low
• The safe state signal 2 (at pin SS2) is pulled to low after an optional delay time ΔtSS2

Data Sheet 147 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

ERR

SS1

SS2

t
ΔtSS2
t < ΔtDET,HF
Figure 62 Flow diagram reaction on SMU signal (ERR signal frequency too high)
Description:
• The ERR signal starts toggling with a frequency of fERR,invalid,HF.
• This is detected as an error as soon as the edge-to-edge time is shorter than the detection time ΔtDET,HF.
• The safe state signal 1 (at pin SS1) is pulled to low.
• The safe state signal 2 (at pin SS2) is pulled to low after an optional delay time ΔtSS2.

ERR

SS1

t
tlow < ΔtDET,LF thigh < ΔtDET,LF ΔtDET,LF
thigh > ΔtDET,HF thigh > ΔtDET,LF*
tlow > ΔtDET,HF *applies to t low > ΔtDET,LF in the same way

Figure 63 Flow diagram reaction on SMU signal (duty-cycle different than 50%, tlow or thigh too long)
Description:
• The ERR signal toggles with changing high and low times (duty cycle can vary as well), but tlow and thigh are
in the valid range between tDET,HF and tDET,LF first.
• Then a low pulse of ERR shown in the figure is longer than the detection time tDET,LF.
• This is detected as an error as soon as the edge-to-edge time is longer than the detection time ΔtDET,LF.
• The safe state signal 1 (at pin SS1) is pulled to low.
• The safe state signal 2 (at pin SS2) is pulled to low accordingly after an optional delay time ΔtSS2.(not in figure)
• The condition can be applied to the high pulse being longer than the detection time tDET,LF in the same way.

Data Sheet 148 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

ERR

SS1

t
tlow < ΔtDET,LF thigh < ΔtDET,LF ΔtDET,HF

thigh > ΔtDET,HF tlow < ΔtDET,HF*

tlow > ΔtDET,HF *applies to thigh < ΔtDET,HF in the same way

Figure 64 Flow diagram reaction on SMU signal (duty-cycle different than 50%, tlow or thigh too short)
Description:
• The ERR signal toggles with changing high and low times (duty cycle can vary as well), but tlow and thigh are
in the valid range between tDET,HF and tDET,LF first.
• Then a low pulse of ERR shown in the figure is shorter than the detection time tDET,HF.
• This is detected as an error as soon as the edge-to-edge time is shorter than the detection time ΔtDET,HF.
• The safe state signal 1 (at pin SS1) is pulled to low.
• The safe state signal 2 (at pin SS2) is pulled to low accordingly after an optional delay time ΔtSS2.(not in figure)
• The condition can be applied to the high pulse being shorter than the detection time tDET,HF in the same way.

12.3.2 Recovery delay reaction on ERR monitoring failure

The micro processor safety management unit (SMU) indicates a serious error by stopping the toggling signal at
pin ERR, recovery delay time reaction to error signal is set - the SMU is given time to recover:

ERR

SS1

SS2

t
Δt DET,LF Δt REC Δt SS2
Interrupt

Figure 65 Flow diagram reaction on SMU signal, error longer than recovery delay time
Description:
• The ERR signal stops toggling and remains low (or high).
• This is detected as an error after the expiration of the detection time ΔtDET,LF.
• ΔtDET,LF is measured from the last recognized edge.
• An interrupt is generated after the detection to indicate the start of the recovery delay time ΔtREC

Data Sheet 149 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

• The safe state signal 1 (at pin SS1) is pulled to low after ΔtREC has expired
• The safe state signal 2 (at pin SS2) is pulled to low after an optional delay time ΔtSS2

ERR

SS1

SS2

t
ΔtREC
t < Δt DET,HF ΔtSS2

Interrupt

Figure 66 Flow diagram reaction on SMU signal, error longer than recovery delay time (ERR signal
frequency too high)
Description:
• The ERR signal starts toggling with a frequency of fERR,invalid,HF.
• This is detected as an error as soon as the edge-to-edge time is shorter than the detection time ΔtDET,HF.
• An interrupt is generated after the detection to indicate the start of the recovery delay time ΔtREC
• The safe state signal 1 (at pin SS1) is pulled to low after ΔtREC has expired
• The safe state signal 2 (at pin SS2) is pulled to low after an optional delay time ΔtSS2

ERR

SS1

SS2

Δt DET,LF Δt REC
Interrupt

Figure 67 Flow diagram reaction on SMU signal, error shorter than recovery delay time
Description:
• The ERR signal stops toggling and remains low (or high).
• This is detected as an error after the expiration of the detection time ΔtDET,LF.
• ΔtDET,LF is measured from the last recognized edge.

Data Sheet 150 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

• An interrupt is generated after the detection to indicate the start of the recovery delay time ΔtREC
• Before ΔtREC has expired the ERR signal resumes toggling.
• The safe state signals 1 (at pin SS1) and 2 (at pin SS2) are kept high all the time.

ERR

SS1

SS2

t
ΔtREC
t < Δt DET,HF t > Δt DET,HF

Interrupt

Figure 68 Flow diagram reaction on SMU signal, error shorter than recovery delay time (ERR signal
frequency too high)
Description:
• The ERR signal starts toggling with a frequency of fERR,invalid,HF.
• This is detected as an error as soon as the edge-to-edge time is shorter than the detection time ΔtDET,HF.
• An interrupt is generated after the detection to indicate the start of the recovery delay time ΔtREC
• Before ΔtREC has expired the ERR signal resumes toggling with a valid frequency.
• The safe state signals 1 (at pin SS1) and 2 (at pin SS2) are kept high all the time.
12.4 Reaction On Error Triggered State Transitions

The reset output (ROT) indicates the behavior of the microcontroller related regulators (for details please refer to
chapter voltage monitoring and reset function).

ROT

SS1

SS2

Δt SS2

Figure 69 Flow diagram reaction on an error triggered state transition- soft reset
Description:
• The falling edge of ROT signal indicates an error

Data Sheet 151 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

• Safe state signal 1 (at pin SS1) goes to low immediately with the occurrence of the error
• Safe state signal 2 (at pin SS2) goes to low after a delay time ΔtSS2 which was set by SPI command
• Please mind that in case of an UV event on QUC, a delayed SS2 signal will follow VQUC as it is supplied from
QUC.

ROT

SS1

SS2

Figure 70 Flow diagram reaction on an error triggered state transitions - hard reset
Description:
• The falling edge of ROT signal indicates an error
• Safe state signal 1 (at pin SS1) goes to low immediately with the occurrence of the error
• Safe state signal 2 (at pin SS2) goes to low together with SS1 as the supplying post regulator LDO_µC is
switched off when pin ROT goes to low
12.5 Reaction On Window Watchdog Output (WWO)

The TLF35584 has an implemented window watchdog failure counter (WWDSTAT.WWDECNT). The counter
increments by two at every invalid window watchdog triggering and decrements by one at every valid window
watchdog triggering. (For specification of valid and invalid triggering please refer to chapter functional and window
watchdog).
The status of the window watchdog failure counter is written in the so called window watchdog status counter.
Any incrementation of the window watchdog status counter is indicated by an interrupt. Any decrementation of
the window watchdog status counter is not indicated by an interrupt. The content of the window watchdog status
counter cannot be less than zero.
The threshold for activating the safe state signals SS1 and SS2 Σ WWO can be changed in INIT, NORMAL and
WAKE state. (WDCFG0.WWDETHR)
The content of the status counter will be compared to the programmed threshold Σ WWO
(RWDCFG0.WWDETHR). If the content of the status counter is equal or higher than Σ WWO, the safe state signals
SS1 and SS2 will be activated (low).

Data Sheet 152 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

Valid WWD triggering

Invalid WWD triggering

7
∑ WWO 6
5
4
3
2
1
0

Window watchdog failure counter

2 4 3 5 7
Interrupt

SS1

SS2

Δt SS2

Figure 71 Flow diagram reaction on WWO

Description:
• The threshold Σ WWO is set to 6 (example)
• An invalid watchdog triggering increments the window watchdog status counter by two, this is indicated by an
interrupt
• A valid watchdog triggering decrements the window watchdog status counter by one, this is not indicated by
an interrupt
• The status counter value 7 is recognized as an error
• Safe state signal 1 (at pin SS1) goes to low immediately with the counter status change
• Safe state signal 2 (at pin SS2) goes to low after a delay time ΔtSS2 which was set by SPI command

12.6 Reaction On Functional Watchdog Output (FWO)

The TLF35584 has an implemented functional watchdog failure counter (FWDSTAT1.FWDECNT). The counter
increments by two at every invalid functional watchdog triggering and decrements by one at every valid functional
watchdog triggering. (For specification of valid and invalid triggering please refer to chapter functional and window
watchdog).
The status of the functional watchdog failure counter is written in the so called functional watchdog status counter.
Any incrementation of the functional watchdog status counter is indicated by an interrupt. Any decrementation of
the functional watchdog status counter is not indicated by an interrupt. The content of the functional watchdog
status counter cannot be less than zero.

Data Sheet 153 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

The threshold for activating the safe state signals SS1 and SS2 Σ FWO can be changed in INIT, NORMAL and
WAKE state. (WDCFG1.FWDETHR)
The content of the status counter will be compared to the programmed threshold Σ FWO (RWDCFG1.FWDETHR).
If the content of the status counter is equal or higher than Σ FWO, the safe state signals SS1 and SS2will be
activated (low).
Valid FWD triggering

Invalid FWD triggering

7
∑ FWO 6
5
4
3
2
1
0

Functional watchdog failure counter

2 4 3 5 7
Interrupt

SS1

SS2

Δt SS2

Figure 72 Flow diagram reaction on FWO

Description:
• The threshold Σ FWO is set to 6 (example)
• An invalid watchdog triggering increments the functional watchdog status counter by two, this is indicated by
an interrupt
• A valid watchdog triggering decrements the functional watchdog status counter by one, this is not indicated by
an interrupt
• The status counter value 7 is recognized as an error
• Safe state signal 1 (at pin SS1) goes to low immediately with the counter status change
• Safe state signal 2 (at pin SS2) goes to low after a delay time ΔtSS2 which was set by SPI command

12.7 Reaction On Thermal Shutdown (TSD)

The thermal shutdown (TSD) indicates temperature overstress: on the chip: As a consequence all pre and post
regulators will be shut down immediately.

Data Sheet 154 Rev. 2.0, 2017-03-16

 TLF35584

Safe State Control Function

TSD

SS1

SS2

Figure73 Flow diagram reaction on TSD

Description:
• The rising edge of TSD signal (internal) is recognized as an error
• Safe state signal 1 (at pin SS1) goes to low immediately with the rising edge of TSD
• Safe state signal 2 (at pin SS2) goes to low together with SS1 as the supplying post regulator LDO_µC is
switched off when pin ROT goes to low

Data Sheet 155 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

13 SPI - Serial Peripheral Interface

13.1 Introduction

Main functions
The serial peripheral interface bus or SPI bus is a synchronous serial data link that operates in full duplex mode.
The TLF35584 communicates in slave mode where the master (µC) initiates the data frame. The TLF35584 should
be addressed via a dedicated chip select line. This allows a connection of other slave devices to the SPI bus.

Data transmission
To begin a communication, the µC first configures the clock, using a frequency less than or equal to the maximum
frequency the TLF35584 supports. The µC pulls down the chip select for the TLF35584.

Functional description
SPI basic access: All data on MOSI (pin SDI) is captured on the rising edge of SPI clock signal (pin SCL) and
shifted on the falling edge of SPI clock signal (pin SCL). The same methodology needs to be applied in the SPI
master for MISO (SDO). A read operation has to start with CMD-bit being 1’b0 and a write operation has to start
with CMD-bit being 1’b1.
In case of a write operation is performed the written command to SDI is looped back to SDO.
The parity is calculated for the output data stream in case a read operation is performed. The data for the
calculation consists of 1’b1, status [5:0] and rd_data[7:0]. The parity bit is set to ‘1’ if the number of ‘1’ in the output
data stream is odd, i.e.XOR function between all 15 bits to send out.
Parity is checked on write data. The parity is calculated on the incoming bit stream for the cmd bit, the six address
bits and the eight data bits.
Configuration via SPI can be done anytime, if the state machine (FSM) is in INIT state, NORMAL state, WAKE
state or SLEEP state. During SLEEP state the SPI has a decreased maximum clock frequency, for details please
refer to Table 19.

SPI access timing can be found in the following diagram:

Figure 74 SPI - frame in normal mode

SPI MISO:

Data Sheet 156 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

• During write, data from MOSI is directly looped back, during read, the addressed register content will be
provided in the very same SPI frame
• The cmd bit is always set to 1’b1. All other status bits are set to zero.

Figure 75 SPI - Timings

Table 19 Electrical Characteristics: SPI - Timings

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

CLK_SPI Operating fSPI_clk – – 10 MHz 1) P_13.1.1

Frequency

CLK_SPI Operating fSPI_clk – – 1.5 MHz SLEEP state P_13.1.2

Frequency

CLK Signal duty cycle 45 50 55 % P_13.1.3

DSCL
CLK_SPI Operating tSPI_clk 100 – – ns P_13.1.4
Period

CLK_SPI High Time 45 – – ns P_13.1.5

tSPI_wsclkh
CLK_SPI Low Time 45 – – ns P_13.1.6
tSPI_wsclkl
CLK_SPI Fall Time tSPI_clkf – – 0.1*tSPI_fact [ns] tSPI_fact ≤ tSPI_clk ; P_13.1.7
100 ns ≤ tSPI_fact
≤ 1 µs
CLK_SPI Rise Time tSPI_clkr – – 0.1*tSPI_fact [ns] tSPI_fact ≤ tSPI_clk ; P_13.1.8
100 ns ≤ tSPI_fact
≤ 1 µs
CLK_SPI Lead Time 100 – – ns P_13.1.9
tSPI_lead

Data Sheet 157 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

CLK_SPI Lag Time 50 – – ns P_13.1.10

tSPI_lag
SPI Chip Select (SCS) tSPI_csr – – 0.2*tSPI_fact [ns] tSPI_fact ≤ tSPI_lag ; P_13.1.11
Rise Time 50 ns ≤ tSPI_fact ≤
500 ns
Table 19 Electrical Characteristics: SPI - Timings (cont’d)
VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

SPI Chip Select (SCS) tSPI_csf – – 0.2*tSPI_fact [ns] tSPI_fact ≤ tSPI_lead; P_13.1.12
Fall Time 100 ns ≤ tSPI_fact
≤ 1 µs
SPI Data Input (SDI) tSPI_su 10 – – ns P_13.1.13
Setup

SPI Data Input (SDI) tSPI_hi 10 – – ns P_13.1.14

Hold Time

SPI Data Output (SDO) tSPI_v – – (0.1*tSPI_fact) [ns] CSDO,load= 50 pF; P_13.1.15
Valid after CLK_SPI +36
tSPI_fact ≥ tSPI_clkf ;
10 ns ≤ tSPI_fact ≤
100 ns
SPI Write Propagation tSPI_wpd – – 35 ns P_13.1.16
Delay SDI to SDO

SPI Data Output (SDO) tSPI_a – – 50 ns CSDO,load = 50 pF P_13.1.17

Access

SPI Data Output (SDO) tSPI_dis 100 ns CSDO,load = 50 pF P_13.1.18

Disable Time –

Sequential Transfer tSPI_td 350 – – ns P_13.1.19

Delay

Sequential Transfer tSPI_td 2 – – µs SLEEP state P_13.1.20

Delay

Frame duration (SCS tSPI_fl – 1.85 ms P_13.1.21

low)

1) For max. achievable CLK_SPI operating frequency, please consider the CLK_SPI rise- and fall times (tSPI_clkr and tSPI_clkf).

SPI errors:
• Wrong parity bit during write, write data is ignored.
• Write to invalid address, write data is ignored.

Data Sheet 158 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

• Wrong number of SPI clock cycles while SCS is low, write data is ignored, read data is provided by the device
with each SPI clock cycle.
• Read from invalid address (all data bits zero returned on MISO for read data). For this case the parity bit is
inverted/corrupted after complete calculation by the device.
• Invalid frame duration, write data is ignored and the output driver for SDO is turned off internally by the device
after tSPI_fl. Read data is provided with each SPI clock cycle as long as SCS is low for less than tSPI_fl.
• If the number of SPI clock cycles is different than 16 and an invalid frame duration error is detected by the
device, the invalid frame duration status flag is set and the wrong number of SPI clock cycle status flag is set.
In case of an SPI error occurs, an interrupt will be generated.
Interrupts on SPI errors are initiated only after SCS has been driven high or the frame time-out occurred.
13.2 SPI Write Access To Protected Registers

Certain internal registers (SYSPCFG0, SYSPCFG1, WDCFG0, WDCFG1, FWDCFG, WWDCFG0, WWDCFG1)
need to be protected against being overwritten accidently. The status of the protection can be checked by reading
the LOCK bit in the register PROTSTAT.
Write access to these registers is only possible after a dedicated 32 bit UNLOCK sequence has been sent via
SPI. The four bytes need to be send without any other SPI write access in between. Error in doing so will reset
the sequence detection, i.e. a new UNLOCK sequence has to be send. An interrupt is generated and the number
of successfully detected UNLOCK sequence bytes is set to zero if a write access to any other register then
PROTCFG is detected in between. The access to the protected registers is possible in INIT, NORMAL and WAKE
state.
The UNLOCK sequence consists of a 32-bit sequence of 4 consecutive bytes (1: 0xAB; 2:0xEF; 3:0x56; 4:0x12)
which have to be sent with no other SPI write access in between. The correctness of every written byte can be
checked by reading the register PROTSTAT. Once the UNLOCK sequence has been performed successfully,
any protected configuration request register can be written. In order to ensure proper writing to the protected
configuration request registers the microcontroller shall read back the register values and verify the correctness
by checking data. The data bits written to the protected configuration request registers are send back inverted
during read operation, that means the microcontroller can calculate an XOR of the register data read and
expected. The results should be 0xFF in case of correct register data. The TLF35584 will not check the correctness
of the values in the register.
All protected configuration request register values are captured by the respective functions only after a successful
LOCK sequence has been performed. A successful LOCK sequence consists of a 32-bit sequence of 4
consecutive bytes (1: 0xDF; 2:0x34; 3:0xBE; 4:0xCA) which have to be send with no other SPI write access in
between. The correctness of every written byte can be checked by reading the register PROTSTAT.
Error in doing so will reset the sequence detection, i.e. a new LOCK sequence has to be sent. In this case (any
SPI write access in between LOCK sequence) an interrupt is generated.
Upon detection of a successful LOCK sequence the configuration registers and all internal functions are updated
with the values from the protected configuration request registers. It is the responsibility of the uC to ensure all
registers are configured properly by either writing a new value into a particular register or by reading back a
register which is supposed to be unchanged. Partial reconfiguration of the protected registers, i.e. configuring just
a single function and leaving other functions unchanged is not supported as with the successful LOCK sequence
all protected configuration request registers are taken over into the configuration (RSYSPCFG0, RSYSPCFG1,
RWDCFG0, RWDCFG1, RFWDCFG, RWWDCFG0, RWWDCFG1).
After the LOCK sequence an internal configuration time of max. 60 µs has to be considered to ensure that the
new configuration is taken over.
Affected functions:
• All watchdog configuration registers for WWD and FWD.

Data Sheet 159 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

• Enabling of WD while the device is in SLEEP state

• All Error pin monitoring configuration registers
• Enabling of Error pin monitoring while the FSM is in SLEEP
• A dedicated register to enable or disable the STDBY LDO
• Configuration of SS2 delay time failure events not leading to FAILSAFE state Read access to any protected
configuration request register is always possible.

13.3 SPI Write Initiated State Transition Request And Regulator Configuration

A State machine transition can be initiated via SPI command(s). In case the state of any selectable voltage source
(post regular) is expected to change for the next state, this information has to be sent together with the command
into the same register. In case the setting for a particular voltage source (post regulator) is supposed to change
but the state needs to be unchanged, the same approach can be applied. This basically means, the SPI command
contains the current state of the FSM but a different setting for configurable voltage source (post regulator).
In order to request a state transition and/or a change of the LDO configuration the request data have to be written
to two separated registers DEVCTRL and DEVCTRLN after each other consequently. The data written to
DEVCTRLN have to be inverted bitwise compared to the data written to DEVCTRL. The request will be only
accepted when the two registers are written consecutively after each other (first DEVCTRL and second
DEVCTRLN) and will be taken over with the rising edge of the CS at the end of the second command.
In case of an invalid request (wrong sequence or DEVCTRLN not inverted to DEVCTRL) it will be rejected, an
interrupt is generated and the corresponding status flag (NO_OP) is set. Incase of an invalid state transition
request according to the State Machine in Chapter 11 the request is ignored without issuing an interrupt.

13.4 Registers Description

Table 20 Abbreviations
*R0) Registers that are being reset only in case of a POR.

*R1) Registers that are being reset only in case of STANDBY and a POR.

*R2) Registers that are being reset only in case of FAILSAFE, STANDBY and a POR.

*R3) Registers that are being reset in case of “Move to INIT” event, FAILSAFE, STANDBY and
a
POR.
r Bits that are readable (read)

rw Bits that are readable and writable (read-write)

rwp Bits that are readable and writable but protected by register PROTCFG (read-
writeprotected)

Data Sheet 160 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

rw1c Bits that are readable and to clear the bit you have to write a 1 to it. (read-write-1-to-clear).
Flag-bits are updated based on the occurred condition.

rwhc Bits that are readable and writable after writing the operation is triggered, once this is done
successfully the bit is cleared by hardware. (read-write-hardware-cleared)

rwhu Bits that are readable and writable, after the operation the bit is updated by hardware.
(readwrite-hardware-updated)

Module Base Address End Address Note

BusInterface 0H 3FH Slave interface

Table 21 Register Address Space

Table 22 Register Overview

Register Short Name Register Long Name Offset Address Reset Value

DEVCFG0 Device configuration 0 *R2) 00H 08H

DEVCFG1 Device configuration 1 *R0) 01H 06H

DEVCFG2 Device configuration 2 *R2) 02H 00H

PROTCFG Protection register *R2) 03H 00H

SYSPCFG0 Protected System configuration request 0 *R1) 04H 01H

SYSPCFG1 Protected System configuration request 1 *R2) 05H 00H

WDCFG0 Protected Watchdog configuration request 0 *R2) 06H 9BH

WDCFG1 Protected Watchdog configuration request 1 *R2) 07H 09H

FWDCFG Protected Functional watchdog configuration 08H 0BH

request *R2)

WWDCFG0 Protected Window watchdog configuration request 09H 06H

0 *R2)

WWDCFG1 Protected Window watchdog configuration request 0AH 0BH

1 *R2)

RSYSPCFG0 System configuration 0 status *R0) 0BH 01H

RSYSPCFG1 System configuration 1 status *R3) 1) 0CH 00H

RWDCFG0 Watchdog configuration 0 status *R3) 0DH 9BH

Table 22 Register Overview (cont’d)
Register Short Name Register Long Name Offset Address Reset Value
RWDCFG1 Watchdog configuration 1 status *R3) 0EH 09H
RFWDCFG Functional watchdog configuration status *R3) 0FH 0BH

Data Sheet 161 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

RWWDCFG0 Window watchdog configuration 0 status *R3) 10H 06H

RWWDCFG1 Window watchdog configuration 1 status *R3) 11H 09H
WKTIMCFG0 Wake timer configuration 0 *R2) 12H 00H
WKTIMCFG1 Wake timer configuration 1 *R2) 13H 00H
WKTIMCFG2 Wake timer configuration 2 *R2) 14H 00H
DEVCTRL Device control request *R2) 15H 00H
DEVCTRLN Device control inverted request *R2) 16H 00H
WWDSCMD Window watchdog service command *R2) 17H 00H
FWDRSP Functional watchdog response command *R2) 18H 00H
FWDRSPSYNC Functional watchdog response command with 19H 00H
synchronization *R2)
SYSFAIL Failure status flags *R1) 1AH 00H
INITERR Init error status flags *R2) 1BH 00H
IF Interrupt flags *R2) 1CH 00H
SYSSF System status flags *R2) 1DH 00H
WKSF 1EH 00H
Wakeup status flags *R2)
SPISF SPI status flags *R2) 1FH 00H
MONSF0 Monitor status flags 0 *R1) 20H 00H
MONSF1 Monitor status flags 1 *R1) 21H 00H
MONSF2 Monitor status flags 2 *R2) 22H 00H
MONSF3 Monitor status flags 3 *R1) 23H 00H
OTFAIL Over temperature failure status flags *R1) 24H 00H
OTWRNSF Over temperature warning status flags *R2) 25H 00H
VMONSTAT Voltage monitor status *R2) 26H 00H
DEVSTAT Device status *R2) 27H 00H
PROTSTAT Protection status *R1) 28H 01H
WWDSTAT Window watchdog status *R3) 29H 00H
FWDSTAT0 Functional watchdog status 0 *R3) 2AH 30H
FWDSTAT1 Functional watchdog status 1 *R3) 2BH 00H
1)
ABIST_CTRL0 ABIST control0 *R2) 2CH 00H
ABIST_CTRL1 ABIST control1 *R2) 2DH 00H
ABIST_SELECT0 ABIST select 0 *R2) 2EH 00H
ABIST_SELECT1 ABIST select 1 *R2) 2FH 00H
ABIST_SELECT2 ABIST select 2 *R2) 30H 00H
GTM Global testmode *R2) 3FH 02H
BCK_FREQ_CHANGE Buck switching frequency change *R2) 31H 00H
Table 22 Register Overview (cont’d)
Register Short Name Register Long Name Offset Address Reset Value

BCK_FRE_SPREAD Buck Frequency spread *R2) 32H 00H

Data Sheet 162 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

BCK_MAIN_CTRL Buck main control *R2) 33H 00H

1) Reset class of single bits is different. See register for details.

The registers are addressed wordwise.

13.4.1 Device registers

Device configuration 0 *R2)

DEVCFG0 Offset Reset Value

Device configuration 0 *R2) 00H 08H

7 6 5 4 3 2 1 0
WKTIMCY
WKTIMEN C nu TRDEL

rw rwrw

Field Bits Type Description

WKTIMEN 7 rw Wake timer enable
0D Wake timer disabled
1D Wake timer enabled in SLEEP or STANDBY state
Reset: 0H
WKTIMCYC 6 rw Wake timer cycle period
0D 10 us
1D 10 ms
Reset: 0H
nu 5:4 none
Reset: 0H
TRDEL 3:0 rw Transition delay into low power states
For STANDBY and SLEEP transition. Defined as a step of 100 us.
0D 100 us
1D 200 us

2D 300 us

..D ...

15D 1600 us
Reset: 8H

Data Sheet 163 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

Device configuration 1 *R0)

DEVCFG1
Device configuration 1 *R0) 01H 06H

7 6 5 4 3 2 1 0

nu RESDEL

rw

Field Bits Type Description

nu 7:3 none
Reset: 00H
RESDEL 2:0 rw Reset release delay time
0D 200 us
1D 400 us

2D 800 us

3D 1ms

4D 2 ms

5D
4 ms
6D 10 ms

7D 15 ms
Reset: 6H
Device configuration 2 *R2)

DEVCFG2
Device configuration 2 *R2) 02H 00H

7 6 5 4 3 2 1 0

EVCEN STU FRE CMONEN CTHR ESYNPHA ESYNEN

r r r rw rw rw rw

Field Bits Type Description

Data Sheet 164 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

EVCEN 7 r External core supply enable status
0D External core supply disabled
1D External core supply enabled
Reset: 0H
STU 6 r Step-up converter enable status
0D Disabled
1D Enabled
Reset: 0H
FRE 5 r Step-down converter frequency selection status
0D Step-down converter runs on low frequency range
1D Step-down converter runs on high frequency range
Reset: 0H
CMONEN 4 rw QUC current monitor enable for transition to a low power state
For STANDBY and SLEEP transition. The setting is overwritten in
SLEEP as current monitoring is always enabled.
0D Disabled
1D Enabled
Reset: 0H
CTHR 3:2 rw QUC current monitoring threshold value
0D 10 mA
1D 30 mA
2D 60 mA
3D 100 mA
Reset: 0H
ESYNPHA 1 rw External synchronization output phase
0D No phase shift
1D 180 phase shift
Reset: 0H
ESYNEN 0 rw Synchronization output for external switchmode regulator enable
0D Disable
1D Enable
Reset: 0H
Protection register *R2)

PROTCFG
Protection register *R2) 03H 00H

7 6 5 4 3 2 1 0

Data Sheet 165 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

KEY

rw

Field Bits Type Description

KEY 7:0 rw Protection key
Protection key register to request write access to protected registers.
Unlock: write 32-bit sequence of 4 consecutive bytes
(1: 0xAB 2:0xEF 3:0x56 4:0x12) to unlock access to protected registers.
Lock: write 32-bit sequence of 4 consecutive bytes
(1: 0xDF 2:0x34 3:0xBE 4:0xCA) to lock access to protected registers. All
configured values are applied to SSC and WD module after the lock.
ABH Key 1 to unlock protected registers.
EFH Key 2 to unlock protected registers.

56H Key 3 to unlock protected registers.

12H Key 4 to unlock protected registers.

DFH Key 1 to lock protected registers.

34H Key 2 to lock protected registers.

BEH Key 3 to lock protected registers.

CAH Key 4 to lock protected registers.

Reset: 00H
Protected System configuration request 0 *R1)

SYSPCFG0
Protected System configuration request 0 04H 01H
*R1)

7 6 5 4 3 2 1 0

nu STBYEN

Field Bits Type Description

nu 7:1 none not used bits shall be written as 0 and will always return 1 upon read
Reset: 00H

Data Sheet 166 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

STBYEN 0 rwp Request standby regulator QST enable
Valid for all device states except FAILSAFE.
0D Disabled
1D Enabled
Reset: 1H
rwp

Data Sheet 167 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

Protected System configuration request 1 *R2)

SYSPCFG1
Protected System configuration request 1 05H 08H
*R2)

7 6 5 4 3 2 1 0
ERRSLPE ERRRECE
SS2DEL N ERREN N ERRREC

rwp rwp rwp rwp rwp

Field Bits Type Description

SS2DEL 7:5 rwp Request safe state 2 delay
Applied for transitions from NORMAL to INIT, WAKE and SLEEP state.
0D no delay
1D 10 ms

2D 50 ms

3D 100 ms

4D 250 ms
Rese
t: 0H
ERRSLPEN 4 rwp Request ERR pin monitor functionality enable while the system is in
SLEEP
0D ERR pin monitor is disabled in SLEEP
1D ERR pin monitor can be active in SLEEP depending on ERREN
bit value.
Reset: 0H
ERREN 3 rwp Request ERR pin monitor enable
0D Disabled
1D Enabled
Reset: 1H
ERRRECEN 2 rwp Request ERR pin monitor recovery enable
0D Disabled
1D Enabled
Reset: 0H

Data Sheet 168 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

ERRREC 1:0 rwp Request ERR pin monitor recovery time
0D 1 ms
1D 2.5 ms
2D 5 ms
3D 10 ms
Reset: 0H
Protected Watchdog configuration request 0 *R2)

WDCFG0
Protected Watchdog configuration request 0 06H 9BH
*R2)

7 6 5 4 3 2 1 0

WWDETHR WWDEN FWDEN WWDTSEL WDCYC

rwp rwp rwp rwp rwp

Field Bits Type Description

WWDETHR 7:4 rwp Request window watchdog error threshold
WWD error threshold to generate reset and enter into INIT state.
Reset: 9H
WWDEN 3 rwp Request window watchdog enable
0D Disabled
1D Enabled
Reset: 1H
FWDEN 2 rwp Request functional watchdog enable
0D Disabled
1D Enabled
Reset: 0H
WWDTSEL 1 rwp Request window watchdog trigger selection
This is ignored when window watchdog is disabled.
0D External WDI input used as a WWD trigger
1D WWD is triggered by SPI write to WWDSCMD register
Reset: 1H
WDCYC 0 rwp Request watchdog cycle time
0D 0,1 ms tick period
1D 1 ms tick period
Reset: 1H
Protected Watchdog configuration request 1 *R2)

Data Sheet 169 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

WDCFG1
Protected Watchdog configuration request 1 07H 09H
*R2)

7 6 5 4 3 2 1 0

nu WDSLPEN FWDETHR

rwp rwp

Field Bits Type Description

nu 7:5 none not used bits shall be written as 0 and will always return 1 upon read
Reset: 0H
WDSLPEN 4 rwp Request watchdog functionality enable while the device is in SLEEP
0D Disabled
1D Enabled, the WD will work based on individual configuration
(WWDEN & FWDEN) settings while the system is in SLEEP mode
Reset: 0H
FWDETHR 3:0 rwp Request functional watchdog error threshold
FWD error threshold to generate reset and enter into INIT state.
Reset: 9H
Protected Functional watchdog configuration request *R2)

FWDCFG Offset Reset Value

Protected Functional watchdog configuration 08H 0BH
request *R2)
7 6 5 4 3 2 1 0

nu WDHBTP

rwp

Field Bits Type Description

nu 7:5 none not used bits shall be written as 0 and will always return 1 upon read
Reset: 0H

Data Sheet 170 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Field Bits Type Description

WDHBTP 4:0 rwp Request functional watchdog heartbeat timer period
Defined as a multiple of 50 watchdog cycles (RWDCFG0.WDCYC).
0D 50 wd cycles
1D 100 wd cycles

2D 150 wd cycles

..D ...

31D 1600 wd cycles

Reset: 0BH
Protected Window watchdog configuration request 0 *R2)

WWDCFG0 Offset Reset Value

Protected Window watchdog configuration 09H 06H
request 0 *R2)

nu CW

7 6 5 4 3 2 1 0

rwp

Field Bits Type Description

nu 7:5 none not used bits shall be written as 0 and will always return 1 upon read
Reset: 0H
CW 4:0 rwp Request window watchdog closed window time
Defined as a multiple of 50 watchdog cycles (RWDCFG0.WDCYC).
0D 50 wd cycles
1D 100 wd cycles

2D 150 wd cycles

..D ...

31D 1600 wd cycles

Reset: 06H
Protected Window watchdog configuration request 1 *R2)

WWDCFG1 Offset Reset Value

Protected Window watchdog configuration 0AH 0BH
request 1 *R2)
7 6 5 4 3 2 1 0

nu OW

rwp

Data Sheet 171 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Field Bits Type Description

nu 7:5 none not used bits shall be written as 0 and will always return 1 upon read
Reset: 0H
OW 4:0 rwp Request window watchdog open window time
Defined as a multiple of 50 watchdog cycles (RWDCFG0.WDCYC).
0D 50 wd cycles
1D 100 wd cycles

2D 150 wd cycles

..D
...
31D 1600 wd cycles
Reset: 0BH
System configuration 0 status *R0)

RSYSPCFG0 Offset Reset Value

System configuration 0 status *R0) 0BH 01H
7 6 5 4 3 2 1 0

nu STBYEN

Field Bits Type Description

nu 7:1 none
Reset: 00H
STBYEN 0 r Standby regulator QST enable status
Current configuration of standby regulator QST enable.
Valid for all device states except FAILSAFE.
0D Disabled
1D Enabled
Reset: 1H
System configuration 1 status *R3) 1)

RSYSPCFG1
System configuration 1 status *R3) 0CH 08H

7 6 5 4 3 2 1 0
ERRSLPE
SS2DEL N ERREN ERRRECEN ERRREC

r r r r r

Field Bits Type Description

1 ) Reset class of single bits is different. See register for details.

Data Sheet 172 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

SS2DEL 7:5 r Safe state 2 delay status
Current configuration of safe state 2 delay applied for transitions from
NORMAL to INIT, WAKE and SLEEP state.
Bits have different reset class than whole register. The Bits are reset
according to *R1)
0D no delay
1D 10 ms

2D 50 ms

3D
100 ms
4D 250 ms
Reset: 0H
ERRSLPEN 4 r ERR pin monitor functionality enable status while the device is in
SLEEP
Current configuration of ERR pin monitor functionality enable for SLEEP.
0D ERR pin monitor is disabled in SLEEP
1D ERR pin monitor can be active in SLEEP depending on ERREN
bit value.
Reset: 0H
ERREN 3 r ERR pin monitor enable status
Current configuration of ERR pin monitor enable.
0D Disabled
1D Enabled
Reset: 1H
ERRRECEN 2 r ERR pin monitor recovery enable status
Current configuration of ERR pin monitor recovery enable.
0D Disabled
1D Enabled
Reset: 0H
Field Bits Type Description
ERRREC 1:0 r ERR pin monitor recovery time status
Current configuration of ERR pin monitor recovery time.
0D 1 ms
1D 2.5 ms
2D 5 ms
3D 10 ms
Reset: 0H
Watchdog configuration 0 status *R3)

RWDCFG0 Offset Reset Value

Watchdog configuration 0 status *R3) 0DH 9BH
7 6 5 4 3 2 1 0

WWDETHR WWDEN FWDEN WWDTSEL WDCYC

Data Sheet 173 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

r r r r r

Field Bits Type

Description
WWDETHR 7:4 r Window watchdog error threshold status
Current configuration of WWD error threshold to generate reset and enter
into INIT state.
Reset: 9H
WWDEN 3 r Window watchdog enable status
Current configuration of WWD enable.
0D Disabled
1D Enabled
Reset: 1H
FWDEN 2 r Functional watchdog enable status
Current configuration of FWD enable.
0D Disabled
1D Enabled
Reset: 0H
WWDTSEL 1 r Window watchdog trigger selection status
Current configuration of WWD trigger selection. This is ignored when
window watchdog is disabled.
0D External WDI input used as a WWD trigger
1D WWD is triggered by SPI write to WWDSCMD register
Reset: 1H
WDCYC 0 r Watchdog cycle time status
Current configuration of watchdog cycle time.
0D 0,1 ms tick period
1D 1 ms tick period
Reset: 1H
Watchdog configuration 1 status *R3)

RWDCFG1
Watchdog configuration 1 status *R3) 0EH 09H

7 6 5 4 3 2 1 0

nu WDSLPEN FWDETHR

r r

Field Bits Type Description

nu 7:5 none
Reset: 0H

Data Sheet 174 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

WDSLPEN 4 r Watchdog functionality enable status while the device is in SLEEP
Current configuration of WD functionality enable for SLEEP.
0D Disabled
1D Enabled, the WD will work based on individual configuration
(WWDEN & FWDEN) settings while the system is in SLEEP mode
Reset: 0H
FWDETHR 3:0 r Functional watchdog error threshold status
Current configuration of FWD error threshold to generate reset and enter
into INIT state.
Reset: 9H
Functional watchdog configuration status *R3)

RFWDCFG Offset Reset Value

Functional watchdog configuration status 0FH 0BH
*R3)
7 6 5 4 3 2 1 0

nu WDHBTP

Field Bits Type Description

nu 7:5 none
Reset: 0H
Field Bits Type Description
WDHBTP 4:0 r Functional watchdog heartbeat timer period status
Current configuration of FWD heartbeat timer period defined as a multiple
of 50 watchdog cycles (RWDCFG0.WDCYC).
0D 50 wd cycles
1D 100 wd cycles

2D 150 wd cycles

..D ...

31D 1600 wd cycles

Reset: 0BH
Window watchdog configuration 0 status *R3)

RWWDCFG0 Offset Reset Value

Window watchdog configuration 0 status 10H 06H
*R3)
7 6 5 4 3 2 1 0

nu CW

Data Sheet 175 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Field Bits Type Description

nu 7:5 none
Reset: 0H
CW 4:0 r Window watchdog closed window time status
Current configuration of WWD closed window time defined as a multiple
of 50 watchdog cycles (RWDCFG0.WDCYC).
0D 50 wd cycles
1D 100 wd cycles

2D 150 wd cycles

..D ...

31D 1600 wd cycles

Reset: 06H
Window watchdog configuration 1 status *R3)

RWWDCFG1
Window watchdog configuration 1 status 11H 0BH
*R3)

7 6 5 4 3 2 1 0

nu OW

Field Bits Type Description

nu 7:5 none
Reset: 0H
OW 4:0 r Window watchdog open window time status
Current configuration of WWD open window time defined as a multiple of
50 watchdog cycles (RWDCFG0.WDCYC).
0D 50 wd cycles
1D 100 wd cycles

2D 150 wd cycles

..D ...

31D 1600 wd cycles

Reset: 0BH

Data Sheet 176 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

Wake timer configuration 0 *R2)

WKTIMCFG0
Wake timer configuration 0 *R2) 12H 00H

7 6 5 4 3 2 1 0

TIMVALL

rw

Field Bits Type Description

TIMVALL 7:0 rw Wake timer value lower bits

Bits (7:0) of wake time defined as a multiple of wake timer cycles
(DEVCFG0.WKTIMCYC).
Reset: 00H
Wake timer configuration 1 *R2)

WKTIMCFG1 Offset Reset Value

Wake timer configuration 1 *R2) 13H 00H

7 6 5 4 3 2 1 0

TIMVALM

rw

Field Bits Type Description

TIMVALM 7:0 rw Wake timer value middle bits

Bits (15:8) of wake time defined as a multiple of wake timer cycles
(DEVCFG0.WKTIMCYC).
Reset: 00H
Wake timer configuration 2 *R2)

WKTIMCFG2
Wake timer configuration 2 *R2) 14H 00H

7 6 5 4 3 2 1 0

Data Sheet 177 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

TIMVALH

rw

Field Bits Type Description

TIMVALH 7:0 rw Wake timer value higher bits

Bits (23:16) of wake time defined as a multiple of wake timer cycles
(DEVCFG0.WKTIMCYC).
Reset: 00H

Device control request *R2)

DEVCTRL
Device control request *R2) 15H 00H

7 6 5 4 3 2 1 0

TRK2EN TRK1EN COMEN nu VREFEN STATEREQ

rw rw rw rw rwhc

Field Bits Type Description

TRK2EN 7 rw Request tracker2 QT2 enable
0D QT2 will be disabled after valid request
1D QT2 will be enabled after valid request
Reset: 0H
TRK1EN 6 rw Request tracker1 QT1 enable
0D QT1 will be disabled after valid request
1D QT1 will be enabled after valid request
Reset: 0H
COMEN 5 rw Request communication ldo QCO enable
0D QCO will be disabled after valid request
1D QCO will be enabled after valid request
Reset: 0H
nu 4 none
Reset: 0H

Data Sheet 178 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

VREFEN 3 rw Request voltage reference QVR enable
0D QVR will be disabled after valid request
1D QVR will be enabled after valid request
Reset: 0H
STATEREQ 2:0 rwhc Request for device state transition
Cleared to 000 by the HW after the request is processed. After writing a
new state value a user should not change the value before it's cleared by
HW.
7D RESERVED
6D RESERVED

5D WAKE

4D STANDBY

3D SLEEP

2D NORMAL

1D INIT

0D NONE
Reset: 0H
Device control inverted request *R2)

DEVCTRLN
Device control inverted request *R2) 16H 00H

7 6 5 4 3 2 1 0

TRK2EN TRK1EN COMEN nu VREFEN STATEREQ

rw rw rw rw rwhc

Field Bits Type Description

TRK2EN 7 rw Request tracker2 QT2 enable
1D QT2 will be disabled after valid request
0D QT2 will be enabled after valid request
Reset: 0H

Data Sheet 179 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

TRK1EN 6 rw Request tracker1 QT1 enable
1D QT1 will be disabled after valid request
0D QT1 will be enabled after valid request
Reset: 0H
COMEN 5 rw Request communication ldo QCO enable
1D QCO will be disabled after valid request
0D QCO will be enabled after valid request
Reset: 0H
nu 4 none
Reset: 0H
VREFEN 3 rw Request voltage reference QVR enable
1D QVR will be disabled after valid request
0D QVR will be enabled after valid request
Reset: 0H
STATEREQ 2:0 rwhc Request for device state transition
Cleared to 000 by the HW after the request is processed. After writing a
new state value a user should not change the value before it's cleared by
HW.
7D NONE
6D INIT

5D NORMAL

4D SLEEP

3D STANDBY

2D WAKE

1D RESERVED

0D RESERVED
Reset: 0H
Window watchdog service command *R2)

WWDSCMD
Window watchdog service command *R2) 17H 00H

7 6 5 4 3 2 1 0
TRIG_ST
ATUS nu TRIG

Data Sheet 180 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

r rw

Field Bits Type Description

TRIG_STATU 7 r Last SPI trigger received

S Reset: 0H

nu 6:1 none
Reset: 00H
TRIG 0 rw Window watchdog SPI trigger command
Read TRIG_STATUS bit first and write inverted value to TRIG bit.
Reset: 0H

Functional watchdog response command *R2)

FWDRSP Offset Reset Value
Functional watchdog response command 18H 00H
*R2)
7 6 5 4 3 2 1 0

FWDRSP

rw

Field Bits Type Description

FWDRSP 7:0 rw Functional watchdog response

Write functional watchdog response bytes to this field.
Reset: 00H

Data Sheet 181 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Reset Value
Functional watchdog response command with synchronization *R2)

FWDRSPSYNC Offset
Functional watchdog response command 19H 00H
with synchronization *R2)

7 6 5 4 3 2 1 0

FWDRSPS

rw

Field Bits Type Description

FWDRSPS 7:0 rw Functional watchdog heartbeat synchronization response

Write the last functional watchdog response byte to this field to
synchronize/restart the heartbeat.
Reset: 00H

Failure status flags *R1)

SYSFAIL
Failure status flags *R1) 1AH 00H

7 6 5 4 3 2 1 0
VOLTSEL
INITF ABISTERR nu VMONF OTF ERR
rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

INITF 7 rw1c INIT failure flag

INIT failure due to the third INIT failure in row. i.e. The device restarts
INIT phase from FAILSAFE.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H

Data Sheet 182 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

ABISTERR 6 rw1c ABIST operation interrupted flag
ABIST interrupted by any fault/event which is not part of ABIST.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H
nu 5:3 none
Reset: 0H
VMONF 2 rw1c Voltage monitor failure flag
Voltage monitor failure occured which lead to FAILSAFE.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags, read MONSF0, MONSF1 and
MONSF3 for details
Reset: 0H
OTF 1 rw1c Over temperature failure flag
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags, read OTFAIL for details
Reset: 0H

VOLTSELER 0 rw1c Double Bit error on voltage selection flag

R Device entered FAILSAFE state due to internal voltage selection failure.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H
Init error status flags *R2)

INITERR
Init error status flags *R2) 1BH 00H

7 6 5 4 3 2 1 0

HARDRES SOFTRES ERRF FWDF WWDF VMONF nu

rw1c rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

Data Sheet 183 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

HARDRES 7 rw1c Hard reset flag
Hard reset has been generated due to the second INIT failure in row. i.e.
The device restarts INIT phase for the 3rd time.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H
SOFTRES 6 rw1c Soft reset flag
Soft reset has been generated due to the first INIT failure. i.e. The device
restarts INIT phase for the 2nd time.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H
ERRF 5 rw1c MCU error monitor failure flag
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H
FWDF 4 rw1c Functional watchdog error counter overflow failure flag
Functional watchdog error counter reached the error threshold.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H
WWDF 3 rw1c Window watchdog error counter overflow failure flag
Window watchdog error counter reached the error threshold.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags
Reset: 0H
VMONF 2 rw1c Voltage monitor failure flag
Voltage monitor failure occured which lead to INIT.
0D No fault, write 0 - no action
1D Fault occurred, write 1 to clear the flags, read MONSF2 for
details Reset: 0H

nu 1:0 rw1c
Reset: 0H
Interrupt flags *R2)

IF
C 00
Interrupt flags *R2) 1 H H

7 6 5 4 3 2 1 0

Data Sheet 184 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

INTMISS ABIST OTF OTW MON SPI WK SYS

r rw1c rw1c rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

INTMISS 7 r Interrupt not serviced in time flag

Interrupt has not been serviced within tINT,TO time
0D No interrupt timeout happened
1D Interrupt timeout happened, cleared by hardware when all other
flags in IF are cleared.
Reset: 0H
ABIST 6 rw1c Requested ABIST operation performed flag
0D No interrupt, write 0 - no action
1D Interrupt flag active, write 1 to clear the flag
Reset: 0H
OTF 5 rw1c Over temperature failure interrupt flag
0D No interrupt, write 0 - no action
1D Interrupt flag active, write 1 to clear the flag, read OTFAIL for details
Reset: 0H
OTW 4 rw1c Over temperature warning interrupt flag
0D No interrupt, write 0 - no action
1D Interrupt flag active, write 1 to clear the flag, read OTWRNSF for
details
Reset: 0H
MON 3 rw1c Monitor interrupt flag
0D No interrupt, write 0 - no action
1D Interrupt flag active, write 1 to clear the flag, read MONSF0,
MONSF1, MONSF2 and MONSF3 for details
Reset: 0H
SPI 2 rw1c SPI interrupt flag
0D No interrupt, write 0 - no action
1D Interrupt flag active, write 1 to clear the flag, read SPISF for
details Reset: 0H
WK 1 rw1c Wake interrupt flag
Only set if device generates an interrupt when leaving SLEEP state.
0D No interrupt, write 0 - no action
1D Interrupt flag active, write 1 to clear the flag, read WKSF for details
Reset: 0H

Data Sheet 185 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Field Bits Type Description

SYS 0 rw1c System interrupt flag

0D No interrupt, write 0 - no action
1D Interrupt flag active, write 1 to clear the flag, read SYSSF for details
Reset: 0H
System status flags *R2)

SYSSF Offset Reset Value

System status flags *R2) 1DH 00H
7 6 5 4 3 2 1 0

nu NO_OP TRFAIL ERRMISS FWDE WWDE CFGE

rw1c rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

nu 7:6 none
Reset: 0H
NO_OP 5 rw1c State transition request failure flag
Requested state transition via DEVCTRL & DEVCTRLN could not be
performed because of wrong protocol.
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
TRFAIL 4 rw1c Transition to low power failed flag
Transition to low power failed either due to the QUC current
monitor, WAK high level or a rising edge on ENA during TRDEL
time. 0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
ERRMISS 3 rw1c MCU error miss status flag
Set only when SYSPCFG1.ERRRECEN='1'
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
FWDE 2 rw1c Functional watchdog error interrupt flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Field Bits Type Description
WWDE 1 rw1c Window watchdog error interrupt flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Data Sheet 186 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

CFGE 0 rw1c Protected configuration double bit error flag

Double bit error occurred on protected configuration register.
Status registers shall be read in order to determine which configuration
has changed.
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Wakeup status flags *R2)

WKSF Offset Reset Value

Wakeup status flags *R2) 1EH 00H

nu WKSPI WKTIM CMON ENA WAK

7 6 5 4 3 2 1 0

rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

ENA 1 rw1c ENA signal wakeup flag

Bit will also be set if FAILSAFE or STANDBY state left because of ENA.
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Field Bits Type Description

nu 7:5 none
Reset: 0H
WKSPI 4 rw1c Wakeup from SLEEP by SPI flag (GoToWAKE)
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
WKTIM 3 rw1c Wake timer wakeup flag
Bit will also be set if STANDBY state left because of wake timer
expired. 0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
CMON 2 rw1c QUC current monitor threshold wakeup flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Data Sheet 187 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

WAK 0 rw1c WAK signal wakeup flag

Bit will also be set if FAILSAFE or STANDBY state left because of
WAK. 0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Field Bits Type Description

nu 7:5 none
Reset: 0H
LOCK 4 rw1c LOCK or UNLOCK procedure error flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
DURE 3 rw1c SPI frame duration error flag
SCS low for more than 2 ms.
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
ADDRE 2 rw1c SPI address invalid flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Data Sheet 188 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

LENE 1 rw1c SPI frame length invalid flag

Number of detected SPI clock cycles different than 16.
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Field Bits Type Description

PARE 0 rw1c SPI frame parity error flag

0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
SPI status flags *R2)

SPISF Offset Reset Value

SPI status flags *R2) 1FH 00H
7 6 5 4 3 2 1 0

nu LOCK ADDRE LENE PARE

DURE
rw1c rw1c rw1c rw1c rw1c

Data Sheet 189 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

Monitor status flags 0 *R1)

MONSF0
Monitor status flags 0 *R1) 20H 00H

7 6 5 4 3 2 1 0

TRK2SG TRK1SG VREFSG COMSG VCORESG STBYSG UCSG PREGSG

rw1c rw1c rw1c rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

TRK2SG 7 rw1c Tracker2 short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
TRK1SG 6 rw1c Tracker1 short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
VREFSG 5 rw1c Voltage reference short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
COMSG 4 rw1c Communication LDO short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
VCORESG 3 rw1c Core voltage short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
STBYSG 2 rw1c Standby LDO short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
UCSG 1 rw1c uC LDO short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Data Sheet 190 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

PREGSG 0 rw1c Pre-regulator voltage short to ground status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Monitor status flags 1 *R1)

MONSF1
Monitor status flags 1 *R1) 21H 00H

7 6 5 4 3 2 1 0

TRK2OV TRK1OV VREFOV COMOV VCOREOV STBYOV UCOV PREGOV

rw1c rw1c rw1c rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

TRK2OV 7 rw1c Tracker2 over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
TRK1OV 6 rw1c Tracker1 over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
VREFOV 5 rw1c Voltage reference over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
COMOV 4 rw1c Communication LDO over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
VCOREOV 3 rw1c Core voltage over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
STBYOV 2 rw1c Standby LDO over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Data Sheet 191 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

UCOV 1 rw1c uC LDO over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
PREGOV 0 rw1c Pre-regulator voltage over voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Monitor status flags 2 *R2)

MONSF2
Monitor status flags 2 *R2) 22H 00H

7 6 5 4 3 2 1 0

TRK2UV TRK1UV VREFUV COMUV VCOREUV STBYUV UCUV PREGUV

rw1c rw1c rw1c rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

TRK2UV 7 rw1c Tracker2 under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
TRK1UV 6 rw1c Tracker1 under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
VREFUV 5 rw1c Voltage reference under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
COMUV 4 rw1c Communication LDO under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
VCOREUV 3 rw1c Core voltage under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Data Sheet 192 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

STBYUV 2 rw1c Standby LDO under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
UCUV 1 rw1c uC LDO under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
PREGUV 0 rw1c Pre-regulator voltage under voltage status flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Monitor status flags 3 *R1)

MONSF3
Monitor status flags 3 *R1) 23H 00H

7 6 5 4 3 2 1 0

BIASHI BIASLOW BG12OV BG12UV nu VBATOV

rw1c rw1c rw1c rw1c

Field Bits Type Description

BIASHI 7 rw1c Bias current too high flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
BIASLOW 6 rw1c Bias current too low flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
BG12OV 5 rw1c Bandgap comparator over voltage condition flag
(VBG1 ≥ VBG2 + 4%)
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
BG12UV 4 rw1c Bandgap comparator under voltage condition flag
(VBG1 ≤ VBG2 - 4%)
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H

Data Sheet 193 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

nu 3:1 none
Reset: 0H
VBATOV 0 rw1c Supply voltage VSx over voltage flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Over temperature failure status flags *R1)

OTFAIL
Over temperature failure status flags *R1) 24H 00H

7 6 5 4 3 2 1 0

MON nu COM nu UC PREG

rw1c rw1c rw1c rw1c

Field Bits Type Description

MON 7 rw1c Monitoring over temperature flag

0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
nu 6:5 none
Reset: 0H
COM 4 rw1c Communication LDO over temperature flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
nu 3:2 none
Reset: 0H
UC 1 rw1c uC LDO over temperature flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
PREG 0 rw1c Pre-regulator over temperature flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Over temperature warning status flags *R2)

Data Sheet 194 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

OTWRNSF
Over temperature warning status flags *R2) 25H 00H

7 6 5 4 3 2 1 0

nu VREF COM nu STDBY UC PREG

rw1c rw1c rw1c rw1c rw1c

Field Bits Type Description

nu 7:6 none
Reset: 0H
VREF 5 rw1c Voltage reference over load flag
(over current for more than 1ms)
0D Write 0 no action
1D Event detected, write 1 to clear the flag
Reset: 0H
COM 4 rw1c Communication LDO over temperature warning flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
nu 3 none
Reset: 0H
STDBY 2 rw1c Standby LDO over load flag
(over current for more than 1ms)
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
UC 1 rw1c uC LDO over temperature warning flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
PREG 0 rw1c Pre-regulator over temperature warning flag
0D Write 0 - no action
1D Event detected, write 1 to clear the flag
Reset: 0H
Voltage monitor status *R2)

VMONSTAT

Data Sheet 195 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

Voltage monitor status *R2) 26H 00H

7 6 5 4 3 2 1 0

TRK2ST TRK1ST VREFST COMST VCOREST STBYST nu

r r r r r r

Field Bits Type Description

TRK2ST 7 r Tracker2 voltage ready status
0D Voltage is out of range or not enabled
1D Voltage is OK
Reset: 0H
TRK1ST 6 r Tracker1 voltage ready status
0D Voltage is out of range or not enabled
1D Voltage is OK
Reset: 0H
VREFST 5 r Voltage reference voltage ready status
0D Voltage is out of range or not enabled
1D Voltage is OK
Reset: 0H
COMST 4 r Communication LDO voltage ready status
0D Voltage is out of range or not enabled
1D Voltage is OK
Reset: 0H
VCOREST 3 r Core voltage ready status
0D Voltage is out of range or not enabled
1D Voltage is OK
Reset: 0H
STBYST 2 r Standby LDO voltage ready status
0D Voltage is out of range or not enabled
1D Voltage is OK
Reset: 0H
nu 1:0 none
Reset: 0H
Device status *R2)

DEVSTAT
27 00
Device status *R2) H H

Data Sheet 196 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

7 6 5 4 3 2 1 0

TRK2EN TRK1EN COMEN STBYEN VREFEN STATE

r r r r r r

Field Bits Type Description

TRK2EN 7 r Tracker2 voltage enable status
0D Voltage is disabled
1D Voltage is enabled
Reset: 0H
TRK1EN 6 r Tracker1 voltage enable status
0D Voltage is disabled
1D Voltage is enabled
Reset: 0H
COMEN 5 r Communication LDO enable status
0D Voltage is disabled
1D Voltage is enabled
Reset: 0H
STBYEN 4 r Standby LDO enable status
0D Voltage is disabled
1D Voltage is enabled
Reset: 0H
VREFEN 3 r Reference voltage enable status
0D Voltage is disabled
1D Voltage is enabled
Reset: 0H
STATE 2:0 r Device state
7D RESERVED
6D RESERVED

5D WAKE

4D STANDBY

3D SLEEP

2D NORMAL

1D INIT

0D NONE
Reset: 0H
Protection status *R1)

PROTSTAT
Protection status *R1) 28H 01H

Data Sheet 197 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

7 6 5 4 3 2 1 0

KEY4OK KEY3OK KEY2OK KEY1OK nu LOCK

r r r r r

Field Bits Type Description

KEY4OK 7 r Key4 ok status

Information about validity of the 4th received protection key byte
0D Key not valid
1D Key valid
Reset: 0H
KEY3OK 6 r Key3 ok status
Information about validity of the 3rd received protection key byte
0D Key not valid
1D Key valid
Reset: 0H
KEY2OK 5 r Key2 ok status
Information about validity of the 2nd received protection key byte
0D Key not valid
1D Key valid
Reset: 0H
KEY1OK 4 r Key1 ok status
Information about validity of the 1st received protection key byte
0D Key not valid
1D Key valid
Reset: 0H
nu 3:1 none
Reset: 0H
LOCK 0 r Protected register lock status
0D Access is unlocked
1D Access is locked
Reset: 1H
Window watchdog status *R3)

WWDSTAT
Window watchdog status *R3) 29H 00H

7 6 5 4 3 2 1 0

Data Sheet 198 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

nu WWDECNT

Field Bits Type Description

nu 7:4 none
Reset: 0H
WWDECNT 3:0 r Window watchdog error counter status
Reset: 0H
Functional watchdog status 0 *R3)

FWDSTAT0 Offset Reset Value

Functional watchdog status 0 *R3) 2AH 30H

7 6 5 4 3 2 1 0
FWDRSPO
nu K FWDRSPC FWDQUEST

r r r

Functional watchdog status 1 *R3)

FWDSTAT1
Functional watchdog status 1 *R3) 2BH 00H

Field Bits Type Description

nu 7 none
Reset: 0H
FWDRSPOK 6 r Functional watchdog response check error status
0D Response message is wrong
1D All received bytes in response message are correct
Reset: 0H
FWDRSPC 5:4 r Functional watchdog response counter value
Reset: 3H

FWDQUEST 3:0 r Functional watchdog question

Reset: 0H
7 6 5 4 3 2 1 0

Data Sheet 199 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

nu FWDECNT

Field Bits Type Description

nu 7:4 none
Reset: 0H
FWDECNT 3:0 r Functional watchdog error counter value
Reset: 0H

ABIST control 0 *R2)

ABIST_CTRL0
C 00
ABIST control0 *R2) 2 H H

7 6 5 4 3 2 1 0

STATUS INT SINGLE PATH START

r rw rw rw rwhc

Field Bits Type Description

STATUS 7:4 r ABIST global error status

ABIST status information after requested operation has been performed,
information shall only be considered valid, once START bit is cleared.
Bits have different reset class than whole register. The Bits are reset
according to *R1).
5D Selected ABIST operation performed with no errors
10D Selected ABIST operation performed with errors, check respective
SELECT registers

Reset: 0H
INT 3 rw Safety path selection
Select whether safe state or interrupt related comparator shall be tested.
0D safe state related comparators shall be tested
1D interrupt related comparators shall be tested
Reset: 0H

Data Sheet 200 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

SINGLE 2 rw ABIST Sequence selection
Select whether a single comparator shall be tested or all comparators in
predefined sequence
0D Predefined sequence
1D Single comparator test
Reset: 0H
PATH 1 rw Full path test selection
Select the path which should be covered by ABIST operation
0D Comparator only
1D Comparator and corresponding deglitching logic, shall be selected in
case contribution to respective safety measure needs to be tested
Reset: 0H

START 0 rwhc Start ABIST operation

The ABIST operation itself will be started. This bit is cleared after ABIST
operation has been performed
0D Operation done
1D Start operation
Reset: 0H
ABIST control 1 *R2)

ABIST_CTRL1
D 00
ABIST control1 *R2) 2 H H

7 6 5 4 3 2 1 0
ABIST_C
nu LK_EN OV_TRIG

rw rw

Field Bits Type Description

nu 7:2 none
Reset: 00H
ABIST_CLK_ 1 rw ABIST clock check enable
EN Select ABIST clock to check its functionality
0D Disable
1D Enable
Reset: 0H

Data Sheet 201 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

OV_TRIG 0 rw Overvoltage trigger for secondary internal monitor enable
0D Disable
1D Enable
Reset: 0H
ABIST select 0 *R2)

ABIST_SELECT0
E 00
ABIST select 0 *R2) 2 H H

7 6 5 4 3 2 1 0

TRK2OV TRK1OV VREFOV COMOV VCOREOV STBYOV UCOV PREGOV

rwhu rwhu rwhu rwhu rwhu rwhu rwhu rwhu

Field Bits Type Description

TRK2OV 7 rwhu Select TRK2 OV comparator for ABIST operation

0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
TRK1OV 6 rwhu Select TRK1 OV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
VREFOV 5 rwhu Select VREF OV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
COMOV 4 rwhu Select COM OV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H

Data Sheet 202 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Offset Reset Value

VCOREOV 3 rwhu Select Core voltage OV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
STBYOV 2 rwhu Select Standby LDO OV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
UCOV 1 rwhu Select uC LDO OV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H

Data Sheet 203 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Field Bits Type Description

PREGOV 0 rwhu Select Pre-regulator OV comparator for ABIST operation

0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
ABIST select 1 *R2)

ABIST_SELECT1 Offset Reset Value

ABIST select 1 *R2) 2FH 00H
7 6 5 4 3 2 1 0

TRK2UV TRK1UV VREFUV COMUV VCOREUV STBYUV UCUV PREGUV

rwhu rwhu rwhu rwhu rwhu rwhu rwhu rwhu

Field Bits Type Description

TRK2UV 7 rwhu Select TRK2 UV comparator for ABIST operation

0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
TRK1UV 6 rwhu Select TRK1 UV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this voltage
Reset: 0H
VREFUV 5 rwhu Select VREF UV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
COMUV 4 rwhu Select COM UV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H

Data Sheet 204 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

VCOREUV 3 rwhu Select VCORE UV comparator for ABIST operation

0D Not selected
1D selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
Field Bits Type Description

STBYUV 2 rwhu Select STBY UV comparator for ABIST operation

0D Not selected
1D selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
UCUV 1 rwhu Select uC UV comparator for ABIST operation
0D Not selected
1D selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
PREGUV 0 rwhu Select pre regulator UV comparator for ABIST operation
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
ABIST select 2 *R2)

ABIST_SELECT2 Offset Reset Value

ABIST select 2 *R2) 30H 00H

7 6 5 4 3 2 1 0

BIASHI BIASLOW BG12OV BG12UV INTOV nu VBATOV

rwhu rwhu rwhu rwhu rwhu rwhu

Field Bits Type Description

BIASHI 7 rwhu Select bias current too high

0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H

Data Sheet 205 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

BIASLOW 6 rwhu Select bias current too low

0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
BG12OV 5 rwhu Select bandgap comparator OV condition
(VBG1 ≥ VBG2 + 4%)
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
Field Bits Type Description

BG12UV 4 rwhu Select bandgap comparator UV condition

(VBG1 ≤ VBG2 - 4%)
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
INTOV 3 rwhu Select internal supply OV condition
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
nu 2:1 none
Reset: 0H
VBATOV 0 rwhu Select supply VSx overvoltage
0D Not selected
1D Selected, bit will be cleared upon successful ABIST operation on
comparator, bit will be set in case of ABIST fail for this
comparator
Reset: 0H
Global testmode *R2)

GTM Offset Reset Value

Global testmode *R2) 3FH 02H

7 6 5 4 3 2 1 0

nu NTM TM

r r

Data Sheet 206 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Field Bits Type Description

nu 7:2 none
Reset: 00H
NTM 1 r Test mode inverted status
0D Device is in test mode
1D Device is in normal mode
Reset: 1H
TM 0 r Test mode status
0D Device is in normal mode
1D Device is in test mode
Reset: 0H
13.4.2 Buck registers

Buck switching frequency change *R2)

BCK_FREQ_CHANGE Offset Reset Value

Buck switching frequency change *R2) 31H 00H
7 6 5 4 3 2 1 0

nu BCK_FREQ_SEL

rw

Field Bits Type Description

nu 7:3 none
Reset: 00H
BCK_FREQ_ 2:0 rw BUCK switching frequency change
SEL For hi and low switching mode. New value needs to be validated via
data_valid procedure
7D Change buck frequency by approx. -4.5% from fOSC,step-down
6D Change buck frequency by approx. -3.0% from fOSC,step-down

5D Change buck frequency by approx. -1.5% from fOSC,step-down

4D No change

3D Change buck frequency by approx. +4.5% from fOSC,step-down

2D Change buck frequency by approx. +3.0% from fOSC,step-down

1D Change buck frequency by approx. +1.5% from fOSC,step-down

0D No Change
Reset: 0H
Buck Frequency spread *R2)

Data Sheet 207 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

BCK_FRE_SPREAD Offset Reset Value

Buck Frequency spread *R2) 32H 00H
7 6 5 4 3 2 1 0

FRE_SP_THR

rw

Field Bits Type Description

FRE_SP_THR 7:0 rw Spread spectrum
Select the percentage of frequency spread(+/-). The mean frequency is
reduced by the percentage as well keeping the maximum frequency at
the nominal frequency selected by FRE.
00H No spread
2BH 1%

55H 2%

80H 3%

AAH
4%
D5H 5%

FFH 6%
Reset: 00H
Buck main control *R2)

BCK_MAIN_CTRL Offset Reset Value

Buck main control *R2) 33H 00H
7 6 5 4 3 2 1 0
DATA_VA
BUSY LID nu

r rw

Field Bits Type Description

BUSY 7 r DATA_VALID parameter update ready status

0D update done
1D update ongoing
Reset: 0H

Field Bits Type Description

Data Sheet 208 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

DATA_VALID 6 rw Enable buck update

Update Command to load new parameter for stepdown regulator (after
configuration write 1 to update and write 0 after BUSY flag is cleared to
proceed operation)
0D No action
1D Load new parameters
Reset: 0H
nu 5:0 none
Reset: 00H

13.5 Electrical Characteristics

Table 23 Electrical Characteristics: SPI signals

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

Data input valid high level VSDI, hi 3.6 – – V VSDI increasing, P_13.5.17
VQUC = 5.0 V
Data input valid low level VSDI, lo – – 0.8 V VSDI decreasing, P_13.5.18
VQUC = 5.0 V
Data input hysteresis VSDI, hyst – 350 – mV VQUC = 5.0 V P_13.5.19

Data Sheet 209 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Data input valid high level VSDI, hi 2.0 – – V VSDI increasing, P_13.5.20
VQUC = 3.3 V
Pin SCS, Chip Select
Chip select valid high level VSCS, hi 3.6 – – V VSCS increasing, P_13.5.1
VQUC = 5.0 V
Chip select valid low level VSCS, lo – – 0.8 V VSCS decreasing, P_13.5.2
VQUC = 5.0 V
Chip select hysteresis VSCS, hyst – 350 – mV VQUC = 5.0 V P_13.5.3
Chip select valid high level VSCS, hi 2.0 – – V VSCS increasing, P_13.5.4
VQUC = 3.3 V
Chip select valid low level VSCS, lo – – 0.8 V VSCS decreasing, P_13.5.5
VQUC = 3.3 V
Chip select hysteresis VSCS, hyst – 160 – mV VQUC = 3.3 V P_13.5.6
Chip select pull-up current ISCS -175 -120 – µA VSCS = 0 V P_13.5.7
Chip select input capacitance – 15 pF 1) P_13.5.8
CSCS 4
Pin SCL, Clock
Clock signal valid high level VSCL, hi 3.6 – – V VSCL increasing, P_13.5.9
VQUC = 5.0 V
Clock signal valid low level VSCL, lo – – 0.8 V VSCL decreasing, P_13.5.10
VQUC = 5.0 V
Clock hysteresis VSCL, hyst – 350 – mV VQUC = 5.0 V P_13.5.11

Clock signal valid high level VSCL, hi 2.0 – – V VSCL increasing, P_13.5.12
VQUC = 3.3 V
Clock signal valid low level VSCL, lo – – 0.8 V VSCL decreasing, P_13.5.13
VQUC = 3.3 V
Clock hysteresis VSCL, hyst – 160 – mV VQUC = 3.3 V P_13.5.14

Clock signal pull-down ISCL – 150 330 µA VSCL = VQUC P_13.5.15

current

Clock input capacitance CSCL – 4 15 pF 1) P_13.5.16

Pin SDI, Data Input, MOSI
Table 23 Electrical Characteristics: SPI signals (cont’d)
VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.

Data input valid low level VSDI, lo – – 0.8 V VSDI decreasing, P_13.5.21
VQUC = 3.3 V
Data input hysteresis VSDI, hyst – 160 – mV VQUC = 3.3 V P_13.5.22

Data Sheet 210 Rev. 2.0, 2017-03-16

 TLF35584

SPI - Serial Peripheral Interface

Data input signal pull-down ISDI – 150 330 µA VSDI = VQUC P_13.5.23
current

Data input capacitance CSDI – 4 15 pF 1) P_13.5.24

Pin SDO, Data Output, MISO
Data output high level VSDO, hi 4.0 – – V VQUC = 5.0 V, P_13.5.25
TLF35584xxVS1 ISDO = -9 mA
Data output low level VSDO, lo – – 0.7 V VQUC = 5.0 V P_13.5.26
TLF35584xxVS1 ISDO = 7 mA
Data output high level VSDO, hi 2.3 – – V VQUC = 3.3 V P_13.5.27
TLF35584xxVS2 ISDO = -7 mA
Data output low level VSDO, lo – – 0.7 V VQUC = 3.3 V P_13.5.28
TLF35584xxVS2 ISDO = 5.5 mA
Data output rise time 1) – 25 ns CSDO,load = 50 pF P_13.5.29
tSDO, rise –
Data output fall time 1) tSDO, fall – – 25 ns CSDO,load = 50 pF P_13.5.30
Data output tristate CSDO, tri – 4 15 pF 1) P_13.5.31
capacitance
Data output tristate leakage ISDO, tr, leaki -10 – 10 µA – P_13.5.32
1) Specified by design, not subject to production test

Data Sheet 211 Rev. 2.0, 2017-03-16

 TLF35584

Interrupt Generation

14 Interrupt Generation

A dedicated interrupt generation block is implemented which is handling requests from independent sources to
generate an interrupt. The different requesters are as follows:
• State machine in case:
– A requested state transition has not been performed successfully, e.g. SLEEP state could not be entered
because of LDO_µC current consumption above the selected threshold level.
– A requested state transition from SLEEP has been performed successfully, i.e. the system has either
successfully entered WAKE state. The uC may only send (additional) SPI commands after an interrupt
event has been generated by the system. The purpose of the interrupt event is to inform the uC that a state
transition has been performed successfully and that the system is capable of performing SPI
communication at full SPI speed.
• Watchdog, an interrupt request is generated if the Watchdog is not serviced properly and configured in a way
to allow service errors to occur, i.e. an error counter threshold value of more than 2 is configured. In this case
an interrupt is generated only if the error counter threshold is not exceeded due to this error.
• Error pin monitoring, an interrupt request is generated if the error pin monitoring block detects an error and is
configured in a way to allow occurrence of this error for a certain amount of time (recovery delay action
enabled). In this case an interrupt is requested if an error is detected by the error pin monitoring and the
recovery delay has not expired.
• Monitoring Block, an interrupt request is generated based on the defined system reaction described in Chapter
11.4.
• Overtemperature warnings and over temperature shutdown of communication LDO
• Overcurrent conditions of voltage reference or standby LDO
• SPI block in case an SPI error has occurred
• ABIST operation has been completed
• Double bit error in the protected configuration

An interrupt is generated to inform a connected uC that a non-severe system condition has occurred. This allows
the uC to perform proper action based on the source of the interrupt. A single interrupt line exists, which is high
on default. All Internal interrupt sources are enabled by default and cannot be disabled.
An interrupt is signaled by pulling the interrupt line low for at least tINT (interrupt min. pulse width) after an internal
interrupt condition occurs. The interrupt line will be driven high if all of the IF register flag(s) has/have been cleared
via SPI operation earliest after tINT has expired but latest after tINTTO has expired.
Special cases:
• If an interrupt is signaled by pulling INT low and not all interrupt status flags are cleared by the uC within tINTTO,
the INT will stay low until tINTTO has expired, but no additional interrupt will be generated. Information about a
pending interrupt event can be derived via the INTMISS status flag. This status flag is cleared each time the
interrupt line is driven low.
• If an interrupt is signaled by pulling INT low and an additional bit is set in the IF register interrupt flag after the
interrupt bits have been read by the uC and this outdated information is used to clear the interrupt flags, the
interrupt line will stay low until tINTTO has expired, but no additional interrupt will be generated. Information
about a pending interrupt event can be derived via a status flag.

Data Sheet 212 Rev. 2.0, 2017-03-16

 TLF35584

Interrupt Generation

• After releasing the interrupt line to high, the interrupt line will stay high for at least tINTTO regardless if any
additional internal interrupt condition has occurred or not. If a new interrupt event occurs during the delay time
out (tINTTO), this will be signaled by generating a new pulse after the delay time out tINTTO.
All interrupt sources can only be cleared by a “write-1-to-clear” (w1c) SPI operation, i.e. writing a logic one to the
corresponding bit(s) in the interrupt register will clear the event.
Interrupt events are organized in a two level approach. The first level (interrupt flag) provides information about
different groups of interrupt events. The second level (status flags) provides detailed information about which
particular event(s) generated the interrupt. To service an interrupt one would only need to write the interrupt flag
register (IF). The status flag registers are only meant to provide detailed information. However all status flags can
be cleared as well.

Recommended interrupt service routine:

After an interrupt has been detected by an uC, the recommended interrupt service routine would need to perform
the following tasks via SPI:
1. Read interrupt flag register (IF)
2. Read status flag register(s) based on information from first read
3. Take the proper action based on interrupt flag(s) and status flag(s)
4. Write back the status flag register(s) to clear particular status flag(s)
5. Write back the interrupt flag register (IF) with the previously read value to clear
6. Recommended: Read interrupt flag register (IF) again to check for occurrence of another interrupt event. In
case step back to 2).
7. Writing back the interrupt register (IF) will release the interrupt line INT if all bits are cleared (interrupt timing
requirements will be fulfilled).
An interrupt is only generated after the reset signal to the uC has been released. An interrupt event which occurred
while the reset line for the uC is still active is not signaled at the interrupt line but the particular status bit for this
event is set.
Details about the timing of the interrupt line are depicted in the following figure:

Internal Interrupt Requests

t INT t INTTO t INTTO t INTTO

t INTTO

Interrupt Line

SPI Service Done SPI Service Done SPI Service Done

INT not serviced flag

(previously set)

INT not serviced flag

(previously cleared)

Figure 76 Interrupt timing

Table 24 Electrical Characteristics: Interrupt - Timings
VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)

Data Sheet 213 Rev. 2.0, 2017-03-16

 TLF35584

Interrupt Generation

Parameter Symbol Values Unit Note / Number

Test Condition
Min. Typ. Max.

Minimum interrupt pulse tINT,min 90 100 150 µs P_14.1

width

Interrupt time out 270 300 350 µs P_14.2

tINTTO
Details about the system behavior in case not all interrupt status flags have been cleared are depicted in the
following figure:

Internal Interrupt Requests

t INTTO t INTTO t INTTO

Interrupt Line

SPI Service Done

INT not serviced flag

(previously set)
INT not serviced flag
(previously cleared)

Figure 77 Interrupt timing without service in time

An interrupt is always generated if an internal status flag is set, irrespective of the current state of this status flag.
For example, if a parity error on SPI communication is detected for the first time, the flag SPISF.PARE is set and
an interrupt is generated. This flag will also set the corresponding SPI interrupt flag (IF.SPI). If the flag IF.SPI is
not cleared, but a second SPI parity error occurs, a new interrupt will be generated regardless. The timings shown
in the two figures above will be fulfilled for generating a new interrupt.

Data Sheet 214 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15 Window Watchdog And Functional Watchdog

15.1 Introduction
Two independent types of watchdogs are implemented in the TLF35584:
• A standalone window watchdog (WWD) with programmable input trigger signal (either pin WDI or trigger via
SPI command to WWDSCMD register)
• A standalone functional or question/answer watchdog (FWD).
The watchdogs have independent timers and error counters, which allows to run both watchdogs in parallel.

WWO

WDI Valid WWD triggering

Window Watchdog
Window Watchdog
Failure Counter
(WWD)
SPI Invalid WWD triggering
WWO
Safe State
Control
Valid FWD triggering
Functional Watchdog
SPI Functional Watchdog
(FWD)
Invalid FWD triggering Failure Counter

FWO FWO

Figure 78 Window watchdog and functional watchdog

Description:
• The functional watchdog is not synchronized to the window watchdog, both are fully independent.
• The functional watchdog and the window watchdog can be activated and deactivated independently.
• The result of the watchdogs (valid or invalid triggering) are monitored independently by the related watchdog
failure counters.
• The status of the window watchdog is WWO, it may have the values “Valid WWD triggering” or “Invalid WWD
triggering”
• The status of the functional watchdog is FWO, it may have the values “Valid FWD triggering” or “Invalid FWD
triggering
• The influence of the settings of both watchdogs on safe state control is described in chapter safe state control
for better understanding
15.2 Window Watchdog

Principle of Operation
The window watchdog is integrated in the TLF35584 to monitor the microcontroller. The microcontroller that is
being monitored has to provide periodical triggering within the "Open Windows". A triggering can consist of a
falling edge on the WDI pin or writing to the register WWDSCMD by an SPI command depending on the
configuration. This triggering terminates the “Open Window”. The watchdog output indicates a “Valid” or “Invalid”
WWD triggering to the WWD failure counter. In case of a “Valid” triggering a “Closed Window” is started.In case

Data Sheet 215 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

there is no triggering during the “Open Window” or a triggering during a "Closed Window", the watchdog output
indicates an “Invalid WWD triggering” to the WWD failure counter and a new “Open Window” is started.
In case the microcontroller is not able to trigger the window watchdog with a correct timing, it is assumed that the
microcontroller doesn’t work as expected. The microcontroller will get informed by the TLF35584 and a reset in
case of multiple failure events.

Configuration
The following parameters of the window watchdog can be configured in INIT, NORMAL and WAKE state:
• The triggering can be set either to pin triggering (pin WDI) or triggering via SPI command (register
WWDSCMD). The default configuration is the triggering via SPI.
• The length of open and closed window can be modified according to the application needs by SPI.
(combination of cycle time WDCYC and number of cycles for open OW and closed CW window)
• The threshold for the window watchdog failure counter overflow can defined by SPI

Initialization
The window watchdog will become active in INIT state as soon as reset output pin ROT turns from low to high.
After activation the watchdog opens a so called “Long Open Window” (LOW) of duration of tLOW. During the ”Long
Open Window” the window watchdog expects a valid triggering, which has to be provided via SPI in case the
default configuration is kept, since any signal to watchdog trigger pin WDI is ignored. This is to avoid wrong
triggering at pin WDI due to glitches at the micro controller outputs during startup and initialization.
The microcontroller can change the configuration of the window watchdog during the “Long Open Window” to
change the trigger selection as well as the times for the “Open” and “Closed Window”. With a reconfiguration the
window watchdog will be restarted with the new configuration. A “Open Window” will be started accordingly,
expecting a valid triggering by the selected triggering input.
If no valid triggering or configuration of the watchdog takes place during the “Long Open Window”, the window
watchdog recognizes an “invalid WWD triggering”. If the INIT timer expires with an invalid WWD triggering present,
a so-called “Soft Reset” will be issued. After the so-called “Soft-Reset” the window watchdog opens a new “Long
Open Window”. This is not indicated by interrupt. The repetition of “Long Open Windows” is limited. Should within
the second “Long Open Window” the window watchdog not be triggered correctly, a normal or “hard” reset will
occur, which means that pin ROT goes to zero and the post regulator output voltages will be switched off. After
the third “Long Open Window” without valid triggering in a row the state machine will bring the device into
“FAILSAFE state (for details please refer to chapter State machine).

Normal Operation
A trigger signal within the "Long Open Window" will terminate the "Long Open Window" and start the "Closed
Window". The "Closed Window" has a fixed duration for operation without invalid triggering.. During normal
operation no valid trigger signal is allowed during the "Closed Window”. If a valid trigger signal is received within
the “Closed Window”, the window watchdog recognizes “invalid WWD triggering”. The “Closed Window” will be
terminated with this invalid triggering and an “Open Window” will be started.
An “invalid WWD triggering” will increment the window watchdog failure counter by two. This is indicated by
interrupt.
After the “Closed Window” has ended, the window watchdog starts an “Open Window”.
Within the “Open Window” a valid trigger signal is expected. If a valid trigger signal is received within the "Open
Window" the watchdog terminates the "Open Window" and starts the "Closed Window". “Valid WWD triggering”

Data Sheet 216 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

will decrement the window watchdog failure counter by one in case it is greater than zero, this is not indicated by
interrupt.
If no valid triggering should be received during the “Open Window”, the window watchdog recognizes “Invalid
WWD triggering” and increments the window watchdog failure counter by two and a new “Open Window” is
started. This is indicated by interrupt.
In normal operation, the watchdog continues to cycle between the "Open Window" and "Closed Window" as long
as valid triggering is received.

Window watchdog output WWO

The window watchdog output WWO is an internal signal: It is connected to the safe window watchdog failure
counter. The value of WWO is either “Valid WWD triggering” or “Invalid WWD Triggering”.

No Trigger No Trigger

No Trigger

Trigger Valid WWD triggering

Trigger No Trigger
Long Open Closed Open
Window Window Window
(CW) (OW) Invalid WWD triggering
(LOW)
Trigger

Initialization Normal Operation Status of WWO

Figure79 Watchdog state diagram

Description:
• “Trigger” is either a SPI command to WWDSCMD register or a valid watchdog trigger at pin WDI
• “No Trigger” in the “Long open Window” is considered as “Invalid WWD triggering”, the watchdog opens again
a ”Long Open Window”
• “Trigger” within the “Long Open Window” is considered as “Valid WWD triggering”, the watchdog closes the
“Long Open Window” and opens the “Closed Window”
• “Trigger” within the “Closed Window” is considered as “Invalid WWD triggering”
• “No Trigger” within the “Closed Window” moves the watchdog to the “Open Window”, after the “Closed
Window” has ended.
• “Trigger” within the “Open Window” is considered as “Valid WWD triggering”, the watchdog closes the “Open
Window” and opens the “Closed Window”
• “No Trigger” in the “Open Window” is considered as “Invalid WWD triggering”,.

Window watchdog trigger pin WDI

Data Sheet 217 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

The watchdog input pin WDI has an integrated pull-down current IWDI. The watchdog input WDI can transition to
high within the "Closed Window" or during the following "Open Window".

Valid Trigger Signal at WDI

Watchdog input WDI is periodically sampled with a period of TSAM. A valid trigger signal is a falling edge from
VWDI,high to VWDI,low. To improve immunity against noise or glitches on the WDI input, at least two high samples
followed by two low samples are required for a valid trigger signal, the valid triggering is considered with the
second consecutive sampling point measuring low signal. For example, if the first three samples (two high one
low) of the trigger pulse at pin WDI are inside the “Closed Window” and only the fourth sample (the second low
sample) is taken in the “Open Window” then the watchdog output WWO will indicate “valid WWD triggering”.

Invalid Triggering at WDI

No trigger signal detected during the "Open Window" or a trigger signal detected during the "Closed Window", is
considered invalid triggering. Watchdog output WDO indicates “invalid triggering” immediately after no valid trigger
during the "Open Window" or immediately if a trigger signal is detected during the "Closed Window".

Figure 80 Valid and invalid trigger pulses at pin WDI

Data Sheet 218 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.2.1 Timing Diagrams

15.2.1.1 Normal operation: Correct triggering

Long Open Window Closed Window Open Window Closed Window

ROT

1
WWDSCMD

WDI
2 3 4 5

variable fixed variable fixed

immediately immediately

Valid WWD triggering

Invalid WWD triggering

Figure 81 Normal operation: Correct triggering

1. The “Long Open Window” starts in INIT state if the reset output of ROT (monitoring the microcontroller related
voltages) turned high. In case the window watchdog was deactivated in SLEEP, the first Open Window starts
with the transition from SLEEP state to WAKE state which is indicated by interrupt. The time of this first Open
Window depends on the configured cycle time and is 600 ms (WDCYC = 1) or 60 ms (WDCYC = 0)
2. During the “Long Open Window” valid triggering of the WWD according to the configured trigger selection is
expected. The maximum time of the “Long Open Window” is fixed, but it will be terminated as soon as a “Valid
WWD triggering” is recognized.
3. The window watchdog will enter now the ”Closed Window”. After receiving this first valid trigger the device will
be allowed to move from INIT to NORMAL state or from WAKE to NORMAL state.
4. The “Closed Window” has a fixed duration tWD,CW (can be determined by SPI command). It starts right after
the valid trigger signal, that closes the “Open Window” or the “Long Open Window”. During the “Closed
Window” no trigger signal should be applied. A transition from low to high at the WDI pin is not detected and
will not lead to a trigger event,
5. A valid trigger signal terminates the “Open Window” immediately, thus the time of the “Open Window” is
variable and depending on the time the microcontrollers schedules the triggering. This is counted as a “Valid
WWD triggering”

Data Sheet 219 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.2.1.2 Fault operation: No trigger in open window after initialization

Long Open Window Long Open Window Closed Window

ROT

WWDSCMD FAULT!

WDI 1 2 3 4 5

variable fixed

immediately

Valid WWD triggering

Invalid WWD triggering

Figure 82 Fault operation: No trigger in Open Window after initialization

1. The initialization timeout and the long open window (LOW) do have the same typ. length. Usually this leads to
the initialization timeout finishing at the slightly before or at same time as the LOW, which would skip the
interrupt event (1). Even though due to the given accuracy, the missing valid triggering within the “Long Open
Window” might lead to an interrupt event after the LOW has ended which is increasing the window watchdog
failure counter by two.
2. The INIT state timer expires for the first time. As no valid triggering of the window watchdog was received
during INIT state as expected, a so-called “Soft-Reset” will be issued: Pin ROT goes to zero, but the output
voltages of the post regulators remain on.
Additional information: In case the window watchdog should not be triggered correctly within the next “Long
Open Window” of the following INIT phase, a “Hard-Reset” will be issued, which means pin ROT will go to
zero and the output voltages will also be switched off. After a third invalid triggering during INIT phase the
device will go into FAILSAFE state.
3. After the so-called “Soft-Reset” pin ROT turns high again after the power-on reset delay time trd and the
watchdog opens a “Long Open Window” to give the microcontroller the chance to trigger and synchronize to
the watchdog period.
4. A valid triggering terminates the “Long Open Window”, which makes the duration of the “Long Open Window”
variable and depending on the triggering. This is counted as a “Valid WWD triggering” and a “Closed Window”
is started. The window watchdog failure counter will be decremented by one without an interrupt issued.
5. The following “Closed Window” lasts for the time tWD,CW. Triggering within this time will be considered as an
”Invalid WWD triggering”.

Data Sheet 220 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.2.1.3 Fault operation: No trigger in Open Window in steady state

Open Window Open Window Closed Window Open Window

ROT

WWDSCMD FAULT!

WDI 1 2 3 4

variable fixed variable

immediately immediately

Valid WWD triggering

Invalid WWD triggering

Figure 83 Fault operation: No trigger in Open Window in steady state

1. A missing valid triggering within the “Open Window” leads after the window has ended to an “Invalid WWD
triggering”. This event is indicated by an interrupt, the window watchdog failure counter increases by two.
2. Having detected an “Invalid WWD triggering” the watchdog will start a new “Open Window” with duration
tWD,OW to give the microcontroller the chance to trigger and synchronize to the watchdog period.
3. A valid triggering terminates the “Open Window”, which makes the duration of the “Open Window” variable
and depending on the triggering. This is counted as a “Valid WWD triggering” and a “Closed Window” is
started.
The window watchdog failure counter will be decremented by one without an interrupt issued.
Additional informations: In case of multiple “Invalid WWD triggering” within the “Open Windows”, the window
watchdog failure counter would be incremented again by two until it reaches the configured threshold. In this
case a reset will be issued.
4. The following “Closed Window” lasts for the time tWD,CW. Triggering within this time will be considered as an
”Invalid WWD triggering”.
The behavior of pin ROT is depending on the value of Σ WWO. In the example above it was assumed, that the
invalid triggering will not lead to exceed the threshold Σ WWO.

Data Sheet 221 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.2.1.4 Fault operation: False trigger in Closed Window after initialization

Figure 84 Fault operation: False trigger in Closed Window after initialization

1. A triggering during the “Closed Window” is indicated as “Invalid WWD triggering”. This event is indicated by
an interrupt and the window watchdog failure counter increases by two.
2. The “Closed Window” will be closed with the “Invalid WWD triggering”. Originally it would last for the time
tWD,CW. The false triggering terminates the “Closed Window” and starts an “Open Window” to give the micro
processor the opportunity to synchronize to the window watchdog period.
3. Within this “Open Window” a valid triggering is expected. A valid triggering terminates the “Open Window”,
which makes the duration of the “Open Window” variable and depending on the triggering. This is counted
as a “Valid WWD triggering” and a “Closed Window” is started. The window watchdog failure counter will be
decremented by one without an interrupt issued.
4. The following “Closed Window” lasts for the time tWD,CW. Triggering within this time will be considered as an
”Invalid WWD triggering”.
The behavior of pin ROT is depending on the value of Σ WWO. In the example above it was assumed, that the
invalid triggering will not lead to exceed the threshold Σ WWO.

Data Sheet 222 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.2.1.5 Fault operation: False trigger in Closed Window in steady state

Figure 85 Fault operation: False trigger in Closed Window

1. A triggering during the “Closed Window” is indicated as “Invalid WWD triggering”. This event is indicated by
an interrupt and the window watchdog failure counter increases by two.
2. The “Closed Window” will be closed with the “Invalid WWD triggering”. Originally it would last for the time
tWD,CW. The false triggering terminates the “Closed Window” and starts an “Open Window” to give the micro
processor the opportunity to synchronize to the window watchdog period.
3. Within this “Open Window” a valid triggering is expected. A valid triggering terminates the “Open Window”,
which makes the duration of the “Open Window” variable and depending on the triggering. This is counted
as a “Valid WWD triggering” and a “Closed Window” is started. The window watchdog failure counter will be
decremented by one without an interrupt issued.
4. The following “Closed Window” lasts for the time tWD,CW. Triggering within this time will be considered as an
”Invalid WWD triggering”.
The behavior of pin ROT is depending on the value of Σ WWO. In the example above it was assumed, that the
invalid triggering will not lead to exceed the threshold Σ WWO.
15.2.2 Electrical characteristics

Table 25 Electrical Characteristics: Window watchdog function

Data Sheet 223 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

VVS =6.0 V to 40 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note / Number
Test Condition
Min. Typ. Max.
General timing parameters watchdog (WWD and FWD)
Watchdog cycle time tCYCLE 94 100 106.5 µs selectable by SPI P_15.2.2.1
command

Watchdog cycle time, default tCYCLE 940 1000 1065 µs selectable by SPI P_15.2.2.2
setting command

Long open window time tLOW 564 600 639 ms – P_15.2.2.3

Watchdog input WDI
Watchdog sampling time tSAM 188 200 213 µs – P_15.2.2.4
WDI valid high level VWDI, high 3.6 – – V VWDI increasing, P_15.2.2.5
VQUC = 5.0 V
WDI valid low level VWDI, low – – 0.8 V VWDI decreasing, P_15.2.2.6
VQUC = 5.0 V
WDI hysteresis – 350 – mV VQUC = 5.0 V P_15.2.2.7

VWDI, hyst
WDI valid high level VWDI, high 2.0 – – V VWDI increasing, P_15.2.2.8
VQUC = 3.3 V
WDI valid low level VWDI, low – – 0.8 V VWDI decreasing, P_15.2.2.9
VQUC = 3.3 V
WDI hysteresis VWDI, hyst – 160 – mV VQUC = 3.3 V P_15.2.2.10
WDI pull-down current IWDI – 150 330 µA VWDI = VQUC P_15.2.2.11
WDI input capacitance CWDI – 4 15 pF 1) P_15.2.2.12
1) Specified by design, not subject to production test
15.3 Functional Watchdog

Principle of Operation
A functional or question/answer watchdog is integrated in the TLF35584 to monitor the microcontroller. In a steady
state a question is generated (taken out of table), in parallel the so called heartbeat counter starts counting from
zero. The heartbeat counter counts up, until the heartbeat period has ended. The duration of the heartbeat period
is set to a default value, but can be adjusted via SPI command. The question consists of 4 bits, the expected
answer consists of 4 responses of 8 bits each. The four responses shall be sent before the heartbeat period has
ended. The last response shall be written to the synchronized response register to reset the heartbeat counter.

Initialization
The functional watchdog is off per default when the device is powered up for the first time. It can be enabled by
SPI writing to WDCFG0.FWDEN.

Data Sheet 224 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

Configuration
The functional watchdog can be configured in INIT, NORMAL and WAKE state. “Configured” means:
• Modify the length of the heartbeat period by SPI command, depending on the needs of the application.
(combination of cycle time WDCYC and number of cycles for heartbeat WDHBTP) •
The threshold for the functional watchdog failure counter overflow can defined by SPI
The heartbeat period is based on the cycle time tCYCLE specified in Table 25.

Normal Operation
The question is taken out of the Table 26, the correct responses are listed in the same row. The sequence of
responses must be kept and can be derived from the response counter FWDSTAT0.FWDRSPC before sending
the response.
The response to the actual question defined in the table shall be composed by four subsequent response bytes.
A correct response to the given question in FWDSTAT0.FWDQUEST register shall be done in the following way.
• The first three responses shall be written into FWDRSP
• The last response should be written into FWDRSPSYNC to reset the heartbeat timer All four responses must
be written before the heartbeat period expires.
If the complete response (32 bits) is correct and if the last response byte was sent with synchronized respond, the
heartbeat counter will be reset and set to zero. If the complete answer (all four responses - 32 bits) is correct, it is
regarded as “Valid FWD triggering”, the functional watchdog error counter Σ FWO is decremented by 1. If the last
response was sent with synchronized response, the heartbeat counter will be reset, but if the answer is wrong,
this is regarded as “Invalid FWD triggering” and the functional watchdog error counter Σ FWO is incremented by
2.
An overflow of the functional watchdog error counter Σ FWO will trigger a “Move to INIT” event, reset the heartbeat
counter and set the functional watchdog error counter Σ FWO to zero.

QUESTION RESP3 RESP2 RESP1 RESP0

0 FF 0F F0 00

1 B0 40 BF 4F

2 E9 19 E6 16

3 A6 56 A9 59

4 75 85 7A 8A

5 3A CA 35 C5

6 63 93 6C 9C

7 2C DC 23 D3

8 D2 22 DD 2D

9 9D 6D 92 62

A C4 34 CB 3B

B 8B 7B 84 74

Data Sheet 225 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

C 58 A8 57 A7 Table 26
Functional
D 17 E7 18 E8 watchdog response
definition
E 4E BE 41 B1

F 01 F1 0E FE

Functional
watchdog output FWO
The functional watchdog output FWO is an internal signal: It is connected to the FWD failure counter. The value
of the functional watchdog FWO output is either “Valid FWD triggering” or “Invalid FWD Triggering”.

Data Sheet 226 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

Reset

Start Heartbeat and Yes

WDCFG0.FWDEN=’1'
generate initial
Question

No
Set response byte
Heartbeat stopped
number to 3
and cleared

Wait for response

byte

Heartbeat counter Yes

expired?

Reset heartbeat
No counter

No New response byte Increment FWD

received? error counter by 2

Yes

No
Last response byte?

Decrement
Yes
response byte
number

Synchronized Yes
response?
Reset heartbeat
counter
No

Response correct?
No

Synchronized Yes
No response?
Decrement FWD
error counter by 1
Yes

Increment FWD Generate new

error counter by 2 question

Figure 86 Functional watchdog flowchart diagram

Data Sheet 227 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.3.1 Timing Diagrams

15.3.1.1 Normal operation: Correct triggering

Figure 87 Normal operation: Correct triggering

1. A new question is generated, in parallel the heartbeat counter starts counting up (It is assumed, that a “Valid
FWD triggering” has happened before).
2. A correct response is received (RESP3)
3. A correct response is received (RESP2)
4. A correct response is received (RESP1)
5. A correct synchronized response is received (RESP0). All responses are correct, the sequence of responses
is correct and the last synchronized response was received before the heartbeat counter overflowed. The
heartbeat counter will be reset (set to zero). This is regarded as “Valid FWD triggering”, the functional
watchdog error counter Σ FWO is decremented by 1 (if the functional watchdog error counter value is higher
than zero).
6. A new question is generated, in parallel the heartbeat counter starts counting up

Data Sheet 228 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.3.1.2 Fault operation: Synchronization is missing

Figure 88 Fault operation: Synchronization is missing

1. A new question is generated, in parallel the heartbeat counter starts counting up (It is assumed, that a “Valid
FWD triggering” has happened before).
2. A correct response is received (RESP3)
3. A correct response is received (RESP2)
4. A correct response is received (RESP1)
5. A correct response is received (RESP0), but not synchronized (written in wrong register). So far, all responses
are correct, the sequence of responses is correct and the last not synchronized response was received before
the heartbeat counter overflow occurred. The heartbeat counter will not be reset and continue to count. This
is regarded as “Valid FWD triggering”, the functional watchdog error counter Σ FWO is decremented by 1 (if
the functional watchdog error counter value is higher than zero). A new question is generated.
6. The heartbeat counter is still counting up, waiting for the answer on the new question. Later in time the
heartbeat counter will expire and an overflow occurs. This is regarded as “Invalid FWD triggering”. The
functional watchdog error counter Σ FWO is incremented by 2. The heartbeat counter is reset.

Data Sheet 229 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

7. The heartbeat counter starts counting up. No new question is generated.

15.3.1.3 Fault operation: Answer is wrong

Figure 89 Fault operation: Answer is wrong

1. A new question is generated, in parallel the heartbeat counter starts counting up (It is assumed, that a “Valid
FWD triggering” has happened before)
2. A correct response is received (RESP3)
3. A correct response is received (RESP2)
4. An incorrect response is received (RESP1)
5. A correct response is received (RESP0). The heartbeat counter will be reset (set to zero). The complete
answer is not correct. This is regarded as “Invalid FWD triggering”. The functional watchdog error counter
Σ FWO is incremented by 2. The heartbeat counter is reset.
6. No new question is generated, but the heartbeat counter starts counting up.
Note: If i.e. RESP2 and RESP1 would be mixed, than both responses would be regarded as incorrect - the
responses have to be sent in correct order.

Data Sheet 230 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

15.3.1.4 Fault operation: Missing response

Figure 90 Fault operation: Answer is not complete

1. A new question is generated, in parallel the heartbeat counter starts counting up (It is assumed, that a “Valid
FWD triggering” has happened before).
2. A correct response is received (RESP3)
3. A correct response is received (RESP2)
4. A response is missing (RESP1)
5. A correct response is received (RESP0). So the last response is not the last response but the second last due
to the missing response (in this example RESP1). The functional watchdog will wait for all four responses to
be written, while the heartbeat counter keeps on counting. There is no fixed time for all four responses, but
they must be sent in correct order before the heartbeat counter expires.
6. The complete answer is not correct due to missing response RESP1. Although the last response is
synchronized, the heartbeat counter will not be reset and continue counting up until an overflow occurs. This
is regarded as “Invalid FWD triggering”. The functional watchdog error counter Σ FWO is incremented by 2.
The heartbeat counter is reset.

Data Sheet 231 Rev. 2.0, 2017-03-16

 TLF35584

Window Watchdog And Functional Watchdog

7. No new question is generated and the heartbeat counter starts counting up.

Data Sheet 232 Rev. 2.0, 2017-03-16

 TLF35584

Application Information

16 Application Information
This is the description how the IC is used in its environment

Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
• Please contact us for addtional supportive documentation.
• For further information you may contact http://www.infineon.com/
Note:This following figure is a very simplified example of an application circuit. The function must be verified in
the real application.

Table 27 Recommended values for parts in application diagram

Name Value Switching frequency range
Inductor step 22 µH 500 kHz
up
Capacitor step 100 µF 500 kHz
up
Filter inductor 4.7 µH 2.2 MHz
step down
filter capacitor 10 - 47 µF 2.2 MHz
step down
Filter inductor 22 µH
step down 400 kHz
filter capacitor 68 - 100 µF 400 kHz
step down

Data Sheet 233 Rev. 2.0, 2017-03-16

Data Sheet 240 Rev. 2.0, 2017-03-16
 TLF35584

Package Outlines

17 Package Outlines

Figure 92 PG-VQFN-48
Package Outlines

Data Sheet 236 Rev. 2.0, 2017-03-16

 TLF35584

Figure 93 PG-LQFP-64

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb?free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages. Dimensions in mm
Revision History

Data Sheet 237 Rev. 2.0, 2017-03-16

 TLF35584

18 Revision History
Revision Date Changes

2.0 2017-03-16 Data sheet for TLF35584 C14 silicon.

Page 6: Chapter 1: Component marking changed.
Page 8: Chapter 3: Pin Assignment changed:
PG-VQFN-48: Pins 44, 45, 39, 36, 35 and 34 changed to internally not connected.
Corresponding update of figures, text and tables: Figure 1, Figure 2, Chapter 3.2,
Figure 3, Chapter 3.4, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11,
Figure 12, Figure 13, Figure 14, Chapter 8
Page 8: Chapter 3: Voltage VS1/2 changed to VVS in the entire document.
Page 31: Figure 8: Pin AG5 (typo) removed from figure.
Page 34: Chapter 6.3.2: Table 8: Highside Rdson changed from 580 to 630 mΩ.
Page 45: Chapter 7.2.2: Table 10: PSRRQUC test condition corrected.
Page 51: Chapter 7.3.2: Table 11: PSRRQCO test condition corrected.
Page 54: Figure 13: Typo corrected.
Page 54: Chapter 7.4.2: Table 12: PSRRQVR test condition corrected.
Page 57: Chapter 7.5.2: Table 13: PSRRQTx test condition corrected.
Page 78: Figure 23: Typo corrected.
Page 221: Figure 77: INTMISS flag behavior in case of multiple events corrected.
All pages: Figures corrected to imply pin configuration for both package variants
(Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12,
Figure 13, Figure 14, Figure 91).

1.0 2016-02-15 Initial release of Data Sheet.

Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™,
CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™,
LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™,
PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™,
SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™,
TriCore™, UHVIC™, XHP™, XMC™.

Trademarks updated November 2015

Data Sheet 238 Rev. 2.0, 2017-03-16

Edition 2017-03-16
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG
All Rights Reserved.

Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.