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Solution Assignment 2

The document contains solutions to 6 questions related to logic design and minimization. Question 1 asks to convert a logic schematic to NAND-only realization. Question 2 asks to implement a logic function as a minimized 2-level NOR/OR circuit. Question 3 involves drawing a K-map and finding prime implicants for a given logic function. Question 4 asks to draw the dual of a logic function implementation without generating the equation. Questions 5 and 6 involve using K-maps to minimize Boolean equations and write the output variables of a binary-to-excess-3 code converter in minimized SOP form.

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Tayyab Abbas
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122 views4 pages

Solution Assignment 2

The document contains solutions to 6 questions related to logic design and minimization. Question 1 asks to convert a logic schematic to NAND-only realization. Question 2 asks to implement a logic function as a minimized 2-level NOR/OR circuit. Question 3 involves drawing a K-map and finding prime implicants for a given logic function. Question 4 asks to draw the dual of a logic function implementation without generating the equation. Questions 5 and 6 involve using K-maps to minimize Boolean equations and write the output variables of a binary-to-excess-3 code converter in minimized SOP form.

Uploaded by

Tayyab Abbas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment # 4

Solution

Q1. Convert the following logic schematic diagram into NAND-only realization. You may use two
-input NAND gates and inverters.
Solution:

Q2. Implement the following function as a minimized 2-level NOR/OR circuit. Show your work
below.
F(A,B,C,D) = M(1,2,6,7,8,9,12,13,14,15)
Solution:
NOR/OR means circle 1s in K-map, take complement at end.
F = acd + abc + bcd + abc
Taking complement:
F = (a+c+d)(a+b+c)(b+c+d)(a+b+c)
Q3. Draw a Karnaugh map for the Boolean function
F (w, x, y, z) = wx+wz+xz+xyz+wxy+w yz

(a)
Solution:

(b) List all Prime Implicants of F.


Solution:
All terms in the original expression are PI’s.
(c) List all Essential Prime Implicants of F.
Solution:
wz, xz
(d) What is the minimal number of NAND gates required to realize this function in a two-level network?
Solution:
SOP is wz+ xz + wxy .
So min two-level implementation requires 4 NAND gates.

Q4. Implementation of a logic function using AND, OR and NOT gates is give below. Draw the dual of
this function without generating the equation.
Solution:
Q5. Use K-map to minimize the following Boolean Equations which contain don’t care minterms.
Provide a minimal SOP form expression for F.
a) F (A, B, C, D) = m (2, 3, 4, 10, 12, 13) + d (11, 14, 15)
Solution:
SOP: F  AB  BC  BC D
b) F (A, B, C, D) = m (1, 4, 5, 6, 8, 9, 11) + d (2, 7, 15)
Solution:
SOP: F  AB  ABC  ABD

Q6. Write the truth-table of a binary-to Excess-3-BCD code-converter. Using K-map minimization
technique, write the output variables as functions of input variables in minimized SOP form. Note that
the output variables are don’t cares (X’s) for all invalid input patterns. Show the SOP in NAND-NAND
form.
Solution:
Truth-Table:
A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
K-Maps:

Z= D
X  BC  BD  BC D

W  A  BC  BD

Y  CD  C D

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