Analog Integrated Circuit Design

Nagendra Krishnapura (nagendra@ee.iitm.ac.in)

Assignment 5

Vdd Vdd Cs gmvx

Rs Rs Rs Rs +
vx
L Rdiff L L ix L -
C C
Zin
vom vop
vom vop CL

I0
I0
Figure 3: Problem 3
(a)
(b)
3. Calculate the input impedance Zin (s) in Fig. 3.
Do you see anything special? What is the input
Figure 1: Problem 1
impedance with gm = 0?

1. Calculate the current flowing in each transistor in Express Zin (s)|gm ̸=0 as a parallel combination of
Fig. 1(a) in the quiescent condition. Calculate the Zin (s)|gm =0 and another branch Z1 (s). What does
small signal differential resistance Rout looking into Z1 (s) consist of?
the drains of the two transistors.
Rs Cs gmvx
In Fig. 1(b), calculate (vop − vom )/ix . What is the
+
condition for this to be infinity? What is the fre- vx
quency at which this happens? -

Vdd
Zin

C1
Zin Figure 4: Problem 4
I0
C2
4. Calculate the input impedance Zin (s) in Fig. 4. Do
you see anything special? Derive an equivalent cir-
cuit with passive elements that has an impedance
Figure 2: Problem 2 Zin .

2. Calculate the input impedance Zin in Fig. 2. Is there 5. Calculate the small signal impedance vx /ix . What is
anything special about it? Model the transistor using the condition for this to be infinity? What is the fre-
only its gm . quency at which this happens? Model the transistor

1
2 Nagendra Krishnapura (nagendra@iitm.ac.in)

Vdd
vx

L
ix C1

Rs I0
C2
10MHz
VCO
PFD
reference &
Figure 5: Problem 5 charge
C2
pump R1 Kvco

using only its gm .

(Icp)
C1
N inverters(N: odd)

divider

(a)
Figure 6: Problem 6 Vdd

6. In Fig. 6, assume that all nodes are at the self bias

Icp
voltage of the inverter. Model the small signal gain
of each inverter as A0 /(1 + s/p1 ) and calculate the QA (UP)
1
condition for instability (i.e. when the loop gain be- D Q
A
comes −1). Hint: Among the roots of −1, pick the iout
ref RST
one which satisfies the above for the lowest value of
A0 .
B RST
7. What is the function of the circuits in Fig. 1(b), div
QB (DN)
Fig. 5, and Fig. 6? D Q
1
8. Fig. 7(a) shows a phase-locked loop which multi-
plies a 10 MHz reference up to 1 GHz. The charge Icp
pump details are shown in Fig. 7(b). KV CO =
100 MHz/V; ICP = 100µA; R = 10 kΩ; C1 =
10 nF; C2 = 0; (b)
Determine the loop bandwidth and the location of the
Figure 7: Problem 1
loop-gain zero.
Determine C2 such that the phase margin is degraded
by no more than 5◦ compared to the original. De-
termine the extra attenuation (in ϕout (s)/ϕref (s)) at
the reference frequency due to the addition of this
value of C2 .