EE8351

DIGITAL LOGIC CIRCUITS

S.S.Harish
Department of EEE
UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND
PROGRAMMABILITY LOGIC DEVICES
Objective
To introduce asynchronous sequential circuits and PLDs

• Asynchronous sequential logic circuits

• Transition table
• flow table
• race conditions
• Hazards & Errors in digital circuits;
• Analysis of asynchronous sequential logic circuits
• Introduction to Programmability Logic Devices:
• PROM
• PLA
• PAL
• CPLD
• FPGA
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 Asynchronous sequential logic circuits
• Synchronous sequential circuits-
• State change in synchronism with clock
• Asynchronous sequential circuits
• State change when input variable change
• Event driven circuit
• No flip flop; No clock
• Gate circuit with propagation delay-Delay elements
• Present state-secondary variable
• Next state- excitation variable

• X-input variable
• y- secondary variable
• Y- excitation variable
• O- output variables
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 Programmable Logic Devices
• Programming- inserting bits into hardware configuration
• Combination of AND & OR logic

• PROM
• Fixed AND, programmable OR

• PAL- programmable array logic

• Programmable AND , Fixed OR

• PLA- Programmable logic array

• Programmable AND & OR
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 Programmable Logic Devices
ROM
• Read only memory-permanent binary information stored
• Input address of memory
• Output- stored bits
• 32 X 8 ROM 32 words of 8 bits
• 32 address  decoder (less to many)
• 8 bits
• 256 interconnections

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 Programmable Logic Devices
ROM
• Fuse at intersection or crosspoint

Truth table

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 Programmable Logic Devices
ROM
• Question: 3 bit number as input, output is square of the number
Truth table
• Solution Input Output
• 3 bits input, A2 A1 A0 O5 O4 O3 O2 O1 O0
A
d
X
• maximum 7, 0 0 0 0 0 0 0 0 0 X
3x8
• square of 7-49 0 0 1 0 0 0 0 0 1 decoder X
X X

• requires 6 bits 0 1 0 0 0 0 1 0 0 X X X
X X
• 3 bit input, 6 bit output 0 1 1 0 0 1 0 0 1 X X X
1 0 0 0 1 0 0 0 0
• Decoder: 3 x 8
1 0 1 0 1 1 0 0 1
• 8 x 6 selectable crosspoints
1 1 0 1 0 0 1 0 0 O
1 1 1 1 0 1 0 0 1

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 Programmable Logic Devices
ROM
• For given input only one decoder output X A’B’C’
A
• Multiple functions using single ROM X
X
A’B’C
A’BC’
B 3x8 A’BC
• F1= Σm(0,1,3)=A’B’C’+A’B’C+A’BC decoder
X X
X AB’C’
• F2= Σm(2,3,4,5)=A’BC’+A’BC+AB’C’+AB’C C X AB’C
ABC’
• 3 Inputs, 2 Outputs ABC

• 2 OR gates for 2 functions Output F1 F2

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 Programmable Logic Devices
ROM
• Mask programming-
• Manufacturer makes masks for a given combinational logic
• Only for mass production
• PROM-
• All fuse intact-
• No connection- blown using high-voltage pulse
• Used Only once
• EPROM
• Erasable PROM- reset using ultraviolet radiation
• EEPROM
• Electrically EPROM
• Reset using electrical signal 9
 Programmable Logic Devices
PLA • F1=A’B’+A’C
• Programmable AND & OR • F2= A’B+AB’
• ROM- implement truth table • 3 inputs, 4 products term, 2 output
• PLA- implement SOP A A’ B B’ C C’
• Product terms using AND array, sum using OR
A’B’
• F1= Σm(0,1,3)=A’B’C’+A’B’C+A’BC X X X

• F2= Σm(2,3,4,5)=A’BC’+A’BC+AB’C’+AB’C X X
A’C
X

• To get SOP, reduce using K-map X X

A’B
X
K-map for F1 K-map for F2
A BC AB’
A BC 00 01 11 10 X X X
00 01 11 10
0 1 1
0 1 1 1
1 1 1 F1 F210
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 Programmable Logic Devices
PAL
• Programmable AND, fixed OR
A
• Product terms using AND array,
A’
• Careful choose of AND B

• sum with fixed OR B’

C
• F1= Σm(0,1,3)=A’B’C’+A’B’C+A’BC C’
• F2= Σm(2,3,4,5)=A’BC’+A’BC+AB’C’+AB’C X X
F1
• To get SOP, reduce using K-map X X
• F1=A’B’+A’C
• F2= A’B+AB’
X X
• 1 function- 2 products term F2
• 2 AND with one OR  fixed for this X X
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 Programmable Logic Devices
PROM PLA PAL
A A’ B B’ C C’ A
X A’B’C’
A A’
X A’B’C
A’B’ B
3x8 X A’BC’ X X X
B B’
decod X X A’BC
A’C C
er X AB’C’ X X X
X AB’C C’
C
ABC’ A’B X X F1
ABC X X X
X X
AB’
X X X
F1 F2
X X
F1= Σm(0,1,3)=A’B’C’+A’B’C+A’BC F2
F1 F2
F2= Σm(2,3,4,5)=A’BC’+A’BC+AB’C’+AB’C X X

PROM PLA PAL

Programmability Fixed AND- programmable OR AND OR- both programmable Programmable AND- fixed OR
Speed All minterms- Medium speed Flexible- dependent on function Select minterms- very fast
Cost Cheap Expensive and sophisticated Cheaper 12
 Programmable Logic Devices

PLA
PAL

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 Programmable Logic Devices
CPLD
• Complex Programmable logic devices
• Instead of single PLA or PAL
• Combination of many PLA or PAL
• Manufacturer specific

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 Programmable Logic Devices
FPGA
• Field programmable gate array
• Programmable at user location
• Uses RAM
• To store- lookup table(LUT)

• To design PLD (PLA,PAL,CPLD,FPGA)

• Computer design- required
• Hardware description Language (HDL)- popular

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 Hazards
• Momentary Unexpected transitions- glitch
• Glitch create- hazard
Hazard

Static Dynamic
Static-0 Static-1
• Static hazard- transition has no effect on steady state output
• Static-0 output should be 0, momentary goes to 1
• Static 1 output should be 1, momentary goes to 0
• Dynamic- one input transition result in 3 or more transitions in output
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 Hazards
Causes of hazard
• Propagation delay
• Different path lengths
• Assumption: only one input, others assumed constant

1 C
1 10
G1

01 G2
0 1
1
101 G3
0

G4
1 0
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 Hazards
• Can be identified from k-map
A BC
00 01 11 10

0 1

1 1 1 1

• Reduced function- all ones covered

F=AC’+BC

• Not all Adjacent ones covered for minimization- result in hazard

• To remove hazard- cover all adjacent ones F=AC’+BC+AB

• To avoid hazard
• Will not be in reduced SOP form 18
 Hazards

• Design hazard free circuit for

• F=Σm (1,3,6,7,13,15)
AB CD 00 01 11 10
00 1 1
01 1 1
11 1 1
10

• F=A’B’D+A’BC+ABD
• Hazard will be present as not all adjacent ones are covered
• F=A’B’D+A’BC+ABD+A’CD+BCD
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 Hazards
• Design hazard free circuit for
• F=πM(0,1,4,5,6,7,9,14,15)
AB CD 00 01 11 10
00 0 0 • F’=(A’C’+BC+B’C’D)’
01 0 0 0 0 • Reduction all zero’s covered
11 0 0 • Hazard- all adjacent zeros covered-no
10 0 • F’=(A’C’+BC+B’C’D+A’BD)’

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 Hazards

• Dynamic hazard- 3 or more transitions

• If circuit is free from Static-0 and Static-1 hazard- no static hazard

• No static hazardfree from Dynamic hazard

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Asynchronous sequential logic circuits

• Present state-secondary variable

• Next state- excitation variable

• X-input variable
• y- secondary variable
• Y- excitation variable
• O- output variables

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 Asynchronous sequential logic circuits
Characteristics
• Only one input is allowed to change at a instant
• 2 or more input variable change prohibited
• yi= Yi  circuit is stable
• Input given- yi ≠ Yi ; for time of propagation delay; circuit is unstable
• After delay- circuit is stable
• One input change at a instant in stable state- Fundamental mode
• Transition table- same as state table
• Flow table- states as letters
• Primitive flow table- only one stable state for input combination
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 Asynchronous sequential logic circuits
• AND gate- output is feedback with delay as input
• Truth table- from k-map
• Encircled- stable state, x=X
• arrow - state change

x A 0 1

0 0 0

1 0 1

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 Asynchronous sequential logic circuits

• Two NAND gate

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 Asynchronous sequential logic circuits
K map for output 1 (Eq 1) K map for output 2 (Eq 2)
Design
y1y2 x 0 1 y1y2 x 0 1
Y1=x.y1+x’.y2
00 0 0 00 0 1
Y2=x.y1’ +x’.y2
01 1 0 01 1 1
11 1 1 11 1 0
10 0 1 10 0 0

Combined K map for both output

y1y2 x 0 1 y1y2 x 0 1
00 00 01 a a b
01 11 01 b c b
11 11 10 c c d
10 00 10 d a d

Transition table Flow table

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 Asynchronous sequential logic circuits
Errors and Hazard
• Oscillation
• Change between 2 unstable state
• Must be avoided
• Race-
• Input change modifies more than one output
• Critical race- results in 2 different outputs-
• Must be avoided
• Non-critical race- different path but same output
• Hazard- Static and dynamic
• Essential hazard- change in input not reached one part but reach by feedback
• To be avoided by additional gates without change in logic level
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 Asynchronous sequential logic circuits

• Design a gated latch with 2 inputs load and data with 1 output O.
When load = 1, accepts the value of D, when load=0 retains the value.
• 2 input, 1 secondary variable, 1 output L L’ D D’

Transition table State table

s LD s LD O
00 01 11 10 O 00 01 11 10 O
0 0 0 1 0 0
a a a b a 0

1 1 1 1 0 1
b b b b a 1

Q=load. data + load’. Q +data. Q

O=Q
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 Asynchronous sequential logic circuits
Design procedure
• 1. Define the problem
• 2. Draw block diagram with all inputs and outputs
• 3. Draw state diagram
• 4. Obtain state transition and flow table
• 5. Plot k-map for next state and output using present state and inputs
• 6. Derive the Boolean expression for excitation variable and output
• 7. Implement the excitation equations and output equations using
logic gates

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 Asynchronous sequential logic circuits
• Design asynchronous sequential circuit has 2 input A,B and 1 output Q. When
A=0, then Q=0. First change in B that accurs when A=1 cause Q=1. Q will
00
remain in 1 until A returns to 0. 01
Q AB 01
00 01 11 10 out a/0 b/0
00
a a b x c 0
10 00 11 01
b a b d x 0 01
c/0 d/0
A c x e c 0
a 10
11
d b d e 0 10 11
B x
e/1
e x b e e 1
Q
11
Flow table 10
Timing diagram Trantition diagram
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 Asynchronous sequential logic circuits
d,x
• State reduction b
c,x d:d
• Implication table c b,x c:cd
e,x b: bcd
a,x a:bcd (ab)(ac)=ab
d
Q AB e,x
00 01 11 10 out e P: (ab) (c) (d) (e)
a a b x c 0 a b c d
implication table
b a b d x 0
Q AB
00 01 11 10 out
c a x e c 0
a a a x c 0
d x b d e 0
c a x e c 0
e x b e e 1
d x a d e 0 Reduced Flow table
Flow table a e 1
e x e
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 Asynchronous sequential logic circuits
State assignment
4 states – 2 variables for
K-map for p (first variables from K-map for Q (second variables
state, Q, P
state assignment table) from state assignment table)
pQ AB pQ AB pQ AB
00 01 11 10 00 01 11 10 00 01 11 10
00 01 00 0 0 0 0 0 0 1 0
00 00 00 00

00 01 11 01 X 0 0 1 X 0 1 1
01 x 01
10 x 01 11 11 1 X 0 1 0 X 1 1
11 11
00 x x x 10 0 x x x 0 X x X
10 10

p=QB’ Q=AB+QA

*ensure no hazard
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 Asynchronous sequential logic circuits

p=QB’
Q=AB+QA
X=pQ
Only when both p and Q 1, output is 1

Implementation using logic gates

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 Course outcome
• Asynchronous sequential circuit
• Excitation variable, Secondary variable
• Transition table, flow table
• State reduction using Implication table
• Hazard and Error
• Static-0, Static-1, Dynamic- for all digital circuits  Hazard free from k-map
• Oscillation covering of adjacent ones
• Race- Critical and non critical
• Essential hazard
• Programmable logic device
• PROM- fixed input(AND), programmable output (OR)
• PAL- programmable input(AND), fixed output (OR)
• PLA- programmable input and output (AND, OR)
• CPLD- More PAL’s or PLA’s
• FPGA- RAM with Lookup table(LUT) 34