Low Cost, 300 MHz

Rail-to-Rail Amplifiers
Data Sheet AD8061/AD8062/AD8063
FEATURES CONNECTION DIAGRAMS
Low cost AD8062
VOUT1
Single (AD8061), dual (AD8062) AD8061/
1 8 +VS

Single with disable (AD8063) NC 1 AD8063 8 DISABLE

(AD8063 ONLY) –IN1 2 7 VOUT2
Rail-to-rail output swing –IN 2 7 +VS
+IN1 3 6 –IN2
Low offset voltage: 6 mV +IN 3 6 VOUT

High speed

01065-001
–VS 4 5 NC –VS 4 5 +IN2

01065-003
(Not to Scale)
300 MHz, −3 dB bandwidth (G = 1) NC = NO CONNECT (Not to Scale)

650 V/µs slew rate Figure 1. 8-Lead SOIC (R) Figure 2. 8-Lead SOIC (R)/MSOP (RM)
8.5 nV/√Hz at 5 V
35 ns settling time to 0.1% with 1 V step VOUT 1
AD8063
6 +VS
AD8061
VOUT 1 5 +VS
Operates on 2.7 V to 8 V supplies
–VS 2
Input voltage range = −0.2 V to +3.2 V with VS = 5 V 5 DISABLE
–VS 2

01065-004
Excellent video specifications (RL = 150 Ω, G = 2)

01065-002
+IN 3 4 –IN
+IN 3 4 –IN
(Not to Scale)
Gain flatness: 0.1 dB to 30 MHz (Not to Scale)

0.01% differential gain error Figure 3. 6-Lead SOT-23 (RJ) Figure 4. 5-Lead SOT-23 (RJ)
0.04° differential phase error
35 ns overload recovery
Low power 3
RF = 50Ω
6.8 mA/amplifier typical supply current
AD8063 400 µA when disabled 0
VO = 0.2V p-p
NORMALIZED GAIN (dB)

RL = 1kΩ RF = 0Ω
VBIAS = 1V
APPLICATIONS –3

Imaging RF

Photodiode preamps –6
OUT
Professional video and cameras IN RL
Handsets 50Ω
–9
DVDs/CDs VBIAS

01065-005
Base stations
–12
Filters 1 10 100 1k
ADC drivers FREQUENCY (MHz)

Clock buffers Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω

GENERAL DESCRIPTION
The AD8061/AD8062/AD8063 are rail-to-rail output voltage 150 Ω load, along with 0.1 dB flatness out to 30 MHz. Addi-
feedback amplifiers offering ease of use and low cost. They have tionally, they offer wide bandwidth to 300 MHz along with
a bandwidth and slew rate typically found in current feedback 650 V/µs slew rate.
amplifiers. All have a wide input common-mode voltage range The AD8061/AD8062/AD8063 offer a typical low power of
and output voltage swing, making them easy to use on single 6.8 mA/amplifier, while being capable of delivering up to
supplies as low as 2.7 V. 50 mA of load current. The AD8063 has a power-down disable
Despite being low cost, the AD8061/AD8062/AD8063 provide feature that reduces the supply current to 400 µA. These features
excellent overall performance. For video applications, their make the AD8063 ideal for portable and battery-powered
differential gain and phase errors are 0.01% and 0.04° into a applications where size and power are critical.

Rev. J Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1999–2013 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD8061/AD8062/AD8063 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Headroom Considerations ........................................................ 14
Applications ....................................................................................... 1 Overload Behavior and Recovery ............................................ 15
Connection Diagrams ...................................................................... 1 Capacitive Load Drive ............................................................... 16
General Description ......................................................................... 1 Disable Operation ...................................................................... 16
Revision History ............................................................................... 2 Board Layout Considerations ................................................... 16
Specifications..................................................................................... 3 Applications Information .............................................................. 17
Absolute Maximum Ratings ............................................................ 6 Single-Supply Sync Stripper ...................................................... 17
Maximum Power Dissipation ..................................................... 6 RGB Amplifier ............................................................................ 17
ESD Caution .................................................................................. 6 Multiplexer .................................................................................. 18
Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 19
Circuit Description ......................................................................... 14 Ordering Guide .......................................................................... 20

REVISION HISTORY
5/13—Rev. I to Rev. J
Added Output Voltage Swing Parameters; Table 1 ...................... 3
Added Output Voltage Swing Parameters; Table 2 ...................... 4
Added Output Voltage Swing Parameters; Table 3 ...................... 5
Changes to Ordering Guide .......................................................... 20
5/13—Rev. H to Rev. I
Changes to Figure 15 ........................................................................ 8
Changes to Ordering Guide .......................................................... 20
1/13—Rev. G to Rev. H
Changes to Figure 12 ........................................................................ 7
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
2/10—Rev. F to Rev. G
Changes to Table 4 ............................................................................ 6
11/09—Rev. E to Rev. F
Changed Input Common-Mode Voltage Range Parameter........ 4
Updated Outline Dimensions ....................................................... 19
10/07—Rev. D to Rev. E
Changes to Applications .................................................................. 1
Updated Outline Dimensions ....................................................... 19
12/05—Rev. C to Rev. D
Updated Format .................................................................. Universal
Change to Features and General Description ............................... 1
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
5/01—Rev. B to Rev. C
Replaced TPC 9 with new graph .................................................... 7
11/00—Rev. A to Rev. B
2/00—Rev. 0 to Rev. A
11/99—Revision 0: Initial Version

Rev. J | Page 2 of 20
Data Sheet AD8061/AD8062/AD8063

SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.

Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 320 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz
−3 dB Large Signal Bandwidth G = 1, VO = 1 V p-p 280 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p 30 MHz
Slew Rate G = 1, VO = 2 V step, RL = 2 kΩ 500 650 V/µs
G = 2, VO = 2 V step, RL = 2 kΩ 300 500 V/µs
Settling Time to 0.1% G = 2, VO = 2 V step 35 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −77 dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ −50 dBc
Crosstalk, Output to Output f = 5 MHz, G = 2, AD8062 −90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
Differential Gain Error (NTSC) G = 2, RL = 150 Ω 0.01 %
Differential Phase Error (NTSC) G = 2, RL = 150 Ω 0.04 Degrees
Third-Order Intercept f = 10 MHz 28 dBc
SFDR f = 5 MHz 62 dB
DC PERFORMANCE
Input Offset Voltage 1 6 mV
TMIN to TMAX 2 6 mV
Input Offset Voltage Drift 3.5 µV/°C
Input Bias Current 3.5 9 µA
TMIN to TMAX 4 9 µA
Input Offset Current ±0.3 ±4.5 µA
Open-Loop Gain VO = 0.5 V to 4.5 V, RL = 150 Ω 68 70 dB
VO = 0.5 V to 4.5 V, RL = 2 kΩ 74 90 dB
INPUT CHARACTERISTICS
Input Resistance 13 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage Range −0.2 to +3.2 V
Common-Mode Rejection Ratio VCM = –0.2 V to +3.2 V 62 80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Low RL = 150 Ω 0.3 0.1 V
RL = 2 kΩ 0.25 0.1 V
Output Voltage Swing High RL = 150 Ω 4.75 4.86 V
RL = 2 kΩ 4.85 4.9 V
Output Current VO = 0.5 V to 4.5 V 25 50 mA
Capacitive Load Drive, VOUT = 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF
G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE
Turn-On Time 40 ns
Turn-Off Time 300 ns
DISABLE Voltage (Off) 2.8 V
DISABLE Voltage (On) 3.2 V
POWER SUPPLY
Operating Range 2.7 5 8 V
Quiescent Current per Amplifier 6.8 9.5 mA
Supply Current when Disabled (AD8063 Only) 0.4 mA
Power Supply Rejection Ratio ∆VS = 2.7 V to 5 V 72 80 dB

Rev. J | Page 3 of 20
AD8061/AD8062/AD8063 Data Sheet
TA = 25°C, VS = 3 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.

Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz
–3 dB Large Signal Bandwidth G = 1, VO = 1 V p-p 250 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p 30 MHz
Slew Rate G = 1, VO = 1 V step, RL = 2 kΩ 190 280 V/µs
G = 2, VO = 1.5 V step, RL = 2 kΩ 180 230 V/µs
Settling Time to 0.1% G = 2, VO = 1 V step 40 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −60 dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ −44 dBc
Crosstalk, Output to Output f = 5 MHz, G = 2 −90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 1 6 mV
TMIN to TMAX 2 6 mV
Input Offset Voltage Drift 3.5 µV/°C
Input Bias Current 3.5 8.5 µA
TMIN to TMAX 4 8.5 µA
Input Offset Current ±0.3 ±4.5 µA
Open-Loop Gain VO = 0.5 V to 2.5 V, RL = 150 Ω 66 70 dB
VO = 0.5 V to 2.5 V, RL = 2 kΩ 74 90 dB
INPUT CHARACTERISTICS
Input Resistance 13 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage Range −0.2 to +1.2 V
Common-Mode Rejection Ratio VCM = –0.2 V to +1.2 V 80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Low RL = 150 Ω 0.3 0.1 V
RL = 2 kΩ 0.3 0.1 V
Output Voltage Swing High RL = 150 Ω 2.85 2.87 V
RL = 2 kΩ 2.9 2.9 V
Output Current VO = 0.5 V to 2.5 V 25 mA
Capacitive Load Drive, VOUT = 0.8 V 30% overshoot, G = 1, RS = 0 Ω 25 pF
G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE
Turn-On Time 40 ns
Turn-Off Time 300 ns
DISABLE Voltage—Off 0.8 V
DISABLE Voltage—On 1.2 V
POWER SUPPLY
Operating Range 2.7 3 V
Quiescent Current per Amplifier 6.8 9 mA
Supply Current when Disabled (AD8063 Only) 0.4 mA
Power Supply Rejection Ratio 72 80 dB

Rev. J | Page 4 of 20
Data Sheet AD8061/AD8062/AD8063
TA = 25°C, VS = 2.7 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.

Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz
G = 1, VO = 1 V p-p 230 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p, VO dc = 1 V 30 MHz
Slew Rate G = 1, VO = 0.7 V step, RL = 2 kΩ 110 150 V/µs
G = 2, VO = 1.5 V step, RL = 2 kΩ 95 130 V/µs
Settling Time to 0.1% G = 2, VO = 1 V step 40 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ –60 dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ –44 dBc
Crosstalk, Output to Output f = 5 MHz, G = 2 –90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 1 6 mV
TMIN to TMAX 2 6 mV
Input Offset Voltage Drift 3.5 µV/°C
Input Bias Current 3.5 µA
TMIN to TMAX 4 8.5 µA
Input Offset Current ±0.3 ±4.5 µA
Open-Loop Gain VO = 0.5 V to 2.2 V, RL = 150 Ω 63 70 dB
VO = 0.5 V to 2.2 V, RL = 2 kΩ 74 90 dB
INPUT CHARACTERISTICS
Input Resistance 13 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage Range –0.2 to +0.9 V
Common-Mode Rejection Ratio VCM = –0.2 V to +0.9 V 0.8 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Low RL = 150 Ω 0.3 0.1 V
RL = 2 kΩ 0.25 0.1 V
Output Voltage Swing High RL = 150 Ω 2.55 2.55 V
RL = 2 kΩ 2.6 2.6 V
Output Current VO = 0.5 V to 2.2 V 25 mA
Capacitive Load Drive, VOUT = 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF
G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE
Turn-On Time 40 ns
Turn-Off Time 300 ns
DISABLE Voltage (Off) 0.5 V
DISABLE Voltage (On) 0.9 V
POWER SUPPLY
Operating Range 2.7 8 V
Quiescent Current per Amplifier 6.8 8.5 mA
Supply Current when Disabled (AD8063 Only) 0.4 mA
Power Supply Rejection Ratio 80 dB

Rev. J | Page 5 of 20
AD8061/AD8062/AD8063 Data Sheet

ABSOLUTE MAXIMUM RATINGS

MAXIMUM POWER DISSIPATION
Table 4.
Parameter Rating The maximum power that can be safely dissipated by the
AD8061/AD8062/AD8063 is limited by the associated rise in
Supply Voltage 8V
junction temperature. The maximum safe junction temperature
Internal Power Dissipation1
for plastic encapsulated devices is determined by the glass
8-lead SOIC (R) 0.8 W
transition temperature of the plastic, approximately 150°C.
5-lead SOT-23 (RJ) 0.5 W
Temporarily exceeding this limit may cause a shift in parametric
6-lead SOT-23 (RJ) 0.5 W
performance due to a change in the stresses exerted on the die
8-lead MSOP (RM) 0.6 W
by the package. Exceeding a junction temperature of 175°C for
Input Voltage (Common-Mode) (−VS − 0.2 V) to (+VS + 0.2 V)
an extended period can result in device failure. While the
Differential Input Voltage ±VS
AD8061/AD8062/AD8063 is internally short-circuit protected,
Output Short-Circuit Duration Observe power derating curves
this may not be sufficient to guarantee that the maximum
Storage Temperature Range −65°C to +125°C
R-8, RM-8, SOT-23-5, SOT-23-6 junction temperature (150°C) is not exceeded under all
Operating Temperature Range −40°C to +85°C conditions.
Lead Temperature (Soldering, 300°C To ensure proper operation, it is necessary to observe the
10 sec) maximum power derating curves.
2.0
1
Specification is for device in free air.
8-Lead SOIC_N: θJA = 160°C/W; θJC = 56°C/W.
5-Lead SOT-23: θJA = 240°C/W; θJC = 92°C/W. 8-LEAD SOIC TJ = 150°C
MAXIMUM POWER DISSIPATION (W) PACKAGE
6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.
8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W. 1.5

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
1.0
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
0.5
maximum rating conditions for extended periods may affect MSOP

device reliability. SOT-23-5, SOT-23-6

01065-006
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)

Figure 6. Maximum Power Dissipation vs. Temperature for

AD8061/AD8062/AD8063

ESD CAUTION

Rev. J | Page 6 of 20
Data Sheet AD8061/AD8062/AD8063

TYPICAL PERFORMANCE CHARACTERISTICS

1.2 3
VOLTAGE DIFFERENTIAL FROM VS (Unit)

1.0 G = +1
+VOUT @ +85°C 0

NORMALIZED GAIN (dB)

+VOUT @ +25°C
0.8
–3 G = +2
+VOUT @ –40°C
0.6

–VOUT @ –40°C –6
0.4
G = +5

VO = 0.2V p-p
–9
0.2 –VOUT @ +85°C RL = 1kΩ

01065-007

01065-010
–VOUT @ +25°C VBIAS = 1V

0 –12
0 10 20 30 40 50 60 70 80 90 1 10 100 1k
LOAD CURRENT (mA) FREQUENCY (MHz)

Figure 7. Output Saturation Voltage vs. Load Current Figure 10. Small Signal Frequency Response

18 3
VO = 1.0V p-p
AD8062 RL = 1kΩ
16 G = +1
VBIAS = 1V
0
POWER SUPPLY CURRENT (mA)

14
G = +2
12 NORMALIZED GAIN (dB)
–3
10
AD8061
8 G = +5
–6
6

4 –9
01065-008

01065-011
2

0 –12
2 3 4 5 6 7 8 1 10 100 1k
SINGLE POWER SUPPLY (V) FREQUENCY (MHz)

Figure 8. ISUPPLY vs. VSUPPLY Figure 11. Large Signal Frequency Response

3 3
RF = 50Ω VS = 5V
VO = 0.2V p-p
RL = 1kΩ
0 0 VBIAS = 1V
VO = 0.2V p-p
NORMALIZED GAIN (dB)

NORMALIZED GAIN (dB)

RL = 1kΩ RF = 0Ω
G = –1
VBIAS = 1V
–3 –3 G = –5
G = –2
RF

–6 –6
OUT
IN RL
50Ω
–9 –9
VBIAS
01065-009

01065-012

–12 –12
1 10 100 1k 1 10 100 1k
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 9. Small Signal Response, RF = 0 Ω, 50 Ω Figure 12. Small Signal Frequency Response

Rev. J | Page 7 of 20
AD8061/AD8062/AD8063 Data Sheet
3 0
VS = 5V VS = 5V
VO = 1V p-p –10 RL = 1kΩ
RL = 1kΩ G = +1
0 VBIAS = 1V –20

HARMONIC DISTORTION (dBc)

NORMALIZED GAIN (dB)

–30
G = –1
2ND @ 1MHz
–3 –40

G = –2 –50 3RD @ 10MHz

–6 –60

G = –5 –70

–9 –80

01065-016
01065-013
–90
2ND @ 10MHz 3RD @ 1MHz
–12 –100
1 10 100 1k 0.5 1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY (MHz) INPUT SIGNAL DC BIAS (V)

Figure 13. Large Signal Frequency Response Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias

0.1 –40
VS = 2.7V VO = 0.2V p-p 604Ω
RL = 1kΩ 5V 10µF
+
0 VBIAS = 1V –50
0.1µF
G = +1
1kΩ
50Ω
NORMALIZED GAIN (dB)

–60 1MΩ INPUT

52.3Ω
–0.1
DISTORTION (dB)
0.1µF +
VS = 5V 1kΩ
1.25Vdc (RLOAD)
–70 –

–0.2 VS = 3V
–80
2ND H
–0.3
–90

–0.4
–100
01065-014

01065-017
3RD H
–0.5 –110
1 10 100 1k 0.01 0.1 1 10 50
FREQUENCY (MHz) FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)

Figure 14. 0.1 dB Flatness Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs.
Input Signal DC Bias

80 200 –30
VS = 5V
150 –40 RL = 1kΩ
G = +5
60 VO = 1V p-p
PHASE 100 –50 2ND 3RD 10MHz
OPEN-LOOP GAIN (dB)

50
–60
DISTORTION (dB)

40
PHASE (Degrees)

GAIN
0
–70
20 –50
–80
–100
0 –90 2ND
–150 3RD 5MHz
–100 1MHz
–200
– 20
01065-018

–110
01065-015

–250 2ND 3RD

– 40 –300 –120
0.01 0.1 1 10 100 1k 0 1 2 3 4 5

FREQUENCY (MHz) OUTPUT SIGNAL DC BIAS (V)

Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency, Figure 18. Harmonic Distortion vs. Output Signal DC Bias
VS = 5 V, RL = 1 kΩ

Rev. J | Page 8 of 20
Data Sheet AD8061/AD8062/AD8063
–40
VS = 5V
RF = RL = 1kΩ
–50 G = +2 2ND @ 10MHz
0.01

DIFFERENTIAL GAIN
0
–60 5V + 10µF –0.01

(%)
DISTORTION (dB)

1MΩ –0.02
0.1µF INPUT
–70 50Ω
50Ω TO 2ND @ 2MHz –0.04
1kΩ 1kΩ 1kΩ 3589A
–0.06
–80 2ND @ 500kHz 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

–90

DIFFERENTIAL PHASE
3RD @ 2MHz 0.02

(Degrees)
0
–100

01065-019
3RD @ 500kHz –0.02

–110 –0.04

01065-022
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
–0.06
RTO OUTPUT (V p-p)
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

Figure 19. Harmonic Distortion vs. Output Signal Amplitude Figure 22. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 1 kΩ, VS = 5 V

–30
VS = 5V

DIFFERENTIAL GAIN
RI = RL = 1kΩ 0.010
–40
VO = 2V p-p
G=2 0.005

(%)
–50
0
DISTORTION (dB)

S1 3RD HARMONIC/ –0.005

–60 DUAL ±2.5V SUPPLY
–0.010
S1 2ND HARMONIC/
–70 DUAL ±2.5V SUPPLY 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

–80 S1 2ND HARMONIC/

DIFFERENTIAL PHASE

SINGLE +5V SUPPLY 0.04

0.03
(Degrees)

–90 0.02
0.01
–100
01065-020

S1 3RD HARMONIC/ 0
SINGLE +5V SUPPLY –0.01

01065-023
–110 –0.02
0.01 0.1 1 10
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)

Figure 20. Harmonic Distortion vs. Frequency Figure 23. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 150 Ω, VS = 5 V

1.0 1000
VS = 5V
FALLING EDGE
0.9 RL = 1kΩ 900 VS = 5V
G = +1 RL = 1kΩ
0.8 800 G = +1

700
OUTPUT VOLTAGE (V)

0.7
SLEW RATE (V/µs)

RISING EDGE
0.6 600

0.5 500

0.4 400

0.3 300

0.2 200
01065-024
01065-021

0.1 100

0 0
0 0.1 0.2 0.3 0.4 0.5 1.0 1.5 2.0 2.5 3.0

TIME (µs) OUTPUT STEP AMPLITUDE (V)

Figure 21. 400 mV Pulse Response Figure 24. Slew Rate vs. Output Step Amplitude

Rev. J | Page 9 of 20
AD8061/AD8062/AD8063 Data Sheet
1400
VS = ±2.5V
FALLING EDGE G = +1
1200 VIN RL = 1kΩ
VS = ±4V
2.5V

1000 FALLING EDGE

VS = +5V
SLEW RATE (V/µs)

VOUT

VOLTS
800

600 RISING EDGE

VS = ±4V 0V
400 RISING EDGE
VS = +5V
200

01065-028
01065-025
500mV/DIV

0
0 20 40 60 80 100 120 140 160 180 200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
TIME (ns)
OUTPUT STEP (V)

Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, RL = 1 kΩ, VS = 5 V Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V

1k
VS = ±2.5V
VS = 5V G = +5
RL = 1kΩ RL = 1kΩ

VOUT
VOLTAGE NOISE (nV/ Hz)

2.5V
100 VOLTS

VIN
1.0V
10

0V

01065-029
01065-026

500mV/DIV

1
10 100 1k 10k 100k 1M 10M 0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz) TIME (ns)

Figure 26. Voltage Noise vs. Frequency Figure 29. Output Overload Recovery, Input Step = 0 V to 1 V

100 0
VCM = 0.2V p-p
VS = 5V –10 RL = 100Ω
RL = 1kΩ
–20 VS = ±2.5V SIDE 2
CURRENT NOISE (pA/ Hz)

10 –30
SIDE 1
CMRR (dB)

–40

–50

–60 604Ω
1
604Ω
–70 50Ω
VIN 154Ω
–80 200mV p-p
57.6Ω 154Ω
01065-027

01065-030

–90
0 –100
10 100 1k 10k 100k 1M 10M
0.01 0.1 1 10 100 500
FREQUENCY (Hz)
FREQUENCY (MHz)

Figure 27. Current Noise vs. Frequency Figure 30. CMRR vs. Frequency

Rev. J | Page 10 of 20
Data Sheet AD8061/AD8062/AD8063
0 7
ΔVS = 0.2V p-p
RL = 1kΩ VS = 5V
–10
VS = 5V 6
–20
–PSRR
–30 5

ISUPPLY (mA)
–40
PSRR (dB)

4
–50
+PSRR 3
–60

–70 2

–80
1

01065-034
01065-031
–90

–100 0
0.01 0.1 1 10 100 500 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz) DISABLE VOLTAGE

Figure 31. ±PSRR vs. Frequency Delta Figure 34. AD8063 DISABLE Voltage vs. Supply Current

–20 6
1kΩ 1kΩ VS = 5V
–30 G = +2
OUTPUT TO OUTPUT CROSSTALK (dB)

+2.5V 5 VDISABLE fIN = 10MHz

–40 @ 1.3VBIAS
RL = 100Ω
OUT 4

OUTPUT VOLTAGE (V)

–50 IN
1kΩ
50Ω
–60 –2.5V
3
–70
INPUT = SIDE 2 INPUT = SIDE 1 2
–80

–90 VS = 5V 1
VIN = 400mV rms
–100 RL = 1kΩ
G = +2 0 VOUT
01065-032

01065-035
–110

–120 –1
0.01 0.1 1 10 100 500 0 0.4 0.8 1.2 1.6 2.0
FREQUENCY (MHz) TIME (µs)

Figure 32. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 kΩ, G = 2, VS = 5 V Figure 35. AD8063 DISABLE Function, Voltage = 0 V to 5 V

0 1k
VS = 5V
VS = 5V
VO = 0.2V p-p
–10 VO = 0.2V p-p
RL = 1kΩ
RL = 1kΩ
VBIAS = 1V 100
–20 VBIAS = 1V
DISABLED ISOLATION (dB)

–30
IMPEDANCE (Ω)

10
–40

–50
1
–60

–70
0.1
01065-033

01065-036

–80

–90 0.01
1 10 100 1k 0.1 1 10 100 1k
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 33. AD8063 Disabled Output Isolation Frequency Response Figure 36. Output Impedance vs. Frequency,
VOUT = 0.2 V p-p, RL = 1 kΩ, VS = 5 V

Rev. J | Page 11 of 20
AD8061/AD8062/AD8063 Data Sheet
VS = 5V VS = 5V
RL = 1kΩ G = +2
RL = 1kΩ
VIN = 1V p-p
SETTLING TIME TO 0.1%

+0.1% 3.5V

VOLTS
–0.1% 2.5V

1kΩ 1kΩ

1.5V

RL = 1kΩ
50Ω

01065-037

01065-040
500mV/DIV
t=0

0 10 20 30 40 50 60 70 80 90 100
20ns/DIV
TIME (ns)

Figure 37. Output Settling Time to 0.1% Figure 40. 1 V Step Response

50
VS = 5V
45 FALLING EDGE G = +2
RL = 1kΩ
40 2.6V VIN = 100mV

35
SETTLING TIME (ns)

RISING EDGE
30
VOLTS

2.5V
25

20

15 2.4V

10 VS = 5V
RL = 1kΩ

01065-041
01065-038

5 G = +1 20mV/DIV

0
0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 50 60 70 80 90 100
OUTPUT VOLTAGE STEP TIME (ns)

Figure 38. Settling Time vs. VOUT

Figure 41. 100 mV Step Response

VS = 5V
G = –1 VS = 5V
RF = 1kΩ G = +2
RL = 1kΩ RF = RL = 1kΩ
VIN = 4V p-p
4.86V
VOLTS

VOLTS

2.43V

0V
0V
01065-039

01065-042

1V 2µs
2µs/DIV 1V/DIV

Figure 39. Output Swing Figure 42. Output Rail-to-Rail Swing

Rev. J | Page 12 of 20
Data Sheet AD8061/AD8062/AD8063
VS = 5V VS = 5V
G = +1 G = +2
RL = 1kΩ RL = RF = 1kΩ
VIN = 2V p-p

2.6V 4.5V
VOLTS

VOLTS
2.5V 2.5V

2.4V 0.5V

01065-043

01065-044
50mV/DIV
1V/DIV

0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
TIME (ns) TIME (ns)

Figure 43. 200 mV Step Response Figure 44. 2 V Step Response

Rev. J | Page 13 of 20
AD8061/AD8062/AD8063 Data Sheet

CIRCUIT DESCRIPTION
The AD8061/AD8062/AD8063 family is comprised of high –0.4
speed voltage feedback op amps. The high slew rate input stage –0.8
is a true, single-supply topology, capable of sensing signals at or
–1.2
below the minus supply rail. The rail-to-rail output stage can
pull within 30 mV of either supply rail when driving light loads –1.6

VOS (mV)
and within 0.3 V when driving 150 Ω. High speed perform- –2.0
ance is maintained at supply voltages as low as 2.7 V. –2.4

HEADROOM CONSIDERATIONS –2.8

These amplifiers are designed for use in low voltage systems. –3.2
To obtain optimum performance, it is useful to understand the

01065-045
–3.6
behavior of the amplifier as input and output signals approach
–4.0
the amplifier’s headroom limits. –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VCM (V)
The AD8061/AD8062/AD8063 input common-mode voltage
range extends from the negative supply voltage (actually 200 mV Figure 45. VOS vs. Common-Mode Voltage, VS = 5 V
below this), or ground for single-supply operation, to within 2

1.8 V of the positive supply voltage. Thus, at a gain of 2, the

AD8061/AD8062/AD8063 can provide full rail-to-rail output
0
swing for supply voltage as low as 3.6 V, assuming the input VCM = 3.0

signal swings from −VS (or ground) to +VS/2. At a gain of 3, VCM = 3.1
VCM = 3.2
the AD8061/AD8062/AD8063 can provide a rail-to-rail output –2
GAIN (dB)

VCM = 3.3
range down to 2.7 V total supply voltage. VCM = 3.4

Exceeding the headroom limit is not a concern for any inverting –4

gain on any supply voltage, as long as the reference voltage at

the amplifier’s positive input lies within the amplifier’s input –6
common-mode range.

01065-046
The input stage is the headroom limit for signals when the –8
0.1 1 10 100 1k 10k
amplifier is used in a gain of 1 for signals approaching the
FREQUENCY (MHz)
positive rail. Figure 45 shows a typical offset voltage vs. input
Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V
common-mode voltage for the AD8061/AD8062/AD8063
amplifier on a 5 V supply. Accurate dc performance is main- Higher frequency signals require more headroom than lower
tained from approximately 200 mV below the minus supply frequencies to maintain distortion performance. Figure 47
to within 1.8 V of the positive supply. For high speed signals, illustrates how the rising edge settling time for the amplifier
however, there are other considerations. Figure 46 shows −3 dB configured as a unity-gain follower stretches out as the top of
bandwidth vs. dc input voltage for a unity-gain follower. As a 1 V step input approaches and exceeds the specified input
the common-mode voltage approaches the positive supply, common-mode voltage limit.
the amplifier holds together well, but the bandwidth begins to For signals approaching the minus supply and inverting gain
drop at 1.9 V within +VS. and high positive gain configurations, the headroom limit is
This manifests itself in increased distortion or settling time. the output stage. The AD8061/AD8062/AD8063 amplifiers use
Figure 16 plots the distortion of a 1 V p-p signal with the a common emitter style output stage. This output stage
AD8061/AD8062/AD8063 amplifier used as a follower on maximizes the available output range, limited by the saturation
a 5 V supply vs. signal common-mode voltage. Distortion voltage of the output transistors. The saturation voltage
performance is maintained until the input signal center voltage increases with the drive current the output transistor is required
gets beyond 2.5 V, as the peak of the input sine wave begins to to supply, due to the output transistors’ collector resistance. The
run into the upper common-mode voltage limit. saturation voltage is estimated using the equation
VSAT = 25 mV + IO × 8 Ω
where:
IO is the output current.
8 Ω is a typical value for the output transistors’ collector
resistance.

Rev. J | Page 14 of 20
Data Sheet AD8061/AD8062/AD8063
3.6
3.7
3.4
3.5
3.2

OUTPUT VOLTAGE (V)

3.3
OUTPUT VOLTAGE (V)

3.0
2V TO 3V STEP 3.1 VOLTAGE STEP
FROM 2.4V TO 3.4V
2.8 2.1V TO 3.1V STEP
2.9
VOLTAGE STEP
2.6 2.2V TO 3.2V STEP
FROM 2.4V TO 3.6V
2.7
2.3V TO 3.3V STEP
2.4 VOLTAGE STEP
2.4V TO 3.4V STEP 2.5
FROM 2.4V TO 3.8V,
2.2 4V AND 5V

01065-048
2.3

01065-047
2.0
2.1
0 100 200 300 400 500 600
0 4 8 12 16 20 24 28 32
TIME (ns)
TIME (ns)

Figure 47. Output Rising Edge for 1 V Step at Figure 48. Pulse Response for G = 1 Follower,
Input Headroom Limits, G = 1, VS = 5 V, 0 V Input Step Overloading the Input Stage

As the saturation point of the output stage is approached, the Output

output signal shows increasing amounts of compression and Output overload recovery is typically within 40 ns after the
clipping. As in the input headroom case, the higher frequency amplifier’s input is brought to a nonoverloading value. Figure 49
signals require a bit more headroom than lower frequency shows output recovery transients for the amplifier recovering
signals. Figure 16, Figure 17, and Figure 18 illustrate this point, from a saturated output from the top and bottom supplies to a
plotting typical distortion vs. output amplitude and bias for point at midsupply.
gains of 2 and 5. 5.0
4.6
OVERLOAD BEHAVIOR AND RECOVERY OUTPUT VOLTAGE
4.2
INPUT AND OUTPUT VOLTAGE (V)

Input 3.8
5V TO 2.5V

The specified input common-mode voltage of the AD8061/ 3.4 OUTPUT VOLTAGE
0V TO 2.5V
AD8062/AD8063 is −200 mV below the negative supply to 3.0
2.6 INPUT VOLTAGE
within 1.8 V of the positive supply. Exceeding the top limit EDGES
2.2
results in lower bandwidth and increased settling time as seen R
1.8
in Figure 46 and Figure 47. Pushing the input voltage of a unity- 1.4
5V
R
gain follower beyond 1.6 V within the positive supply leads to 1.0 VIN
the behavior shown in Figure 48—an increasing amount of 0.6 – 2.5V VO
–

01065-049
output error and much increased settling time. Recovery time 0.2
from input voltages 1.6 V or closer to the positive supply is –0.2
0 10 20 30 40 50 60 70
approximately 35 ns, which is limited by the settling artifacts
TIME (ns)
caused by transistors in the input stage coming out of saturation.
Figure 49. Overload Recovery, G = −1, VS = 5 V
The AD8061/AD8062/AD8063 family does not exhibit phase
reversal, even for input voltages beyond the voltage supply rails.
Going more than 0.6 V beyond the power supplies turns on
protection diodes at the input stage, which greatly increases the
current draw of the device.

Rev. J | Page 15 of 20
AD8061/AD8062/AD8063 Data Sheet
CAPACITIVE LOAD DRIVE DISABLE OPERATION
The AD8061/AD8062/AD8063 family is optimized for The internal circuit for the AD8063 disable function is shown
bandwidth and speed, not for driving capacitive loads. Output in Figure 52. When the DISABLE node is pulled below 2 V
capacitance creates a pole in the amplifier’s feedback path, from the positive supply, the supply current decreases from
leading to excessive peaking and potential oscillation. If dealing typically 6.5 mA to under 400 µA, and the AD8063 output
with load capacitance is a requirement of the application, the enters a high impedance state. If the DISABLE node is not
two strategies to consider are as follows: connected and allowed to float, the AD8063 stays biased at
Use a small resistor in series with the amplifier’s output and the full power.
load capacitance. VCC

Reduce the bandwidth of the amplifier’s feedback loop by

increasing the overall noise gain. 2V
TO AMPLIFIER
Figure 50 shows a unity-gain follower using the series resistor BIAS
DISABLE
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.

01065-052
VEE

RSERIES Figure 52. Disable Circuit of the AD8063

AD8061 VO
Figure 34 shows the AD8063 supply current vs. DISABLE
01065-050

CLOAD
VIN
voltage. Figure 35 plots the output seen when the AD8063 input
Figure 50. Series Resistor Isolating Capacitive Load is driven with a 10 MHz sine wave, and DISABLE is toggled
Voltage feedback amplifiers like those in the AD8061/AD8062/ from 0 V to 5 V, illustrating the part’s turn-on and turn-off
AD8063 family are able to drive more capacitive load without time. Figure 33 shows the input/output isolation response with
excessive peaking when used in higher gain configurations the AD8063 shut off.
because the increased noise gain reduces the bandwidth of the BOARD LAYOUT CONSIDERATIONS
overall feedback loop. Figure 51 plots the capacitance that
Maintaining the high speed performance of the AD8061/AD8062/
produces 30% overshoot vs. noise gain for a typical amplifier.
AD8063 family requires the use of high speed board layout
10k
techniques and low parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
CAPACITIVE LOAD (pF)

RS = 4.7
1k path. Remove the ground plane near the package to reduce
parasitic capacitance.
Proper bypassing is critical. Use a ceramic 0.1 µF chip capacitor
RS = 0 to bypass both supplies. Locate the chip capacitor within 3 mm
100
of each power pin. Additionally, connect in parallel a 4.7 µF to
10 µF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
01065-051

10
Minimizing parasitic capacitance at the amplifier’s inverting
1 2 3 4 5 input pin is very important. Locate the feedback resistor close to
CLOSED-LOOP GAIN
the inverting input pin. The value of the feedback resistor may
Figure 51. Capacitive Load vs. Closed-Loop Gain come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.

Rev. J | Page 16 of 20
Data Sheet AD8061/AD8062/AD8063

APPLICATIONS INFORMATION
SINGLE-SUPPLY SYNC STRIPPER The circuit can be modified to provide the sync stripping
function for such a waveform. Instead of connecting RG to
When a video signal contains synchronization pulses, it is ground, connect it to a dc voltage that is two times the black
sometimes desirable to remove them prior to performing level of the input signal. The gain from the noninverting input
certain operations. In the case of analog-to-digital conversion, to the output is 2, which means the black level is amplified by 2
the sync pulses consume some of the dynamic range, so to the output. However, the gain through RG is −1 to the output.
removing them increases the converter’s available dynamic It takes a dc level of twice the input black level to shift the black
range for the video information. level to ground at the output. When this occurs, the sync is
Figure 53 shows a basic circuit for creating a sync stripper using stripped, and the active video is passed as in the ground-
the AD8061 powered by a single supply. When the negative referenced case.
supply is at ground potential, the lowest potential to which the RED
output can go is ground. This feature is exploited to create a DAC
75Ω 75Ω
waveform whose lowest amplitude is the black level of the video GREEN
MONITOR
#1
and does not include the sync level. DAC
75Ω 75Ω

3V BLUE
DAC
75Ω 75Ω
0.1µF 10µF
3 7
VIDEO IN 75Ω VIDEO OUT 1kΩ
6
75Ω AD8061
2 3V
75Ω
4 RF
1kΩ
0.1µF 10µF
7
01065-053

RG PIN NUMBERS ARE 1kΩ 2

1kΩ FOR 8-LEAD PACKAGE
6 75Ω RED
AD8061
3 75Ω
Figure 53. Single 3 V Sync Stripper Using AD8061
4

In this case, the input video signal has its black level at ground, 1kΩ

so it comes out at ground at the input. Because the sync level is 3V MONITOR
#2
below the black level, it does not show up at the output. However,
0.1µF 10µF
all of the active video portion of the waveform is amplified by a
8
gain of 2 and then normalized to unity gain by the back-
1kΩ 2
terminated transmission line. Figure 54 is an oscilloscope plot 1 75Ω GREEN
AD8062
of the input and output waveforms. 3 75Ω

5
7 75Ω BLUE
1 1kΩ AD8062
75Ω
6
INPUT

01065-055
4
1kΩ

Figure 55. RGB Cable Driver Using AD8061 and AD8062

2
RGB AMPLIFIER
OUTPUT Most RGB graphics signals are created by video DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and the voltage of the video
01065-054

500mV 10µs is also zero. Before the availability of high speed rail-to-rail op
amps, it was essential that an amplifier have a negative supply
Figure 54. Input and Output Waveforms for a Single-Supply to amplify such a signal. Such an amplifier is necessary if one
Video Sync Stripper Using an AD8061
wants to drive a second monitor from the same DAC outputs.
Some video signals with sync are derived from single-supply
However, high speed, rail-to-rail output amplifiers like the
devices, such as video DACs. These signals can contain sync,
AD8061 and AD8062 accept ground-level input signals and
but the whole waveform is positive, and the black level is not
output ground-level signals. They are used as RGB signal
at ground but at a positive voltage.
amplifiers. A combination of the AD8061 (single) and the
AD8062 (dual) amplifies the three video channels of an RGB
system. Figure 55 shows a circuit that performs this function.

Rev. J | Page 17 of 20
AD8061/AD8062/AD8063 Data Sheet
MULTIPLEXER The select signal and the output waveforms for this circuit are
The AD8063 has a disable pin used to power down the ampli- shown in Figure 57. For synchronization clarity, two different
fier to save power or to create a mux circuit. If two (or more) frequency synthesizers, whose time bases are locked to each
AD8063 outputs are connected together, and only one is enabled, other, generate the signals.
then only the signal of the enabled amplifier will appear at the 2µs
output. This configuration is used to select from various input
signal sources. Additionally, the same input signal is applied to
OUTPUT
different gain stages, or differently tuned filters, to make a gain-
step amplifier or a selectable frequency amplifier.
Figure 56 shows a schematic of two AD8063 devices used to
create a mux that selects between two inputs. One of these is a
1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave. SELECT
+4V

01065-057
0.1µF 10µF
1V 2V
1
TIME 49.9Ω AD8063
BASE Figure 57. AD8063 Mux Output
1V p-p OUT
3MHz
0.1µF 10µF

–4V
1kΩ

1kΩ 49.9Ω VOUT

+4V 49.9Ω

0.1µF 10µF

1
2V p-p 49.9Ω AD8063
1MHz
TIME
BASE
IN 0.1µF 10µF

–4V
1kΩ

1kΩ
01065-056

HCO4
SELECT

Figure 56. Two-to-One Multiplexer Using Two AD8063s

Rev. J | Page 18 of 20
Data Sheet AD8061/AD8062/AD8063

OUTLINE DIMENSIONS
3.00
2.90
2.80

5 4 3.00 5.00 (0.1968)

1.70
1.60 2.80 4.80 (0.1890)
1.50 2.60
1 2 3
8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4
0.95 BSC
1.90
BSC
1.27 (0.0500) 0.50 (0.0196)
1.30 BSC 45°
1.75 (0.0688) 0.25 (0.0099)
1.15 1.35 (0.0532)
0.25 (0.0098) 8°
0.90
1.45 MAX 0.20 MAX 0.10 (0.0040) 0°
0.95 MIN 0.08 MIN COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.55 0.31 (0.0122) 0.25 (0.0098)
0.15 MAX 10° SEATING 0.40 (0.0157)
0.45 PLANE 0.17 (0.0067)
0.05 MIN SEATING 5° 0.60
0.50 MAX PLANE BSC 0.35
0.35 MIN 0°
COMPLIANT TO JEDEC STANDARDS MS-012-AA

11-01-2010-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

012407-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
COMPLIANT TO JEDEC STANDARDS MO-178-AA REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 58. 5-Lead Small Outline Transistor Package [SOT-23] Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
(RJ-5) Narrow Body (R-8)
Dimensions shown in millimeters Dimensions shown in millimeters and (inches)

3.00
2.90
2.80
3.20
3.00
2.80
6 5 4 3.00
1.70
1.60 2.80
1.50 2.60
1 2 3
8 5 5.15
3.20 4.90
PIN 1 3.00 4.65
INDICATOR 2.80 1
4
0.95 BSC
1.90 PIN 1
BSC IDENTIFIER
1.30
0.65 BSC
1.15
0.90
1.45 MAX 0.20 MAX 0.95 15° MAX
0.95 MIN 0.08 MIN 0.85 1.10 MAX
0.55 0.75
0.15 MAX 10° 0.45 0.80
0.05 MIN SEATING 0.60 0.15 6° 0.23
0.50 MAX 4° 0.35 0.40 0.55
PLANE BSC 0.05 0.09
0.30 MIN 0° 0.25 0° 0.40
COPLANARITY
10-07-2009-B
12-16-2008-A

0.10

COMPLIANT TO JEDEC STANDARDS MO-178-AB COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 60. 6-Lead Small Outline Transistor Package [SOT-23] Figure 61. 8-Lead Mini Small Outline Package [MSOP]
(RJ-6) (RM-8)
Dimensions shown in millimeters Dimensions shown in millimeters

Rev. J | Page 19 of 20
AD8061/AD8062/AD8063 Data Sheet
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option Branding
AD8061AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8061ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD8061ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8061ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8061ART-R2 −40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5 HGA
AD8061ART-REEL7 −40°C to +85°C 5-Lead SOT-23, 7-Inch Tape and Reel RJ-5 HGA
AD8061ARTZ-R2 −40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5 H0D 2
AD8061ARTZ-REEL −40°C to +85°C 5-Lead SOT-23, 13-Inch Tape and Reel RJ-5 H0D2
AD8061ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23, 7-Inch Tape and Reel RJ-5 H0D2
AD8061AR-EBZ Evaluation Board for 8-Lead SOIC_N
AD8061ART-EBZ Evaluation Board for 5-Lead SOT-23
AD8062AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8062ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD8062ARZ-RL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8062ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8062ARM −40°C to +85°C 8-Lead MSOP RM-8 HCA
AD8062ARMZ −40°C to +85°C 8-Lead MSOP RM-8 #HCA
AD8062ARMZ-RL −40°C to +85°C 8-Lead MSOP, 13-Inch Tape and Reel RM-8 #HCA
AD8062ARMZ-R7 –40°C to +85°C 8-Lead MSOP, 7-Inch Tape and Reel RM-8 #HCA
AD8062AR-EBZ Evaluation Board for 8-Lead SOIC_N
AD8062ARM-EBZ Evaluation Board for 8-Lead MSOP
AD8063ARZ –40°C to +85°C 8-Lead SOIC_N R-8
AD8063ARZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8063ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8063ART-R2 –40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6 HHA
AD8063ART-REEL7 –40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6 HHA
AD8063ARTZ-R2 –40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6 H0E 3
AD8063ARTZ-REEL –40°C to +85°C 6-Lead SOT-23, 13-Inch Tape and Reel RJ-6 H0E3
AD8063ARTZ-REEL7 –40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6 H0E3
AD8063AR-EBZ Evaluation Board for 8-Lead SOIC_N
AD8063ART-EBZ Evaluation Board for 6-Lead SOT-23
1
Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.
2
New branding after data code 0542, previously branded HGA.
3
New branding after data code 0542, previously branded HHA.

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