Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

UNIT 3: CMOS LOGIC STRUCTURES

Introduction:
The various applications that require logic structures have different optimizations. Some of the
circuit needs fast response, some slow but very precise response; others may need large
functionality in a small space and so on. The CMOS logic structures can be implemented in
alternate ways to get specific optimization. These optimizations are specific because of the
tradeoff between the n numbers of design parameters.

CMOS Complementary Logic Structure

 CMOS logic structures of NAND & NOR has been studied in previous unit. They were
ratioed logic i.e. they have fixed ratio of sizes for the n and the p gates.
 It is possible to have ratio less logic by varying the ratio of sizes which is useful in gate
arrays and sea of gates. Variable ratios allow us to vary the threshold and speed.
 If all the gates are of the same size the circuit is likely to function more correctly.
 Apart from this the supply voltage can be increased to get better noise immunity. The
increase in voltage must be done within a safety margin of the source -drain break down.
Supply voltage can be decreased for reduced power dissipation and also meet the
constraints of the supply voltage. Sometimes even power down with low power
dissipation is required. For all these needs an on chip voltage regulator is required which
may call for additional space requirement.
 A CMOS requires an n-block and a p-block for completion of the logic.
 For an n input logic, 2n gates are required.

BICMOS Logic Structure

 The CMOS logic structures have low output drive capability. If bipolar transistors are
used at the output the capability can be enhanced.
 Bipolar transistors are current controlled devices and produces larger output current then
the CMOS transistors. This combined logic is called BICMOS logic.
 We can have the bipolar transistors both for pull up and pull down or only for pull up as
shown in the figures 3.1 and 3.2 below.
 The figure 3.1 shows a CMOS NAND gate with NPN transistors at both level.

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

Figure 3.1: NAND with two NPN drivers

 P1 and P2 enhance the souring of current into the base of T1.
 N1 and N2 enhance the sinking of current into the base of T2.
 N3 is utilized to clamp the pull down, when the output is high. By means of these
arrangements, T1 and T2 are made to change states rapidly, thus increasing the operating
speed.
This design shown in figure 3.1 is basically used for speed enhancing in highly automated
designs like gate arrays. Since the area occupied by the bipolar transistors is more and if the aim
in the design is to match the pull up and pull down speeds then we can have a transistor only in
the pull up circuit because p devices are slower as shown in the figure 3.2.

Figure 3.2: NAND with one NPN in pull up

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

Figure 3.3: NOT with two NPN drivers

PSEUDO NMOS Logic Structure

 Pseudo logic structure consists of the pull up circuit being replaced by a single pull up
PMOS whose gate is permanently grounded. This actually means that PMOS is all the
time on.
 For an n input logic we have only n+1 gates.
 This technology is equivalent to the depletion mode type and preceded the CMOS
technology and hence the name pseudo.
 The two sections of the device are now called as load and driver.
 The ßn/ßp (ßdriver/ßload) has to be selected such that sufficient gain is achieved to get
consistent pull up and pull down levels.

Figure 3.3: Pseudo NMOS

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

Advantages
 The gate capacitance of CMOS logic is two unit gate but for psuedo logic it is only one
gate unit.
 Number of transistors per input is reduced area is reduced drastically.
Disadvantage
 PMOS is always on, static power dissipation occurs whenever the NMOS is on.
Example:

Figure 3.4: Example for Pseudo NMOS

The alternate methods of Pseudo NMOS are as show below
a. Multi drain logic
One way of implementing pseudo NMOS is to use multidrain logic. It represents a merged
transistor kind of implementation. The gates are combined in an open drain manner, which is
useful in some automated circuits shown in figure 3.5.

Figure 3.5: Multi drain logic

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

b. Ganged Logic
 The inputs are separately connected but the output is connected to a common terminal.
 The logic depends on the pull up and pull down ratio.
 In the circuit shown in figure 3.6, when ratio is equal to unity then the circuit becomes
destructive in nature. The output is ‘1’ when input is “000” and output is ‘0’ when input
is ”111”,but for any other input conditions Vdd gets shorted to Vss.
 When the ratio is greater than unity, the pull down transistor will have higher sinking
ability and thus the circuit works as a NOR gate.
 When the ratio is less than unity, each pull down transistor has a lesser sinking ability and
output will go low only when all the pull down transistors are switched on. Hence the
circuit works as a NAND gates.
 Thus ganged CMOS can used as NAND or NOR logic based on the ratio.

Figure 3.6: Ganged logic

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

Clocked CMOS Logic (C2MOS) Logic Structure

This logic is realized by including clock into regular CMOS circuit. An example circuit is shown
below.

Figure 3.7: Example for C2MOS

Advantage
The pull down transistors operate at a lower Vds, due to additional n-transistor.
Disadvantage
The number of transistors increased to 2n+2.

Dynamic CMOS Logic Structure

 This logic structure enhances the speed of the pull up device by pre-charging the output
node to Vdd.
 The working of the device is split into two stages pre-charge stage and evaluate stage for
which we need a clock. Hence it is called as dynamic logic.

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

 The output node is pre-charged to Vdd by the PMOS and is discharged conditionally
through the NMOS.
 When the clock is low the pre-charge phase occurs and clock is high evaluate phase
occurs. The path to Vss is closed by the NMOS i.e the ground switch.
 The pull up time is improved because of the active PMOS which is already pre-charged.
But the pull down time increases because of the ground switch.
 Alternatively you can also have a p block and pre-charge the n transistor to Vss.

Figure 3.8: Dynamic CMOS Logic

Advantages
 This circuit does not have static power dissipation.
 It contains n+2 transistor for n inputs.
 The input capacitance is one unit each.
 The CMOS has higher speed as well as lower floor area.

Disadvantages
 Inputs have to change during the pre-charge stage and must be stable during the evaluate.
If this condition cannot occur then charge redistribution corrupts the output node.
 A simple single dynamic logic cannot be cascaded. The reason discussed below.

Assume inputs A=B=C=1

Figure 3.9: Cascading of 2 NAND gates

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

According to the given inputs V01=0, and V02=1, but the second output will not be in the
excepted state.V01 will not go low until its capacitance is completely discharged. Hence, there
will be a small propagation delay td but as C=1, V02 will go low.it will not go high until next pre-
charge phase. Thus we have erroneous output.

CMOS Domino Logic

Figure 3.10: CMOS domino logic.

The disadvantage associated with the dynamic CMOS is over come in this logic. In this we are
able to cascade logic blocks with the help of a single clock. The pre-charge and the evaluate
phases retained as they were. The change required is to add a buffer at the end of each stage.

Figure 3.11: Example CMOS domino logic.

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

The logic works in the following manner, assume A=B=C=1 and expected output is Z=1. When
the clk=0, i.e. during the pre-charge stage the output of the dynamic logic is high and the output
of the buffer is low. Since the subsequent stages are fed from the buffer they are all off in the
pre-charge stage. When the gate is evaluated in the next phase, the output conditionally goes low
and the output of the buffer goes high. The subsequent gates make a transition from high to low.
Hence in one clock cycle the cascaded logic makes only one transition from 1 to 0 and buffer
makes a transition from 0 to 1.In effect we can say that the cascaded logic falls like a line of
dominos, and hence the name.
The advantage is that any number of logic blocks can be cascaded provided the sequence can be
evaluated in a single clock cycle. Single clock can be used to pre-charge and evaluate all the
logic in a block.
The limitation is that each stage must be buffered and only non- inverted structures are possible.
Care must be taken to ensure design is correct.

Advantages

 Use smaller gates, achieve higher speed and get a smooth operation.

CMOS NP Domino Logic Structure (Zipper CMOS)

 This is a refinement of the domino CMOS structure.
 In the figure, first stage is pre-charged high, the second stage is pre-charged low and the
third stage is pre-charged high.
 The subsequent blocks are complementary networks, there is no need of an inverter in
between, and thus there is a reduction in the parasitic capacitances.

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

Figure 3.12: CMOS NP domino logic.

Figure 3.13: Altered CMOS NP domino logic.

Advantages

 No charge leakage and charge sharing problems.

 Higher speed.

Cascaded Voltage Switch Logic (CVSL)
 This is a special type of logic structure which contains two cross coupled load devices.
 The structure delivers both true and complementary outputs.
 It is also called as double rail logic.

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

 The circuit will not function unless both the pull down networks are connected.

Figure 3.14: Cascaded voltage switch logic.

The procedure for writing the circuits is as follows

 Write down the expression for Q and Qbar and simplify them.
 AND in the expression corresponds to series connection and OR corresponds to parallel
connection of n-devices.
 Write the cross coupled P-MOSFETS as pull-up and complete the pull down by writing
N-MOSFET.
 Write the circuit of Q below Qbar and the circuit of Qbar below Q.

Examples on CVSL
1) AND/NAND

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

2) OR/NOR

3) XOR/XNOR

4)

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Fundamentals of CMOS VLSI Unit-3 CMOS Logic Structures

Dynamic CVSL Structure

The static CVSL can be made dynamic with inclusion of clock shown in figure 3.15.

Figure 3.15: Dynamic Cascaded voltage switch logic.

The inverters are added here as part of the domino connections to keep the pre-charged
output conditions at logic low.
The network for the particular output has to be written below the respective output itself i.e.
the circuit for Q has to be written below Q and same for Qbar also.
Example on Dynamic CVSL
AND/NAND

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