VLSI Design & Testing

(BEC602)
Module 4
CMOS Circuit and Logic Design

Introduction, CMOS Logic structures, CMOS Complementary logic,

Pseudo n-MOS logic, Dynamic CMOS logic, Clocked CMOS Logic, Cascade Voltage Switch logic, Pass
transistor Logic, Electrical and Physical design of Logic gates, The inverter, NAND and NOR gates, Body
effect, Physical Layout of Logic gates, Input output Pads.

Text Book: Principals of CMOS VLSI Design A System approach Neil H E Weste and Kamran Eshraghain. Wisley Publishing
company. [Text 1: 5.1,5.2,5.2.1, , 5.2.2, 5.2.3, 5.2.4, 5.2.6, 5.2.8, 5.3,5.3.1,5.3.2, 5.3.4 ,5.3.8,5.5]
 Introduction
• Two phases of design are:
1 circuit (structural) design
2 layout (physical) design.

CMOS logic structures

➢ The area taken by a fully complementary static CMOS gate may be:
➢ greater than that required,
➢ the speed may be too slow,
➢ or the function may just not be implementable as a purely complementary structure.
➢ In these cases, it is desirable to implement smaller and faster gates at a cost of increased design and
operational complexity and, possibly, decreased circuit stability.
➢ There are a number of alternate CMOS logic structures that can be used.
 CMOS complementary logic
• The complementary CMOS inverter,
NAND, and NOR gates are shown in
Fig. 5.1.
• All complementary gates may be
designed as ratioless circuits.
• That is, if all transistors are the same
size the circuit will function
correctly.
• In addition, a complex gate that
implements the function
Z = (A.B) + C.(D + E) is shown.
 Pseudo-nMOS logic
• A pseudo-nMOS gate is shown in Fig.
• Here, the load device is a single p-transistor,
with the gate connected to Vss.
• This is equivalent to a conventional nMOS
gate except that the depletion or
enhancement nMOS load is replaced by a p-
device.
• As with nMOS, the gain ratio of the p-
transistor load to n-driver transistors
ßload/ßdriver has to be selected to yield
sufficient gain to generate consistent logic
levels.
• The main problem with the gate (in common with conventional nMOS) is the
static power dissipation that occurs whenever the pull-down chain is turned on.
• As the p load is always turned on, when the n pull-down is on, current flows in
the gate structure.
• There are n + 1 transistors in an n input pseudo-nMOS gate.
• In a complementary gate, the capacitive load on each input is at least two unit
gate loads (the gate input capacitance of a unit sized transistor).
• In this type of gate, the minimum load can be one unit gate load, as a result of
using only one transistor for each term of the input function.
• One possible advantage of the pMOS load is that it does not suffer from bodv
effect as the nMOS depletion load does.
 Dynamic CMOS logic
• A basic dynamic CMOS gate is shown in Fig.
• It consists of an n-transistor logic structure whose output node is precharged to
VDD by a p-transistor (precharge) and conditionally discharged by an n-transistor
(evaluate) connected to Vss.
• (Alternatively, an n-transistor precharge to Vss and p-transistor discharge to VDD
and p logic block may be used.)
• Φ is a single phase clock.
• For the former case, the precharge phase occurs when Φ = O.
• The path to the Vss supply is closed via the n-transistor "ground switch'
during
Φ = 1.
• The input capacitance of this gate is the same as the pseudo-nMOS
gate.
• The pull-up time is improved by virtue of the active switch but -the
pull-down time is increased due to the ground switch.
• A number of problems are manifest in this structure.
• Firstly, the inputs can only change during the precharge phase.
• If this condition is not met, charge redistribution effects can corrupt
the output node voltage.
• Simple single phase dynamic CMOS gates cannot be cascaded.
• For instance, consider the circuit in Fig below.
• When the gates are precharged, the output nodes are charged to VDD.
• During the evaluate phase, the output of the first gate will conditionally discharge.
• However, some delay will be incurred due to the finite pull-down time.
• Thus the precharged node can discharge the output node of the following gate before
the first gate is correctly evaluated.
• Improvements on this structure use the forms of two and four phase logic.
• These gates add a sample and hold clock phase to the precharge and evaluate cycles.
• Fig. 5.5a shows one version of a gate implemented using the clock relationships shown in Fig. 5.5b.
• The composite clocks Φ12 and Φ23 are used in this example.
• During Φ1 node PZ is precharged, while node Z is held at its previous value.
• When Φ2 is true, node PZ remains precharged and, in addition, the transmission gate turns on, thus precharging
node Z.
• When Φ3 is asserted, the gate evaluates and node PZ conditionally discharges.
• Node Z follows node PZ as the transmission gate remains on.
• Finally, when Φ4 is true, node Z will be held in the evaluated state.
• The state of node PZ is immaterial.
• There are four types of gates
characterized by the phase in which
evaluation occurs.
• When using such logic gates, they
must be used in the appropriate
sequence.
• The allowable connections between
types are shown in Fig. 5.6
• Note that four levels of logic may be
evaluated per hit time.
• Alternatively, a 2-phase logic scheme
may be employed by using type 4
gates and type 2 gates or type 1 gates
and type 3 gates.
An alternate 4-phase structure is shown in Fig. 5.7a.
The clocking waveforms are shown in Fig. 5.7b.
This structure has the intergate restrictions shown in Fig. 5.8.
This gate type is more restrictive than the previous gate, but the circuit is
simpler, the number of clocks is reduced, and the layout would be smaller.
Similarly, a 2-phase system could employ gate types 2 and 4.
The number of transistors required for such logic gates is either n + 4 or n + 3
for an n-input gate.
A problem that occurs with such gates is that the clock frequency must be long
enough to allow for the slowest gate to evaluate.
Thus fast gates tend to evaluate quickly and the remainder of the cycle is "dead
time."

Fig 5.8 Allowable gate

interconnections –type B
 Clocked CMOS logic (C2MOS)
• A clocked CMOS gate is shown in Fig. 5.9.
• This form of logic was originally used to build low power
dissipation CMOS logic.
• The reasons for the reduced dynamic power dissipation
stem mainly from metal gate CMOS layout considerations.
• The main use of such logic structures at this time is to form
clocked structures that incorporate latches or interface with
other dynamic forms of logic.
• The gates have the same input capacitance as regular
complementary gates but larger rise and fall times due to
the series clocking transistors.
 Cascade voltage switch logic (CVSL)
• It is a differential style of logic requiring both true and complement
signals to be routed to gates.
• Two complementary nMOS switch structures are constructed and then
connected to a pair of cross-coupled p pull-up transistors.
• When the inputs switch, nodes Q and Q are either pulled high or low.
• Positive feedback applied to the p pull-ups causes the gate to switch.
• The logic trees may be further minimized from the full differential form
using logic minimization algorithms.
• This version, which might be termed a "static" CVSL gate, is slower than
a conventional complementary gate employing a p-tree and n-tree
• 5.11b shows the implementation of the example gate. Note that this is
not a very efficient implementation of this gate.
• Further refinement leads to a clocked version of the CVSL gate (Fig.
5.11c).
• This is really just two "domino" gates operating on true and
complement inputs with a minimized logic tree.
• The advantage of this style of logic over domino logic is simply the
ability to generate any logic expression, making it a complete logic
family.
• This is achieved at the expense of the extra routing, active area, and
complexity associated with dealing with double rail logic.
• However, the ability to generate any logic function is of advantage
where automated logic synthesis is required.
• A four-way XOR gate is shown in Fig. 5.11d
• Common advantages of the dynamic logic styles are as follows:
• Smaller area than fully static gates.
• Smaller parasitic capacitances, hence higher speed.
• Glitch-free operation if designed carefully.
 Pass Transistor Logic
• A popular use of pass transistor logic is the function unit used in ALU.
• The nMOS structure is shown in Fig a below.
• In CMOS this structure is replicated as shown in Fig b by using full transmission
gate for each original nMOS.
• A more realizable circuit is seen in Fig c.
• This alleviates many direct n- to p- transistor connections.
• A dynamic version is shown in Fig d.
• nMOS has fastest fall time while pMOS has fastest rise time.
• Using larger p transistors decreases rise time but increases fall time.
• An alternative approach to the dynamic version is to include a buffer, which is fed
back to the p transistor pull up.
• Formal methods for deriving pass transistor logic have
been presented for nMOS.
• They are based on model shown in Fig 5.14
• where a set of variables control a pass transistor
network to which pass variables are applied.
• In the case of an exclusive-or gate, the truth table is
shown in Table 5.1
• The pass function column refers to the input variables,
which could be passed to the output to achieve the
function
• A modified Karnaugh map may be drawn for the pass functions, as shown in
Table 5.2.
• The input variables are grouped to appropriately steer the pass variables to the
output under the influence of the control variables.
• In this case, B is a pass variable x variable under the control
• under the control of A, and B is a pass x.
• Note that groupings of A.
• The resulting structure is shown in Fig. 5.15.
 Electrical and physical design of logic gates
The inverter
• Schematic to symbolic layout conversion for inverter is shown in fig 5.16 below.
• In a schematic, lines drawn between device terminals represent connections.
• Any nonplanar situation is dealt with by simply crossing two lines (i.e., the connection
between the drain of the n-transistor and the drain of the p-transistor).
• However, in a physical layout, we have to concern ourselves with the interaction of
physically different interconnection layers.

Fig 5.16
• We know from our consideration of the fabrication process, that the source and
drain of the n-transistor are n-diffusion regions, while the p.transistor uses p-
diffusion regions for these connections.
• Additionally, in a bulk CMOS process. we cannot make a direct connection from
n-diffusion to p-diffusion.
• Thus we have to implement the simple inter drain connection in the structural
domain, as at least one wire and two contacts in the phvsical domain.
• Assuming that the process does not have buried contacts, this connection has to
be in metal.
• Substituting our layout symbols, the partial inverter shown in Fig. 5.16b results.
• Finally, we must add substrate contacts that are not implied in the schematic. The
resulting symbolic schematic is shown in Fig. 5.16d.
• Converting this to a symbolic layout yields the arrangement shown in Fig. 5.17a.
• An alternative layout is shown in Fig. 5.17b, where the transistors are aligned
horizontally.
• For instance, if a metal line has to be passed through the middle of the cell from
the left end of the cell to the right end, the lavout shown in Fig. 5.17c could be
used.
• Here, horizontal metal straps connect to a vertical polysilicon line, which in turn
connects the drains of the transistors.
• Alternatively, if a metal line is to be passed from left to right at the top or bottom
of the cell, the power and ground connections to the transistors may be made in
the appropriate diffusion layer (Fig. 5.17d).
• In the case of the vertical polysilicon drain connection, an extra connection
resistance is incurred.
• In addition, a slight extra capacitance may be incurred.
• Alternatively, the inverter layout may be reconstructed to use vertical oriented
transistors, as shown in Fig. 5.17e.
 Paralleled Inverter layouts
• A large inverter may be constructed from many smaller inverters connected in
parallel. This is svmbolically shown in Fig. 5.18a.
• Placing transistors back to back (Fig. 5.18b) yields a more optimum drain
capacitance due to the merged diffusion regions.
• This results from the fact that the drain area does not increase in size much but
the gain of transistors (P) is doubled.
• A further reduction in drain capacitance is achieved by using the star connection
shown in Fig. 5.18c.
 5.3.2 NAND and NOR gates
• Similar reasoning can be applied to converting the 2-input NAND schematic to a
layout.
• Fig. 5.19a shows a direct translation of the schematic.
• By orienting the transistors horizontally, the layout in Fig. 5.19b is possible.
• Note that in case of NAND gate, the latter layout is much cleaner (and smaller).
 NOR Gate
• The 2-input NOR gate symbolic layout is shown in Fig. 5.20a.
• The alternative layout is shown in Fig. 5.20b.
• The latter connection, in common with paralleled inverters, has less drain area
connected to the output.
• This results in a faster gate.
 5.3.4 Body effect
• Body effect is the term given to the modification of the threshold voltage Vt with
a voltage difference between source and substrate.
• Specifically, , where ϒ is a constant, Vsb is the voltage between
source and substrate, and ΔVt is the change in threshold voltage.
• For instance, in the multiple NAND gate shown in Fig. 5.24a, the n-transistor at
the output will switch slower if the source potential of this transistor is not the
same as the substrate.
• Fig. 5.24b illustrates how this could occur.
• The n-transistors with inputs A— C are initially off (VgsA=VgsB=VgsC=0).
• The n-transistor with input D is turned on (Vgsn = VDD ) and then off (VgsD = O).
• This action charges the capacitance (C1) at the source of n-transistor-D (VsbD≠0).
• If all the inputs are then set to a HIGH level (VgsA=VgsB=VgsC=VgsD= VDD), the source
of D will instantaneously be at VDD-Vtn.
• Thus n-transistors with gate signals A—C have to discharge this node to turn on
the n-transistor with D on the gate.
• In particular, the fall time of this gate will be slower than that predicted by the
approximations for the series connected transistors.
• To minimize this effect, gate design should minimize "internal" node capacitance
and take into account the relative body effect of the two types of transistors.
• If, for instance, the relative impact of the n-transistor body effect is worse than
that for the p-transistors, then NOR structures might be preferred.
• As the body effect is essentially a dynamic problem involving the charging of
parasitic capacitances, we can use the natural time sequencing of signals to offset
the body effect.
• The first strategy is to place the transistors with the latest arriving signals nearest
the output of a gate.
• The early signals, in effect "discharge" internal nodes and the late arriving signals
have to switch transistors with minimum body effect.
• The other strategy is to minimize the capacitance of internal nodes.
• Thus a diffusion wire would be used at the output of a gate rather than on some
internal node.
• Connections on internal nodes should be completed in metal or, if buried
contacts are allowed, polysilicon

Fig 5.24 Body Effect in a multiple input gate

 5.3.8 Physical layout of logic gates
• All complementary gates may be using a single row of n-transistors above or
below a single row of p-transistors, aligned at common gate connections.
• Most "simple" gates may be designed using an unbroken row of transistors in
which abutting source-drain connections are made.
• This is sometimes called the "line of diffusion" rule, referring to the fact that the
transistors form a line of diffusion intersected by polysilicon gate connections.
• Techniques for automatically designing such gates:
• The CMOS circuit is converted to a graph where
• 1) the vertices in the graph are the source/drain connections and
• 2) the edges in the graph are transistors that connect particular source-drain
vertices.
• Two graphs, one for the n-logic tree and one for p-logic tree.
• Fig 5.27 shows an example of graph transformation.
• The connection of edges in the graphs mirror the series-parallel connection of the
transistors.
• Each edge is named with the gate signal name for that particular transistor.
• The graphs are dual of each other as p- and n- are dual.
• If there exists a sequence of edges( containing all edges) in the p- and n- graph that
have identical labeling, then gate may be designed with no breaks, this is Euler path.
• Main points in the algorithm are:

• In Fig 5.28a, the original graph with a possible Euler path is shown.
• The sequence of gate signal in Euler path is (A,B,C,D).
• To complete a layout, the transistors are arranged in the ordering of labeling, n-
and p- transistors are in parallel rows as shown in fig 5.28b.
• Vertical polysilicon lines complete gate connection.
• Metal routing wires complete layout.
 Complementary XNOR gate
• The schematic of XNOR is shown in Fig 5.29a.
• 2 possible layouts are shown in fig 5.29 b and c.
• The layout shown in Fig. 5.29b uses the single row of n- and p-transistors, with a
break, while that in Fig. 5.29c uses a stacked layout.
• The selection of the styles would depend on the overall layout - whether a short,
fat, or-long thin cell was needed.
• Note that the gate segments that are maximally connected to the supply and
ground rails are placed adjacent to these signals.
• An automatic approach to achieve this style of layout that uses a graph-theoretic
approach has been proposed.
• The approach is based on the use of interval graphs to
optimal!y place transistors on vertical polysilicon lines
in a gate matrix style.
• Power and ground run at the top and bottom of the
cell.
• The approach is summarized in Fig. 5.30.
• Transistors are grouped in strips to allow maximum
source/drain connection by abutment. To achieve
better grouping, polysilicon columns are allowed to
interchange to Increase abutment.
• The resultant groups are then placed in rows with
groups maximally connected to the Vss and V𝐷𝐷 rails
placed towards these signals. Row placement is then
based on the density of other connections. ·
• Routing js achieved by vertical diffusion or manhattan
(horizontal and vertical) metal routing. This normally
would require a maze router.
 Input-Output (I/O) Structures
• Overall Organization
• Pad size is defined usually by the minimum
size to which a bond wire can be attached.
• This is usually of the order of 150 µm by 150
µm.
• Additionally, a constant position for VDD, Vss,
and any other global control wires is an
advantage.
• Fig. 5.58 illustrates some of these concepts.
• Power and ground bus widths may be
calculated from a worst-case estimate of the
power dissipation of a die and providing good
supply voltages.
• Multiple power and ground pads may be
used to reduce noise.
• Some designer advocate placing the lowest
circuit voltage (Vss) as die outermost track.
Fig 5.58 General pad layouts
•
• With these points in mind, a frame generation program may be easily constructed as
follows:
• The resulting I/O frame is shown in Fig 5.59a

Fig 5.59a I/O frame generation

 VDD and VSS pads
• These pads are easily designed and consist of metal pad connected to
appropriate bus
• The broken path may be completed in polysilicon .
• Alternatively, a two level metal process affords good cross overs.

VDD pad design

 Output pads
• An output pad must have sufficient drive capability to achieve adequate rise and fall
times.
• If pad drives non-CMOS loads, then any required DC characteristics must be met.
• If pads are to drive CMOS loads, given a load capacitance and target rise and fall time,
the output transistor sizes may be calculated.
• one then generally needs buffering to present a lower load to internal circuitry.
• A ratio of 2.7 is optimal for speed. However. a stage ratio of 2—10 will work adequately.
• Generally, in a pad, a two-stage inverter circuit is used to result in a non-inverting
output stage.
• Layout guidelines such as separating n- and p-transistors and using the appropriate
guard rings tied to the supply rails must be used.
• When driving TTL loads with CMOS gates, the different switching thresholds have to be
considered.
• VIL of a TTL gate is 0.4 volts. VOL of a CMOS gate is 0 volts.
• VIH for a TTL gate is 2.4 volts. The VOH for a CMOS gate is 5 volts.
• In the low state, the CMOS buffer must be capable of "sinking" 1.6 mA for a standard
TTL load with a VOL of <0.4 V.
 Input pads
• The design of input pads can parallel that of output pads with respect to transistor
sizing.
• Often the transistors used in the output pad may be just "turned around.“
• The gate connection of an MOS transistor has a very high input resistance (1012 to 1013
Ω).
• The voltage at which the oxide punctures and breaks down is about 40—100 volts.
• The voltage that can build up on a gate may be determined from

• Thus if I = 10 µA, Cg=.03 pF, and Δt = 1µSec, the voltage on the gate is approx. 330 volts.
• Usually a combination of a resistance and diode clamps (electrostatic protection) are
used to limit this potentially destructive voltage.
• A typical circuit is shown in Fig. 5.60
• Clamp diodes DI and D2 turn on if the
voltage at node X rises above VDD or
below Vss.
• Resistor R is used to limit the peak
current that flows in the diodes in the
event of an unusual voltage excursion.
• Values anywhere from 200 Ω—3K Ω are
used.
• This resistance, in conjunction with any
input capacitance, C, will lead to an RC
time constant.
• A polysilicon resistor is preferable to a
diffusion resistor in a p-well process, as it
reduces the possibility of creating extra
charge injection into the substrate which
can contribute to latch-up.
• A "punch-through" device has closelv spaced source and drain diffusions but no
gate.
• The device affords protection by "avalanching' at around 50V.
• When interfacing TTL logic to CMOS, it is advantageous to place the switching
point of the input inverter in the middle of the TTL switching range.
• For TTL VOL = 0.4 volts and VOH = 2.4 volts.
• Thus the switching point should be set near 1.4 volts.
 Tri-state pads
• A tri-state pad may be modeled on the tri-state inverter structure.
• Another circuit is shown in Fig. 5.61a.
• This is faster due to the reduced number of devices in series.
• Care must be taken to switch the buffer as to prevent large DC currents during
switching.
 Bi-directional pads
• By merging an input and a tristate pad , a bi directional pad may be constructed.
End of Module 4