Unit 3 - Introduction to CMOS Logic

Styles
Combinational vs. Sequential Logic
Static complementary gate structure

Pull-up and pull-down networks

VDD

pull-up
network
inputs out
Pull-down
network
VSS

3
 Static CMOS Circuit
• At every point in time (except during the switching transients) each gate output
is connected to either VDD or Vss via a low-resistive path.
• The outputs of the gates assume at all times the value of the Boolean function,
implemented by the circuit (ignoring, once again, the transient effects during
switching periods).
• This is in contrast to the dynamic circuit class, which relies on temporary
storage of signal values on the capacitance of high-impedance circuit nodes.
• In Static CMOS circuits with n inputs, 2n transistors are needed.
• nMOS block is a dual of the pMOS block.
❑ Whatever is in series in nMOS, appears in parallel in pMOS and vice versa.
• CMOS gates consume power only during the transition of inputs.
Pull-up/pull-down network design
❑Pull-up and pull-down networks are duals.

❑To design one gate, first design one network, then compute
dual to get other network.

5
 NMOS Transistors in Series/Parallel Connection

Transistors can be thought of as switches controlled by their gate signal

NMOS switch closes when the switch control input is high
PMOS Transistors in Series/Parallel Connection
Complementary CMOS Logic Style Construction (cont.)
CMOS Inverter

VDD N Well VDD

PMOS 2
PMOS
Contacts
In Out

In Out
NMOS Metal 1
Polysilicon

NMOS
GND
NAND Gate

Va Vb Vout
0 0 1
0 1 1
1 0 1
1 1 0
10
 Voltage transfer curves

• The threshold voltages of the two devices are given by:

• The propagation delay depends upon the input patterns

NOR Gate

Va Vb Vout
0 0 1
0 1 0
1 0 0
1 1 0
12
Example Gate: COMPLEX CMOS GATE
 4-input NAND Gate

Vdd

Out

GND

In1 In2 In3 In4

Complex CMOS Structures

15
Xor gate

16
 AOI/OAI gates

❑AOI = and/or/invert; OAI = or/and/invert.

❑Implement larger functions.
❑Pull-up and pull-down networks are compact: smaller area, higher speed
than NAND/NOR network equivalents.

17
AOI example

invert

or

and

18
Problems

A C

B D
Y
A B

C D

19
 Problems

❑Design a CMOS circuit to implement the logic

Y = A'B' + B'C + C'A
❑Make a 2 input CMOS XOR gate to implement
Y = A ⊕ B.
❑CMOS XOR and XNOR gates are similar. Just one of the input
pairs (A and A' are reversed).

20
 Pseudo-nMOS
• Adding a single pFET to otherwise nFET-only
circuit produces a logic family that is called
pseudo-nMOS
• Less transistor than CMOS
• For N inputs, only requires (N+1) FETs
• Pull-up device: pFET is biased active since the
grounded gate gives VSGp = VDD
• Pull-down device: nFET logic array acts as a large Figure 4.1 General structure
of a pseudo-nMOS logic gate
switch between the output f and ground
• However, since the pFET is always biased on, VOL
can never achieve the ideal value of 0 V
• A simple inverter using pseudo-nMOS as Figure
4.2 (1)
(2) Figure 4.2 Pseudo-nMOS inverter
 nFET Array in Pseudo-nMOS
❒ The design of nFET array of pseudo-nMOS is the same as in standard CMOS
» Series and parallel logic FETs
» Smaller simpler layouts, and interconnect is much simpler
» However, the sizes need to be adjusted to insure proper electrical coupling to
the next stage (a) General circuit
» Resize in physical design

(b) Layout
(a) NOR2 (b) NAND2
Figure 4.4 AOI gate
Figure 4.3 Pseudo-nMOS NOR and NAND gates
 Dual-Rail Logic Networks
• Single-rail logic: the value of a variable is either a 0 or a 1 only

• Dual-rail logic: both the variable x and its complement are used to form
the difference
 Differential Cascode Voltage Switch Logic (DCVSL)
• DCVS or differential CVSL (CVSL) provides for dual-rail logic gates, and the
out results f and are held until the inputs induce a change
Differential Cascode Voltage Switch Logic (DCVSL)

Figure 4.23 Structure of a CVSL logic gate (a) AND/NAND (b) OR/NOR

Figure 4.24 CVSL gate example

 Differential Cascode Voltage Switch Logic (DCVSL)
• The DCVSL gate provides differential (or complementary) outputs.
• Both the output signal (Vout1) and its inverted value (Vout2) are simultaneously available.
Advantages
• It eliminates the need for an extra inverter to produce the complementary signal.
• Differential implementation of a complex function may reduce the number of gates required
by a factor of two.
• The number of gates in the critical timing path is also often reduced.
• This approach prevents some of the time-differential problems introduced by additional
inverters.
Disadvantages
• The differential nature virtually doubles the number of wires that must be routed, often
leading to unwieldy designs (on top of the additional implementation overhead in the
individual gates).
• The dynamic power dissipation is high.
 Pass Transistor Logic
• Reduce the number of transistors required to implement logic
by allowing the primary inputs to drive gate terminals as well
as source/drain terminals
• Contains only NMOS transistors.
• In this gate, if the B input is high, the top transistor is turned on
and copies the input A to the output F.
• When B is low, the bottom pass transistor is turned on and
Pass transistor implementation of AND gate
passes a 0.
• an NMOS device effectively passes a 0 but is poor at pulling a
node to VDD.
• When the pass transistor pulls a node high, the output only
charges up to VDD -VTn.
 Pass Transistor Logic
• Pass-transistor gates cannot be cascaded by connecting the output of
a pass gate to the gate input of another pass-transistor
• The output of M1 (node x) drives the gate of another MOS device.
Node x can charge up to VDD-VTn1. If node C has a rail-to-rail
swing, node Y only charges up to the voltage on node x - VTn2,
 Tri-State Circuits
• A tri-state circuit produces the usual 0 and 1 voltages,
but also has a third high impedance Z (or Hi-Z)
• Useful for isolating circuits from common bus
lines
• In Hi-Z case, the output capacitance can hold a
voltage even though n hardwire connection exists
• A non-inverting circuit ( a buffer) can be obtained by
adding a regular static inverter to the input

(a) Symbol and operation (b) CMOS circuit Figure 4.6 Tri-state layout

Figure 9.5 Tri-state inverter

 Dynamic CMOS Logic Circuits
• A dynamic logic gate uses clocking and charge storage
properties of MOSFETs to implement logic operations
• Provide a synchronized data flow
• Result is valid only for a short period
• Less transistors, and maybe faster than static cascades

• Based on the circuit in Figure 4.13

• The clock drives a complementary pair of transistors Mn
and Mp
• An nFET array between the output node and ground to
perform the logic function
• When it is called the precharge phase
• When it is called the evaluation phase
Figure 4.13 Basic dynamic logic gate
 Dynamic CMOS Logic Circuits
• A dynamic NAND3 is shown in Figure 9.18

• When f = 1, charge leakage reduces the voltages held on

the output node

Figure 4.14 Dynamic logic gate example

Leakage
• Dynamic node floats high during evaluation
• Transistors are leaky (IOFF ≠ 0)
• Dynamic value will leak away over time
• Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
• Must be weak enough not to fight evaluation

Circuit Families Slide 32

Charge Sharing
• Dynamic gates suffer from charge sharing

Slide 33
Secondary Precharge
• Solution: add secondary precharge transistors
• Typically need to precharge every other node
• Big load capacitance CY helps as well

Circuit Families Slide 34

Noise Sensitivity
• Dynamic gates are very sensitive to noise
• Inputs: VIH ≈ Vtn
• Outputs: floating output susceptible noise
• Noise sources
• Capacitive crosstalk
• Charge sharing
• Power supply noise
• Feedthrough noise
• And more!

Circuit Families Slide 35

 Domino Logic
• Domino logic is a CMOS logic style obtained by adding a
static inverter to the output of the basic dynamic gate
circuit
• Non-inverting
• Cascade operation
• “Domino chain reaction” that must start at the first
stage and then propagate stage by stage to the output
Figure 4.16 Domino logic stage

(a) AND gate (b) OR gate

Figure 4.18 Layout for
Figure 4.17 Non-inverting domino logic gates
domino AND gate
 Domino Logic

❒ Note that the operation indicates that domino gates are only useful in cascades

(a) Single-FET charge keeper (b) Feedback controlled keeper

Figure 4.19 A domino cascade Figure 4.20 Charge-keeper circuits

(a) Percharge (b) Evaluate

Figure 4.21 Visualization of the domino effect Figure 4.22 Structure of a MODL circuit
NORA CMOS Logic (NP-Domino Logic)
 NORA CMOS Logic (NP-Domino Logic)
• In domino CMOS logic gates, all logic operations are performed by the
NMOS transistors acting as pull-down networks, while the role of PMOS
transistors is limited to pre-charging the dynamic nodes.
• In addition to NMOS-based domino CMOS logic, we can construct
dynamic logic stages using PMOS transistors.
• Advantages of NORA CMOS logic
• Static CMOS inverter is not required at the output of every dynamic
logic stage. Instead, direct coupling of logic blocks is feasible by
alternating nMOS and pMOS logic blocks.
• It allows pipelined system architecture.
• NORA CMOS logic gates also suffer from charge sharing and leakage.
 True Single Phase Clock (TSPC) CMOS
• Each NMOS and PMOS stage is followed by a dynamic latch (inverter) built with only the
single phase clock φ
• The single phase clock φ is used for both NMOS and PMOS stages – NMOS logic stages
pre-charge when φ is low and evaluate when φ is high – PMOS logic stages pre-charge
when φ is high and evaluate when φ is low
• With inverter latches between each stage, an erroneous evaluation condition can not exist
• Attractive circuit for use in pipelined, high-performance processor logic
 Clock-CMOS (C2MOS) Logic
• Static CMOS: the output of a static logic gate is valid so long as the
input value is valid and the circuit has stabilized

• However, logic delays are due to the “rippling” through the circuits
• No reference to any specific time base
• So on, Clock CMOS, or C2MOS is proposed

• C2MOS concept: non-overlapping clock

(3)
(4) Figure 4.7 Clock signals

• But in physical signal, the clocks may overlap slightly during a

transition
 C2MOS Networks
❒ C2MOS is composed of a static logic circuit with a tri-state output network (made up of FETs M1 and
M2) that is controlled by and
» When , both M1 and M2 are active, and become a standard static logic gate
» When , both M1 and M2 are cut off, so the output is a Hi-Z state

Figure 4.8 Structure of a C2MOS gate

 Example of C2MOS

(a) NAND2

(a) Inverter (b) NAND2

Figure 4.10 Layout examples of C2MOS circuits

(b) NOR2
Figure 4.9 Example of C2MOS logic gate
 Leakage in C2MOS
• Charge leakage: since the output node cannot
hold the charge on Vout very long
• This places a lower limit on the allowable clock
frequency
• If a voltage is applied to the drain or source, a
small leakage current flows into, or out of, the
device
• One reason is due to the required bulk connections (a) Bulk leakage currents
• The current off of the capacitor by iout
(5)

(6)

(7)
(b) Logic 1 voltage decay

Figure 4.11 Charge leakage problem

(8)
Complementary Pass-Transistor Logic
• Complementary Pass-Transistor (CPL): an
dual-rail tech. that is based on nFET logic
equations

(a) AND gate (b) AND/NAND array

Figure 4.25 CPL AND/NAND circuit

• CPL has several 2-input gates that can be

created by using the same transistor topology
with different input sequences
• Less layout area
• However, threshold will be loss and the fact that
an input variable may have to drive more than
one FET terminal (a) OR/NOR (b) XOR/XNOR

Figure 4.26 2-input CPL arrays