Application note

Renesas R-Car H2 platform for

automotive infotainment
AN-PM-050

Abstract
The R-Car H2 System-on-Chip (SoC) based platform from Renesas is part of a family of platforms
(R-Car series) for automotive infotainment systems. The H2 is aimed at the high-end segment, and is
optimised for automotive Human Machine Interface (HMI), infotainment and integrated dashboards.

The platform features the Dialog DA9063 as PMIC (Power Management IC) and the Dialog DA9210
multiphase step down buck converter to power and supervise the complete system.

Through a description of the general system configuration, power capabilities and requirements and
an overview of the component interconnections, it will be shown that the combination of DA9063 and
DA9210 are highly suited as the R-Car power management system solution for H2 platforms.
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Contents
Abstract ................................................................................................................................................ 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 2
Tables ................................................................................................................................................... 2
1 Introduction.................................................................................................................................... 3
2 Renesas R-Car H2 SoC description ............................................................................................ 3
3 DA9063 and DA9210 description ................................................................................................. 4
4 R-Car H2 SoC power requirements ............................................................................................. 6
5 DA9063 PMIC and R-Car H2 SoC block system diagram .......................................................... 7
6 Cold boot sequence for H2........................................................................................................... 8
1
7 Platform resource references and ordering information ......................................................... 9
8 DA9063-6DHK2-A detailed register description ....................................................................... 10
Revision history ................................................................................................................................. 14

Figures
Figure 1: R-Car H2 system block diagram ............................................................................................ 3
Figure 2: DA9063 system block diagram .............................................................................................. 4
Figure 3: DA9210 system block diagram .............................................................................................. 5
Figure 4: R-Car H2 power-up sequence ............................................................................................... 6
Figure 5: DA9063 and R-Car H2 interconnections ................................................................................ 7
Figure 6: DA9063-6DHK2-A Power-up sequence ................................................................................. 8

Tables
Table 1: OTP6D register settings ........................................................................................................ 10

Application note Revision 1.0 15-Sep-2015

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1 Introduction
This document describes how to interconnect the DA9063 Power Management IC (PMIC) and the
DA9210 to the Renesas R-Car H2 SoC. The DA9063 is a highly integrated chip that supports
Dynamic Voltage Control (DVC) technology, enabling significant power saving: this feature supports
the DVFS (Dynamic Voltage and Frequency Scaling) technology that is used by many processors.
As a result of their highly integrated features, the DA9063 and DA9210 PMICs significantly reduce
the overall system cost and size compared to a discrete solution. This application note addresses
only the power supply related features: discussion of other features of the optimized PMIC is beyond
the scope of this document.
For further information on the DA9063 and DA9210 please refer to the datasheets available via your
local Dialog sales office.
For information about Renesas R-Car H2 SoC, please refer to Renesas website:

http://am.renesas.com/applications/automotive/cis/cis_highend/rcar_h2/

2 Renesas R-Car H2 SoC description

Renesas R-Car H2 is a platform for automotive infotainment with a SoC containing nine cores
(ARM®CortexTM-A15 Quad Core, ARM Cortex TM-A7 Quad, SH4A) and G6400 GPU.
Figure 1 shows a typical system block diagram of the R-Car H2 SoC application. The embedded
ARM®CortexTM-A15 Quad Core and SH4A core requires a suitable power management that is
readily achieved using the Dialog DA9063 with DA9210.

Figure 1: R-Car H2 system block diagram

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3 DA9063 and DA9210 description

The DA9063 is a high current system PMIC suitable for dual and quad core processors that require
up to 5 A core processor supply. The DA9063 contains:

• 6 x DC-DC buck converters designed to use small external 1 μH inductors, capable of

supplying in total up to 12 A continuous output (0.3 – 3.3 V). The buck converters do not
require external Schottky diodes; they dynamically optimize their efficiency depending on
the load current using an Automatic Sleep Mode (ASM) and incorporate pin and software
controlled Dynamic Voltage Control (DVC) to support processor load adaptive
adjustment of the supply voltage. In addition BuckPro includes the facility to implement
VTT memory bus termination.

• 11 x SmartMirror™ programmable low dropout (LDO) regulators rated up to 300 mA. All
support remote capacitor placement and can operate from low 1.5/1.8 V input supplies.
This allows these LDOs to be cascaded with (i.e. supplied by) a suitable buck supply to
improve overall system efficiency.

Figure 2: DA9063 system block diagram

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The DA9210 (Figure 3) is a multi-phase synchronous step down converter suitable for supplying
CPUs that require high currents. The DA9210 operates with four phases, each phase using a small
external 0.47 μH inductor. The buck is capable of delivering up to 12 A continuous output current at
an output voltage in the range of 0.3-1.57 V. The input voltage range of 2.8-5.5 V makes it suited for
a wide variety of low voltage systems. Two DA9210 devices can be used in parallel to deliver up to
24 A.
To guarantee the highest accuracy and support multiple PCB routing scenarios without loss of
performance, a remote sensing capability is implemented in DA9210.

Figure 3: DA9210 system block diagram

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4 R-Car H2 SoC power requirements

Several power domains in the R-Car H2 SoC platform require precise voltage management for
reliable operation of the system. The primary power domains are:
VDD (1.0 V): power supply for internal ARM cores (ARM® Cortex TM-A7 Dual Core, SH4A
core)
VCCQ (3.3 V/ 1.8 V): supplies for I/Os
VDDR (1.5 V/1.35 V): supplies for DDR pre-drivers
Other supplies may be required for DDR3 memory, peripherals, I/O interfaces, USB and such like.
Additionally, the system power management must comply with the specific power-up and power-
down sequence guidelines for the R-Car SoC (Figure 4).

Figure 4: R-Car H2 power-up sequence

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5 DA9063 PMIC and R-Car H2 SoC block system diagram

Figure 5: DA9063 and R-Car H2 interconnections

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6 Cold boot sequence for H2

Figure 6: DA9063-6DHK2-A Power-up sequence

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7 Platform resource references and ordering information1

Platform name: R-Car H2
PMIC, BUCK: DA9063, DA9210
Schematic: ADAS_SK_V201_schematic_v1
Board name: ADAS-SK (R-CAR-H2)
2
PMIC OTP variant: DA9063-6DHK2-A
2 2
BUCK OTP variant: DA9210-18FN2-A , DA9210-21FN2-A

Please refer to AN-PM-010_Layout_Guidelines available from the Dialog website, for Dialog
recommended PCB layout guidelines.

Please refer to AN-PM-058 Shared IRQ Line Considerations available from the Dialog website, for
considerations regarding IRQ line sharing.

NOTE
1
For schematic availability, please contact your local Renesas representative.
2
Please contact your local Dialog representative for the most current recommended OTPs.

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8 DA9063-6DHK2-A detailed register description

Key settings
 Normal Start-up
 Voltage monitor
 Buck Core1 & Buck Core 2 dual-phase mode
 Buck Mem & Buck IO merged mode
 2-wire control interface, standard speed, FM+ (Fast Mode Plus)
 Eco mode enabled
 RTC enabled
 LDO 4, 8 GPIO controlled by host

Table 1: DA9063-6DHK2-A register settings

Register Function Register Register description
Address value
0x00A IRQ_MASK_A 0x00 nONKEY, RTC, and some status IRQ masks
0x00B IRQ_MASK_B 0x01 Charger wakeup and temperature, current or voltage IRQ masks
0x00C IRQ_MASK_C 0x00 GPI7-0 and ADCIN1-3 IRQ masks
0x00D IRQ_MASK_D 0x01 GPI15-8 and external control signal IRQ masks
0x00E CONTROL_A 0x03 PSM target status, companion charger control
0x00F CONTROL_B 0x09 Power down / up signalling
0x010 CONTROL_C 0x53 Debounce, boot, DVC and DEF_SUPPLY control
0x011 CONTROL_D 0x68 Watchdog and LED blink control
0x012 CONTROL_E 0x0C RTC, ecomode, feedback pins, V_LOCK
0x013 CONTROL_F 0x00 Watchdog reset, shutdown and wake-up
0x014 PD_DIS 0x40 Disable / pause blocks when below the PSS sequencer PD_DIS slot
0x015 GPIO_0_1 0xDD GPIO 0 and 1 control
0x016 GPIO_2_3 0xFD GPIO 2 and 3 control
0x017 GPIO_4_5 0xFF GPIO 4 and 5 control
0x018 GPIO_6_7 0xEF GPIO 6 and 7 control
0x019 GPIO_8_9 0xF9 GPIO 8 and 9 control
0x01A GPIO_10_11 0xEF GPIO 10 and 11 control
0x01B GPIO_12_13 0xDF GPIO 12 and 13 control
0x01C GPIO_14_15 0xAA GPIO 14 and 15 control registers
0x01D GPIO_MODE0_7 0xFE GPIO 0-7 mode control
0x01E GPIO_MODE8_15 0xFF GPIO 8-15 mode control
0x01F SWITCH_CONT 0xB0 Rail switches
0x020 BCORE2_CONT 0x00 BUCK CORE2 Control
0x021 BCORE1_CONT 0x60 BUCK CORE1 Control
0x022 BPRO_CONT 0x00 BUCK PRO Control
0x023 BMEM_CONT 0x00 BUCK MEM Control

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Register Function Register Register description
Address value
0x024 BIO_CONT 0x00 BUCK IO Control
0x025 BPERI_CONT 0x00 BUCK PERI Control
0x026 LDO1_CONT 0x00 LDO1 Control
0x027 LDO2_CONT 0x08 LDO2 Control
0x028 LDO3_CONT 0x00 LDO3 Control
0x029 LDO4_CONT 0x40 LDO4 Control
0x02A LDO5_CONT 0x00 LDO5 Control
0x02B LDO6_CONT 0x00 LDO6 Control
0x02C LDO7_CONT 0x00 LDO7 Control
0x02D LDO8_CONT 0x60 LDO8 Control
0x02E LDO9_CONT 0x00 LDO9 Control
0x02F LDO10_CONT 0x00 LDO10 Control
0x030 LDO11_CONT 0x00 LDO10 Control
0x031 SUPPLIES 0x00 Vibrator output level
0x032 DVC_1 0x00 Dynamic voltage control
0x033 DVC_2 0x00 Dynamic voltage control
0x034 ADC_MAN 0x04 ADC manual and automatic measurement control
0x035 ADC_CONT 0x00 ADC automatic measurement control
0x036 VSYS_MON 0x40
0x083 ID_2_1 0x20 PSS sequence control
0x084 ID_4_3 0x88 PSS sequence control
0x085 ID_6_5 0x01 PSS sequence control
0x086 ID_8_7 0x01 PSS sequence control
0x087 ID_10_9 0x00 PSS sequence control
0x088 ID_12_11 0x59 PSS sequence control
0x089 ID_14_13 0x66 PSS sequence control
0x08A ID_16_15 0x76 PSS sequence control
0x08B ID_18_17 0x37 PSS sequence control
0x08C ID_20_19 0x00 PSS sequence control
0x08D ID_22_21 0x00 PSS sequence control
0x08E ID_24_23 0x05 PSS sequence control
0x08F ID_26_25 0x00 PSS sequence control
0x090 ID_28_27 0x00 PSS sequence control
0x091 ID_30_29 0x05 PSS sequence control
0x092 ID_32_31 0x00 PSS sequence control
0x095 SEQ_A 0xA5 PSS sequencer slot end points
0x096 SEQ_B 0xFE PSS sequencer slot end points
0x097 WAIT 0x54 Power sequencer wait cycle

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Register Function Register Register description
Address value
0x098 EN_32K 0xE8 RTC clocking control
0x099 RESET 0x94 Reset timer control
0x09A BUCK_ILIM_A 0xFF Buck current limit
0x09B BUCK_ILIM_B 0xFF Buck current limit
0x09C BUCK_ILIM_C 0xFF Buck current limit
0x09D BCORE2_CFG 0x80 BUCKCORE2 control
0x09E BCORE1_CFG 0x80 BUCKCORE1 control
0x09F BPRO_CFG 0x99 BUCKPRO control
0x0A0 BIO_CFG 0x81 BUCKPRO control
0x0A1 BMEM_CFG 0x81 BUCKMEM control
0x0A2 BPERI_CFG 0x81 BUCKPERI control
0x0A3 VBCORE2_A 0x78 BUCKCORE2 voltage A
0x0A4 VBCORE1_A 0x78 BUCKCORE1 voltage A
0x0A5 VBPRO_A 0x16 BUCKPRO voltage A
0x0A6 VBMEM_A 0x7D BUCKMEM voltage A
0x0A7 VBIO_A 0x7D BUCKIO voltage A
0x0A8 VBPERI_A 0x32 BUCKPERI voltage A
0x0A9 VLDO1_A 0xAD LDO* voltage A
0x0AA VLDO2_A 0xBC LDO* voltage A
0x0AB VLDO3_A 0xF8 LDO* voltage A
0x0AC VLDO4_A 0xF8 LDO* voltage A
0x0AD VLDO5_A 0xB2 LDO* voltage A
0x0AE VLDO6_A 0xB2 LDO* voltage A
0x0AF VLDO7_A 0x94 LDO* voltage A
0x0B0 VLDO8_A 0xB2 LDO* voltage A
0x0B1 VLDO9_A 0xB2 LDO* voltage A
0x0B2 VLDO10_A 0xB2 LDO* voltage A
0x0B3 VLDO11_A 0x94 LDO* voltage A
0x0B4 VBCORE2_B 0x69 BUCKCORE2 voltage B
0x0B5 VBCORE1_B 0x69 BUCKCORE1 voltage B
0x0B6 VBPRO_B 0x16 BUCKPRO voltage B
0x0B7 VBMEM_B 0x7D BUCKMEM voltage B
0x0B8 VBIO_B 0x6D BUCKIO voltage B
0x0B9 VBPERI_B 0x32 BUCKPERI voltage B
0x0BA VLDO1_B 0x1E LDO* voltage B
0x0BB VLDO2_B 0x3C LDO* voltage B
0x0BC VLDO3_B 0x2D LDO* voltage B
0x0BD VLDO4_B 0x2D LDO* voltage B

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Register Function Register Register description
Address value
0x0BE VLDO5_B 0x32 LDO* voltage B
0x0BF VLDO6_B 0x32 LDO* voltage B
0x0C0 VLDO7_B 0x14 LDO* voltage B
0x0C1 VLDO8_B 0x14 LDO* voltage B
0x0C2 VLDO9_B 0x32 LDO* voltage B
0x0C3 VLDO10_B 0x32 LDO* voltage B
0x0C4 VLDO11_B 0x14 LDO* voltage B
0x0C5 BBAT_CONT 0x00 Backup battery charger
0x0C6 GPO11_LED 0x00 High power GPO PWM
0x0C7 GPO14_LED 0x00 High power GPO PWM
0x0C8 GPO15_LED 0x00 High power GPO PWM
0x0C9 ADC_CFG 0xE0 ADC automatic measurement control
0x0CA AUTO1_HIGH 0x00 ADC measurement thresholds
0x0CB AUTO1_LOW 0x00 ADC measurement thresholds
0x0CC AUTO2_HIGH 0x00 ADC measurement thresholds
0x0CD AUTO2_LOW 0x00 ADC measurement thresholds
0x0CE AUTO3_HIGH 0x00 ADC measurement thresholds
0x0CF AUTO3_LOW 0x00 ADC measurement thresholds
0x105 INTERFACE 0xB9 Host interfaces
0x106 CONFIG_A 0xA6 Host interfaces and other IOs
0x107 CONFIG_B 0x16 VDD_FAULT comparator
0x108 CONFIG_C 0x50 Buck duty cycle and clock polarity
0x109 CONFIG_D 0x00
0x10A CONFIG_E 0x3F BUCK and rail switch default settings
0x10B CONFIG_F 0x07 LDO default and bypass mode settings
0x10C CONFIG_G 0xFF LDO default settings
0x10D CONFIG_H 0xF8
0x10E CONFIG_I 0x04
0x10F CONFIG_J 0Xca
0x110 CONFIG_K 0x00 GPIO pull resistors
0x111 CONFIG_L 0x20 GPIO pull resistors
0x112 CONFIG_M 0x00
0x113 CONFIG_N 0x00
0x114 MON_REG_1 0xCE
0x115 MON_REG_2 0x00
0x116 MON_REG_3 0x00
0x117 MON_REG_4 0x44
0x121 GP_ID_0 0x01

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Register Function Register Register description
Address value
0x122 GP_ID_1 0x00
0x123 GP_ID_2 0x00
0x124 GP_ID_3 0x00
0x125 GP_ID_4 0x00
0x126 GP_ID_5 0x00
0x127 GP_ID_6 0x00
0x128 GP_ID_7 0x00
0x129 GP_ID_8 0x00
0x12A GP_ID_9 0x00
0x12B GP_ID_10 0x00
0x12C GP_ID_11 0x00
0x12D GP_ID_12 0x00
0x12E GP_ID_13 0x00
0x12F GP_ID_14 0x00
0x130 GP_ID_15 0x00
0x131 GP_ID_16 0x00
0x132 GP_ID_17 0x00
0x133 GP_ID_18 0x00
0x134 GP_ID_19 0x00
0x183 CUSTOMER_ID 0x00 Chip ID
0x184 CONFIG_ID 0x6D Customer ID

Revision history
Revision Date Description
1.0 15-Sep-2015 Initial version.
2.0 07-Oct-2015 Update to OTP information.

Application note Revision 1.0 15-Sep-2015

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APPROVED The content of this document has been approved for publication.
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