Hardware Implementation of a Low Power

SD Card Controller
Pan Zhou1, Teng Wang1, Xin’an Wang1*,Yinhui Wang1
1 Key Lab of Integrated Microsystems
School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School
Shenzhen, China
anxinwang@pku.edu.cn

Abstract—Technical innovation drives the low second application category, which has experienced a
power consumption requirements in ASIC design. This dramatic increase of heat dissipation that is now
paper presents a SD card controller, in which two reaching a fundamental limit [2].
asynchronous units (BIU and CIU) are included for Excessive power dissipation causes overheating,
lower power structure. Adding low power mode to finite
state machine makes this controller to shut down if no
which can lead to soft errors or permanent damage. It
data or command is transferring for a long time. Only also limits battery life in portable equipment. From
one FIFO is used to store temporary data in order to technical point of view, the fundamental problem of
save area, it is still simplified though add some control low power consumption can be divided into four
logics. These modified structures are specifically major areas: device, circuit, structure and system. The
implemented for low power applications, and hardware prevalent scheme in circuit or structure area for low
cost is reduced at the same time. FPGA prototyping power design is to take advantage of pipeline or
results show the correctness of the proposed design, and parallel method. However, that method requires
it is synthesized by CSMC 180nm CMOS technology
reasonable tasks partitioning, which will result in
process with a clock frequency of 100 MHz, dynamic
power consumption of 8.2223mW and 12.2K equivalent
increasing complexity and difficulty as more
logic gates. developer kits are in need.
Display Data Upload
Keypad Audio
Index Terms—low power consumption, SD card
controller, asynchronous units, FSM adding low power
mode, one FIFO Keypad Audio Display
Control Codec Control
I. INTRODUCTION Sensors commu
Analog Front End
Global aging, limited energy sources, the demand Wireless

for low consumption and other factors are

USB Port
contributing to the reform of ASIC design, with USB
which smaller area and lower power of chip have SD card controller Trans

gradually been the critical issues. More generally, as Level

density size and complexity of the chips continue to ADC Shift
MMC/SD
increase, the difficulty in providing adequate cooling Power CARD
might either add significant cost or limit the power Battery Source
functionality of the computing systems which make supply Charger
use of those integrated circuits. Saving power Figure 1. Typical architecture of system application
consumption by hook in IC design field is inevitable SD card is most widely used in data storage
now and later. applications. It includes an on-card intelligent
As chip size is shrinking and many other micro- controller which manages interface protocols,
electronics reliabilities are developing gradually, low security algorithms for copyright protection, data
power design of any system has become priority [1]. storage and retrieval, as well as error correction code,
The current trend towards low power design in defect handling and diagnostics, power management
mainly driven by two forces: the growing demand for and clock control [3]. This paper proposed a SD card
long life autonomous portable equipment, and the controller with several schemes of low power
technological limitations of high performance VLSI consumption as shown in figure1.
systems. For the first category of products, low
power is the major goal for which speed and/or II. ARCHITECTURE OVERVIEW
dynamic range have to be sacrificed. High speed and Depending on analysis of target application, the
high integration density are the objectives for the proposed architecture as shown in figure 2 combine

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 Figure 2. The proposed architecture of SD card controller
two asynchronous units, bus interface unit (BIU) and
card interface unit (CIU), with communication unit. III. DESIGN AND IMPLEMENTATION
Input sample unit and output hold unit make sure that To deal with low power design in SD card
signals from controller and card can communicate controller, this paper makes some improvements from
correctly. Clock control unit select the frequency system architecture, hardware implementation and
which SD card operate in. other aspects. The following description will focus on
According to SD card protocol, command is 48 optimized structure set for low consumption,
bits which consist of start bit, index bits, content bits, improved design of finite state machine and simple
cyclic redundancy check bits (CRC) and stop bit. If design for data temporary storage.
master want to control SD card to realize data
A. Optimized Structure for Low Consumption
transfer or other functions, relative registers in BIU is
loaded with data. CIU take over decoded data and Asynchronous designs are promising to tackle
transmit them to card in the same clock. The problems such as electro-magnetic interference,
proposed hardware circuit for CRC takes advantage power consumption, performance, and modularity of
of linear feedback shift registers structure based on digital circuits. This gives asynchronous design
equation 1. interesting features including higher throughput,
robustness, lower dynamic power consumption and
C ij+1 = C ij −1 + gi (Cix + din ) (1) better EMI characteristics [4].
Numerous SD card controllers employ the same
structure, among which BIU and CIU are most
BIU and CIU is equipped with clock prevalent units. BIU is in need since control signals
independently, yet linked via communication unit. from master must be received and disposed, and CIU
This design implements a synchronizer based two is employed to transmit command and data to SD
cascade registers to make relevant signals card. Actually, the clock frequency which SD card
communicating. Signals from different clock domains need is far below that in controller. Making use of
may not communicated correctly. It is not enough if frequency dividing circuit will result in larger area
there is only synchronizer. Impulse transition unit is and larger power consumption obviously.
required especially when to transmit signals from fast To deal with this matter, based on advantage of
clock domain to slow clock domain. asynchronous circuit, this design alters clock of CIU
To achieve command and data transfer, input and optimizes it for low consumption. When signals
sample unit and output hold unit are designed for this go from a slower domain to a faster clock domain,
SD card controller. The clock source used by card pulse transform unit is need to guarantee correct
comes from clock unit. In the actual implementation, timing requirement.
there is a little delay for data from SD card or
controller relative to clock unit. Therefore, the signals B. Improved Design of Finite State Machine
of output hold unit is exported to SD card, and the Data transfer and command transfer are issues
input sample unit is used to acquire signals from card. indispensable, so the strategy is pivot in which

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corresponding logic and state machine are realized. binary value through gray code conversion. Wfull
There are three state machines in this design, and rempty are not only the control signals of read
command FSM, data transmit FSM and data receive and write in FIFO, but also sent to master as interrupt
FSM. The general format for command and data is signals.
contain start bit, transmitter bit, content bits, cyclic
redundancy check bits and stop bit. There will be two
formats when response is necessary after card return
operating results.
Command transmit and data transmit contribute
to the vast majority of FSM in this design. Relative to
other controllers only wait start signals to initiate
transfer, this paper proposed a novel scheme in which
low consumption state is flexibly used. Clock source
of most components in CIU can be cut off when the
command FSM stay in idle state more than 100 clock
cycles. Since there is no command or data transfer
after a certain time, some parts is no need to continue
working, which causing power loss. Figure 4. Asynchronous FIFO structure diagram
In line with correlative researches, the major area
and consumption in the ASIC become the quantity of
flip-flops. Aiming at this issue, this design try to cut
short the amount of FIFO, to facilitate the data
transmission low-consumption and high-performance.
Firstly, SD card controller is a half-duplex
peripheral as mentioned. Then the sole FIFO can only
stores either receive data or transmit data at the same
time. This FIFO works in two different clock
domains. Experiment results in [7] prove that
comparing with synchronous FIFO, asynchronous
FIFO performs better in cutting area and reducing
consumption. But it will cause conflict quasi-steady
signals, which may lead to the design function of the
system failure. Synchronization units are put into use
in order to guarantee FIFO work normally. This
design provides two control signals named wen and
ren as FIFO enable signals, benefited by directly
Figure 3. Finite state machine flow diagram accessing enable signals no matter when to transmit
Figure 3 shows the final FSM structure. The or receive. As well the FIFO is asynchronous, a
improvements aforementioned reduce the power of multiplexer is supported to select accurate clock. At
CIU in this design. More to the point, consequent last, a process can interactive with BIU and CIU by
structure augment will be uncomplicated. means of control logic.
C. Simple Design for Data Temporary Storage IV. RESULTS AND DISCUSSIONS
Data transfer between BIU and CIU is an issue To ensure the design function properly, both
about transfer cross clock domain, and treatment of abundant random verification and certain application
asynchronous clock has been difficulties in circuit algorithms are combined applied for function
design. There are many solutions to this problem, simulation. FPGA prototyping is carried out with
such as the phase control method, double jump Xilinx XUPV5-LX110T platform and SanDish TF-
technology. However, these methods are low CLASS10 card is employed as the SD card model.
efficiency, the best approach is to use asynchronous Figure 5 illustrates the transmit procedure of the
FIFO, which passes signals between the clock controller in normal condition. When the command
regions is more flexible and commonly used [5]. start signal is high and relative data are ready,
Figure 5 illustrates the structure of this command FSM turns to cmd_tx state. Signal wire
asynchronous FIFO. Gray code is applied for the named cmd_out transmits command out. If this
judgment of full or empty on account of only one bit command expects response and data transmit, FSM
changing every time. Address of memory is normal turn to response_rx state after card send response.

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Data transmit start when response is done and V. CONCLUSION
checked correctly. Data can transfer in block mode or To meet the requirement of low power
stream mode, and block mode need cyclic consumption for communication with SD card, this
redundancy check. paper proposes and implements a low power SD card
controller, with asynchronous units BIU and CIU set
for valid transfer, as well as an asynchronous FIFO
for data temporary storage and improved finite state
machine adding low power state. The proposed
controller is implemented by hardware description
language, and simulated on ModelSim. This design is
verified by FPGA, and synthesized in CSMC 180nm
CMOS technology process with a clock frequency of
100MHz, dynamic power consumption of 8.2223mW
and 12.2K logic gates consumed.
Figure 5. command and data transfer waveform REFERENCES
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