See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/346078987

Design and Implementation of Real Time Data Acquisition System using

Reconfigurable SoC

Article in International Journal of Advanced Computer Science and Applications · January 2020
DOI: 10.14569/IJACSA.2020.0110938

CITATIONS READS
4 268

3 authors, including:

Dharmavaram Asha Devi

Sreenidhi Institute of Science & Technology
20 PUBLICATIONS 51 CITATIONS

SEE PROFILE

Some of the authors of this publication are also working on these related projects:

SoC Designs using Zed Boards with ARTIX7 FPGA View project

All content following this page was uploaded by Dharmavaram Asha Devi on 17 March 2021.

The user has requested enhancement of the downloaded file.

 (IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 11, No. 9, 2020

Design and Implementation of Real Time Data

Acquisition System using Reconfigurable SoC
(DAS using RSoC)

Dharmavaram Asha Devi1 Tirumala Satya Savithri2 Sai Sugun.L3

Department of Electronics and Department of Electronics and Project Assistant
Communication Engineering Communication Engineering Sreenidhi Institute of Science and
Sreenidhi Institute of Science and JNTUH College of Engineering, Technology
Technology, Hyderabad, India Kukatpalli, Hyderabad, India Hyderabad, India

Abstract—System on chip (SoC) technology is widely used for cost with bulk volume production and enables high speed data
high speed and efficient embedded systems in various computing transfers between the various system blocks [1].
applications. To perform this task, Application Specific IC
(ASIC) based system on chips are generally used till now by The data acquisition is an integral part of any measurement
spending maximum amount of research, development time and and control systems used in various applications. The
money. However, this is not a comfortable choice for low and principle of data acquisition is to acquire real world physical
medium-level capacity industries. The reason is, with ASIC or parameters such as temperature, light intensity, pressure,
standard IC design implementation, it is very difficult task where sound etc. through appropriate sensors that are connected
quick time to market, upgradability and flexibility are required. through multiple channel data selectors using time division
Therefore, better solution to this problem is design with multiplexing with serial peripheral interface technique or
reconfigurable SoCs. Therefore, FPGAs can be replaced in the parallel processing technique [2]. The real and physical data
place of ASICs where we can have more flexible and re- which is in analog nature has to be converted in to digital
configurable platform than ASIC. In the embedded world, in representation using digitization. The process of conversion of
many applications, accessing and controlling are the two analog signal into digital signal is known as digitization. After
important tasks. There are several ways of accessing the data and digitization, the digital data is read by the processor and
the corresponding data acquisition systems are available in the process the data in readable format and then it will be sent to
market. For defence, avionics, aerospace and automobile
the display devices if standalone measurement is required.
applications, high performance and accurate data acquisition
Otherwise, the data can be accessed remotely by using web-
systems are desirable. Therefore, an attempt is made in the
proposed work, and it has been discussed that how a
based data acquisition techniques using WiFi network.
reconfigurable SoC based data acquisition system with high Development time, cost and lack of flexibility are the
performance is designed and implemented. It is a semicustom major drawbacks of ASIC based SoCs [1]. These are
design implemented with Zynq processing system IP, appropriate choice for bulk volume production and where
reconfigurable 7-series FPGA used as programmable logic, there are no requirements for upcoming enhancements.
hygro, ambient light sensor and OLEDrgb peripheral module Because of this reason, low or medium volume market
IPs. All these sensor and display peripheral modules are
industries depends on a convenient solution, system on a
interfaced with processing unit via AXI-interconnect. The
programmable IC, an exact essence of system on
proposed system is a reconfigurable SoC meant for high-speed
data acquisition system with an operating frequency of 100MHz. reconfigurable device [1], [2]. This can be done with FPGAs
Such system is perfectly suitable for high speed and economic which are reconfigurable and flexible than ASIC based SoCs.
real time embedded systems. It is a better solution that using an FPGA for applications
where system enhancements are desired [3]. The technical
Keywords—Application Specific Integrated Circuit (ASIC); details of peripheral modules, Hygro, ALS and OLEDrgb are
Advanced eXtensible Interface (AXI); data acquisition system; referred from [4], [5] and [6], respectively.
Field Programmable Gate Array (FPGA); Peripheral Module
The earlier researchers were implemented FPGA based
(PMOD); System on Chip (SoC)
data acquisition designs using ISE software and Spartan 3,
I. INTRODUCTION Spartan 6 FPGAs respectively. Daniel Roggow et al explained
a laboratory workstation configuration with ZedBoard. They
Many cases, the term „SoC‟ was referred as an Application have demonstrated workstation setups for MP-1: Quadcopter
Specific Integrated Circuit (ASIC). The best example of an Interface, MP-2: Digital Camera, MP-3: Target Acquisition
ASIC based application is mobile phone. Complex circuitry and MP-4: UAV Control and they have received a good
with multiple functions with high speed logic, interfacing of feedback from the students [7].
many peripherals including memory is implemented on single
chip meant for specific application is known as application It is to be noted in [8], described about the system with
specific integrated circuit. The solution with SoC gives low three modules named as signal processing, data acquisition

325 | P a g e
www.ijacsa.thesai.org
 (IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 11, No. 9, 2020

with FPGA and data storage. It was designed by VHDL and and hyper terminal. The complete procedural flow with
simulated with ISE. respect to CAD tool is illustrated in Fig. 1.
FPGA based high speed ADC with a sampling rate of 80 B. Design Procedure
Mega samples and used DMA without loss of data and DDR3 The proposed research work is based on FPGA based SoC
memory was used for manipulations of data was discussed in using Zynq processor. It provides a perfect stage for the
[9]. The design was implemented with VHDL. implementation of flexible system on chips. Because, Zynq is
DAQ with Network Control Module using FPGA was a sandwich of a processing-system (PS) and programmable-
discussed in [11]. LabView software tool was used to design logic (PL) [1], [3]. The PS is prepared with a dual-core ARM
and development of their design and tested with National processor (ARM Cortex-A9). And the Artix 7 FPGA is used
Instruments data acquision and FPGA devices. as programmable logic.
In [12], a 32 channel DAQ system for medical imaging In the proposed work, Zed board is used that consists of
and clinical application was presented. It was developed with Zynq architecture, integrated memory, a various number of
FPGA, NI‟s PXI, ADC, signal generator, timing and peripherals, general purpose ports and high-speed interfacing
synchronization modules. FFT-hardware was implemented in ports for communication. The Programmable Logic is used for
FPGA for the purpose of high frame rates, demodulation of design and implementation of logic with high speed. And the
the signal and higher order harmonics spectral characteristics. processing system cares about software routines, operating
systems, and provides the communication between software
In [13], Satillite tracking data with respect to the humidity, and hardware [2]. To meet this need, Xilinx high level
temperature and light data measurements with Zynq processor synthesis tool, Artix 7 FPGA and ARM processor are used.
based reconfigurable SoC discussed efficiently.
In the proposed architectural design of data acquisition
Smart monitoring of automobile data logger design and system, AXI peripheral interconnect block is used to interface
prototype implementation with Zed Board and Xilinx platform Zynq processing system with all peripheral interfaces as
was explained in [14]. shown in Fig. 2.
The FPGA based processor designs, verifications of
various applications are referred from [15], [16], [17], [18],
[19] and [20].
As per the present survey of history in related work, the
majority of the research work methodology is conventional
FPGA front end flow designs using CAD tools. Therefore, the
corresponding technology and performance of the designs are
restricted within the technology scope of hardware and
software tools used. Definitely, there is a requirement in the
performance-based enhancements in the SoC based designs.
Therefore, by adding today‟s technology towards SoC
designs, especially in the design of high-speed real time
embedded system-based applications, an attempt is made to
design and develop the high-performance based data
acquisition system in Zynq-7000 architecture platform.
II. DESIGN OF SOC BASED DATA ACQUISITION SYSTEM
A. Methodology
The proposed system methodology is a semicustom SoC
block design using multiple IP integration using front end
CAD tool, Xilinx Vivado System Design Suite and SDK
software. The proposed system architecture consists of Zynq
processing system interfaced with hygro, ALS and OLEDrgb
via AXI interconnect. The hardware part of the design is
loaded in to the Artix7 FPGA, which acts as a programmable
logic device. The data processing and controlling part is
implemented with application software with SDK and ARM9
processor, acts as processing system. The hardware used for
verification are Artix 7 FPGA and the multiple sensors
interfaced with FPGA. The results can be monitored by either Fig. 1. Design and Implementation flow of SoC based DAS.
standalone system or remote system through WiFi network. In
the proposed system, peripheral modules, Hygro and ALS are
used to access temperature, humidity and ambient light
intensity. These parameters are displayed on OLEDrgb display
Sponsored Source: JNTUH TEQIP III UNDER CRS.

326 | P a g e
www.ijacsa.thesai.org
 (IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 11, No. 9, 2020

peripheral modules, hardware connectivity with zed board are

shown in Fig. 3.
As there are three PMODs used in the proposed system,as
illustrated in Fig. 4, their specifications and interface
configuration details are explained as follows.
A. HYGRO Interface
The HYGRO PMOD consists of T1 HDC1080, which is
an integrated digital temperature and humidity sensors. It
provides accurate measurement with low power. It operates in
a range of 2.7 V to 5.5 V supply. It is more economical and
suitable for wide range of low power applications. The
temperature and humidity sensors are calibrated with ±0.2°C
(typical) and ±2% accuracy.
Fig. 5 illustrates the interfacing of HYGRO PMOD with
Zynq Processor. It has dual modes of operations known as
measurement mode and sleep mode. After power up, it will be
Fig. 2. Block Diagram of Data Acquisition System. in sleep mode and waits for I2C input and commands. The
commands are used to trigger and read measurements, check
In this design, three peripheral modules are used, that are the status condition of the battery and configure the timing
Hygro, ALS and OLEDrgb. The Hygro PMOD consists of conversions. Whenever it obtains a command to trigger a
temperature and humidity sensors. Hence, in order to select measurement, it switches to measurement mode from sleep
these parameters, one interrupt signal is used. And this mode. If it completes the measurement, it will return to sleep
interrupt is connected through Concat block. We can observe mode. The default mode of this device is, first it will measure
from Fig. 2, an interrupt-IRQ (Interrupt Request) is connected temperature and then humidity. The bit pattern of the 16-bit
to output of Concat block and the input of Concat is connected temperature register is, first it will hold14-bit acquisition value
to I2C Interrupt from PMOD Hygro. This Hygro PMOD is and the two least significant bits are always zero.
connected to port Ja of the Zed board. The other PMOD, ALS
is connected to port Jb. To display the acquired and processed The result accuracy depends on the time conversion. The
data, OLEDrgb is used which is connected to port Jc. In order temperature and relative humidity can be calculated using
to reset the system, one reset block, „Processor System Reset‟ equations 1 and 2, respectively [3].
is used.
Temperature (0C) = *1650C – 400C (1)
In the proposed system, we can view these parameters, in
the hyper terminal. Hence, in its Peripheral I/O pins, one Relative Humidity (%RH) = *100%RH (2)
UART peripheral is enabled.
After completion of the block level design, validate it and
make sure there will be no errors in the design. Then, generate
HDL wrapper for the design, after that synthesize and
implementation processes has to be done. Once if
implementation is to be done successfully, then bit stream can
be generated.
Next process is exporting the hardware including bitstream
and launch software design kit (SDK) software to create and
build the application project. Application project in the
proposed system is developed using C. Here, the zed board
consists of programmable logic (PL) and processing system
(PS) are sandwiched in single IC. The created design will be
loaded in PL, which is an ARTIX 7 FPGA. The control
process, that is accepting the input data, processes it and
displays the appropriate results at the display devices will be
done by software logic instructed to processing system.
III. HARDWARE INTERFACE
Once, application project is ready, then make sure we have
to interface PMOD Hygro to output connector A, ALS to
connector B and OLEDrgb is connected to the output
connector C as we have created our design in Fig. 2. The Fig. 3. Interfacing of HYGRO, ALS, OLEDrgb PMODs with PL via PS.

327 | P a g e
www.ijacsa.thesai.org
 (IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 11, No. 9, 2020

Fig. 4. PMODs used in Data Acquisition System.

Fig. 6. Humidity and Temperature Measurement.

It communicates with the Zed board, via serial peripheral

interface and requires a serial clock frequency (SCK) of 1
MHz and 4 MHz. When CS pin is made low, it operates in a
regular mode of operation and brings a single reading in
sixteen serial clock (SCLK) cycles [4]. The information bits
are kept on the dropping edge of the serial clock. It is valid on
the succeeding growing edge of SCLK. It consists of 3 zeroes
at starting, the 8-bits of data with the most significant bit at
first, and 4 zeroes at the end.
C. OLEDrgb Interface
Fig. 5. Interfacing of HYGRO with Zynq Processor.
There are six ports are used between the peripheral
module, OLEDrgb to Zynq processing system via AXI
To complete the measurement of humidity and
interconnect. AXI_LITE_GPIO is connected to M03_AXI,
temperature, it is required to organize the register address to
AXI_LITE_SPI is connected to M04_AXI. Because, it is
0x02. We have to configure logic HIGH to Bit-12 to measure
connected through SPI protocol. The input clock to this
both humidity and temperature parameters. In order to set the
module is, ext_spi_clk, driven by the processing system
resolution of a temperature, configure logic LOW to Bit-10 for
through FCLK_clk0. s_axi_aclk of Hygro and s_axi_aclk of
14-bit resolution or set it to logic HIGH for resolution of 11-
ALS are connected to s_axi_aclk and s_axi_aclk2 of
bit.
OLEDrgb to have the communication appropriately.
In order to set the desired humidity measurement
The reset signal is generated from the processor reset
resolution, set the bits 9 and 8 of configuration register to 00
block to all the peripheral modules including AXI interconnect
to achieve 14-bit resolution, or set to 01 to achieve 11-bit
as shown in the Fig. 2. The output port is connected to jC in
resolution or set to 10 to achieve 8-bit resolution. The
order to interface the OLEDrgb to Zed Board as illustrated in
measurements are triggered by setting an address pointer to
Fig. 8.
0x00 then, measurements waiting period will be completed,
depending on the time conversion and read the output data [3]. IV. DEVELOPMENT OF APPLICATION SOFTWARE
Fig. 6 shows the timing signals under read operation when
data is ready. The process, export the created project into the software
development kit using the Vivado software, will create
B. ALS Interface “Hardware Base system” or “Hardware Platform”. Once, the
The peripheral module ALS is a single ambient light hardware platform is created, software system is used or
sensor. When the ALS is exposed with light, it will convert developed to complete the real time application. This software
the light into voltage signal. This analog voltage signal is system is in the form of three layers over the hardware system
converted into 8-bits of digital data by the analog to digital base [10] as illustrated in Fig. 7. The second layer is board
converter. The range of values from 0 to 255 indicates low support package layer, which will set functions and drivers of
light level to a high light level [4]. low level that are needed by following layer over the board
support package layer to communicate with hardware used.
The pin configuration of ALS [4], Pin.1 is Chip Select Application software is created with C or C++ and it will run
(CS), Pin.2 is no connection (NC), Pin.3 is Serial Data Out over the operating system and it is the highest level of
(SDO), Pin.4 is Serial Clock (SCK), Pin.5 is ground pin, and abstraction from the bottom hardware [1], [10].
Pin.6 is Power Supply, VCC (3.3V/5V). The operating voltage
range of this ALS is 2.7V to 5.25V. However, the proposed
work requires 3.3V.

328 | P a g e
www.ijacsa.thesai.org
 (IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 11, No. 9, 2020

TABLE I. (B). LUT AS LOGIC, MEMORY AND FLIPFLOP PAIRS

LUT as LUT as LUT Flip Flop
Name Logic Memory Pairs
(53200) (17400) (53200)
DAC_i 1901 106 1130
PmodALS_0 370 17 265
PmodHYGRO_0 570 10 273
PmodOLEDrgb_0 414 17 300
PS7_Axi_peripheral 532 61 272
Rst_ps7_0_100M 17 1 15

TABLE I. (C). IOBS AND LOGIC UTILIZATION

Bonded Bonded
Fig. 7. Software Layers Over the Custom Hardware [10]. ILOGIC OLOGIC
Name IOB IOPADS
(200) (200)
(200) (130)
V. RESULTS AND DISCUSSION DAC_i 1901 106 1130 2
The Xilinx software development kit is used to create our PmodALS_0 370 17 265 1
data acquisition application. Compilation and debugging
processes are also done within this tool. In the proposed PmodHYGRO_0 570 10 273 0
application, we have connected three peripheral modules: PmodOLEDrgb_0 414 17 300 1
Hygro, ALS and OLEDrgb as illustrated in Fig. 3. The PS7_Axi_peripheral 532 61 272 0
application software is developed to read the temperature and
Rst_ps7_0_100M 17 1 15 0
humidity from Hygro Pmod and ambient light intensity from
ALS Pmods respectively. These three data values are The area of the proposed design occupied in the Artix 7
processed and displayed on OLEDrgb display Pmod as shown FPGA is represented in Table I. The LUT area for total DAC
in Fig. 8. is 3.77%. Slice registers occupy 2.38%, total Slices occupy
5.59%.The detailed utilization report for LUT, Slice Registers,
Muxes and Slices are illustrated in Table I(A). LUT as Logic,
Memory and FlipFlop Pairs reports are specified in Table I(B).
The number of input and output blocks and input logic and
output logics are illustrated in Table I(C).
The proposed design, timing constraints are met
satisfactorily as specified in the Table II. All the worst
negative slacks for setup, hold and pulse widths are positive.
There are zero negative slacks for setup, hold and pulse
widths. Numbers of Failing end points are also zero. There
were total 5636 end points for each setup and hold. And for
pulse width, total end points are 2687.
The comparison of proposed system that is Reconfigurable
Fig. 8. Display of Temperature, Humidity and Ambient Light Intensity on
data acquisition with respect to ASIC based data acquisition
OLEDrgb. systems are illustrated in Table III and Fig. 9. Therefore, the
summarized advantages of Reconfigurable data acquisition
TABLE I. UTILIZATION REPORT systems are listed as follows.
Table I(A). LUT, Slice Registers, Muxes and Slices 1) The existed data acquisition systems are implemented
Slice Slice F7 F8 with ASIC (Application Specific Integrated Circuit) based,
Slice
Name LUTs Registers Muxes Muxes which does not include the enhancement facility in increasing
(13300)
(53200) (106400) (26600) (13300) the number of channels and the corresponding data acquisition
DAC_i 2007 2530 8 4 473 and signal conditioning circuitry enhancement. The non-
PmodALS_0 387 590 0 0 166 recurring engineering cost and time to market is very high.
PmodHYGRO_0 580 541 8 4 211 Whereas the proposed system is implemented with
Reconfigurable device, and the corresponding cost and
PmodOLEDrgb_0 431 666 0 0 174
development time is very less. Hence, it is best suitable for
PS7_Axi_peripheral 593 696 0 0 242 low and medium industrial applications and even academic
Rst_ps7_0_100M 18 37 0 0 13 institutions can develop such systems.

329 | P a g e
www.ijacsa.thesai.org
 (IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 11, No. 9, 2020

2) The software and hardware used in the proposed VI. CONCLUSION

system is suitable for low powered and high-speed The Reconfigurable SoC based data acquisition system is
applications which can meet with ASIC based designs. designed, implemented and made successfully functional
3) Many embedded systems used LCD, LED or monitors using Xilinx Vivado System Design Suite 2018.1, Xilinx
for data acquisition purpose. Whereas in the proposed system, Software Development Kit (SDK), Zed development board,
OLEDrgb is used for display of results which is a tiny, clarity and three peripheral modules. Advantages of this proposed
colour display of 94 X 64 pixels [5]. system has been clearly discussed with the comparison
analysis of Reconfigurable data acquisition with respect to
TABLE II. DESIGN TIMING SUMMARY REPORT ASIC based data acquisition system. It is a cost effective, low
powered and high accurate Reconfigurable embedded
Table II. Timing Report application.
Setup Hold Pulse Width
ACKNOWLEDGMENT
Worst Negative Slack Worst Hold Slack Worst Pulse Width Slack
(WNS): 2.417ns (WHS): 0.026ns (WPWS): 3.750ns This work has been carried out by using the equipment
Total Negative Total Slack(TNS);
Worst Pulse Width sanctioned by TEQIP Phase-III sponsored fund from the
Negative Slack JNTUH. Therefore, the authors of this paper acknowledge the
Slack(TNS); 0.00ns 0.00ns
(WPWS):0.00ns
funding source, JNTUH, Kukatpalli and the supporting
Number of Failing Number of Failing Number of Failing
Endpoints: 0 Endpoints: 0 Endpoints: 0
institute, Sreenidhi Institute of Science and Technology for
Total Number of Total Number of Total Number of
giving the encouragement and providing facilities to do
Endpoints: 5636 Endpoints: 5636 Endpoints: 2687 research and development activities.
REFERENCES
[1] Louise H. Crockett, Rose A. Elloit, Martin A. Enderwitz, David
Northcote “The Zynq Book Tutorials for Zybo and Zed Board”,
Department of Electronic and Electrical Engineering, University of
Strathclyde Glasgow, Scotland, UK, August 2015.
[2] Survey on developing data acquisition system using ZYNQ architecture,
ZedBoard_HW_UG_v1_9.pdf, ZedBoard (ZynqTM Evaluation and
Development) Hardware‟s Users Guide, Version 1.9 January 29th, 2013.
[3] Pmod-hygro-rm.pdf, PMOD HYGRO Reference Manual, Revised
February 22, 2017.
[4] pmodals_rm.pdf., PmodALSTM, Reference Manual, Revised April 15,
2016.
[5] Pmodoledrgb_rm.pdf, PmodOLEDrgb TM, Reference Manual, Revised
April 26, 2016.
Fig. 9. ASIC Versus FPGA based Data Acquisition Systems. [6] Daniel Roggow, Paul Uhing, Phillip Jones and Joseph Zambreno, “A
project-based embedded systems design course using a reconfigurable
TABLE III. COMPARISON ANALYSIS OF RECONFIGURABLE DATA soc platform”, 2015 IEEE International Conference on Microelectronics
ACQUISITION SYSTEM VS ASIC BASED DATA ACQUISITION SYSTEM Systems Education (MSE) , 10.1109/MSE.2015.7160005, ISBN: 978-1-
4799-9915-6, 2015.
ASIC based Data Acquisition Reconfigurable Data
S.No. [7] AXI Reference Guide, UG761(v13.4) January 18, 2012.
SoC Acquisition SoC
[8] Ye Fan, “FPGA based data acquision system”, 2011 IEEE International
Once the circuit design is taped In Reconfigurable data Conference on Signal Processing, Communications and Computing
out, alteration is not possible. acquisition, FPGAs are used. (ICSPCC), DOI:10.1109/ICSPCC.2011.6061756, Electronic ISBN: 978-
1
Hence, it is less flexible for With these, either partial or full 1-4577-0894-7, October 2011.
enhancement of the designs reconfiguration is possible.
[9] Aboli Audumbar Khedkar, Khade. R.H. “High speed FPGA-based data
Not suitable for applications These are extremely suitable acquisition system”, Microprocessors and Microsystems, Volume 49,
where design up gradation is very for Radars, mobile base Pages 87-94, March 2017.
2
much required such as Radars, stations, high computing data
[10] Louse H.Crockett, Ross A.Elliot, Martin A. Enderwitz, Robert
mobile applications etc. applications etc.
W.Stewart “The Zynq Book Embedded Processing with the ARM
These are not suitable for cortex-A9 on the Xilinx, Zynq-7000 All Programmable SoC” 1st
Best suitable for prototype and
3 prototype of a design. ASICs are Edition, Published by Strathclyde Academic Media in July 2014.
validation of a design.
also prototype by FPGAs. [11] Rajasekaran, C., Jeyabharath, R. and Veena, P. “FPGA SoC Based
Difficult for low and medium Multichannel Data Acquisition System with Network Control Module”,
level industries because of Many advantages such as less Circuits and Systems, 8, 53-75, ISSN Online: 2153-1293, 2017.
unbearable NRE cost. Hence, it is NRE cost, easy barrier to [12] S Khan et al 2013 FPGA Based High Speed Data Acquisition System
4
a hard barrier to design entry and design entry, less time required for Electrical Impedance Tomography, J. Phys.: Conf. Ser. 434 012081.
lot of time is required to market to market.
the end product. [13] Dharmavaram Asha Devi, Tirumala Satya Savithri, Sai Sugun.L,
“Satellite Tracking Data Acquisition System using Reconfigurable
With latest 7-series FPGAs, SoC”, Journal of Xi‟an University of Architecture and Technology”,
No doubt these are energy these are also more or less Volume XII, Issue III, March 2020.
efficient, high performance and equivalent to ASIC based
5 [14] M. Bhavani and D. A. Devi, "Design of smart Monitor for automobiles
cost per unit will be less with designs in terms of
bulk volume production. performance and power using FPGA based Data Logger," 2019 International Conference on
consumption Communication and Electronics Systems (ICCES), Coimbatore, India,
2019, pp. 1940-1945, doi: 10.1109/ICCES45898.2019.9002034.

330 | P a g e
www.ijacsa.thesai.org
 (IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 11, No. 9, 2020

[15] Dharmavaram Asha Devi, Muchukota Suresh Babu, “Design and [18] Talal Bonny, Tamer Rabie, Mohammed Baziad, and Walid Balid.
Analysis of Power Efficient 64-Bit ALCCU”, International Journal of “SHORT: Segmented Histogram Technique for Robust Real-Time
Recent Technology and Engineering (IJRTE), ISSN: 2277-3878, Object Recognition”, Journal of Multimedia Tools and Applications.
Volume-8 Issue-2, pp-162-166, July 2019. [19] D. A. Devi and N. S. Rani, "Design and Implementation of custom IP
[16] Talal Bonny. “Chaotic or Hyper-chaotic Oscillator? Numerical solution, for Real Time Clock on Reconfigurable Device," 2019 Third
circuit design, Matlab HDL-coder implementation, VHDL code, security International Conference on Inventive Systems and Control (ICISC),
analysis, and FPGA realization”, Journal of Circuits, Systems, and Coimbatore, India, 2019, pp. 414-418, doi:
Signal Processing. 10.1109/ICISC44355.2019.9036428.
[17] Talal Bonny and Qasim Nasir, “Clock Glitch Fault Injection Attack on [20] D. A. Devi and L. S. Sugun, "Design, implementation and verification of
an FPGA-based Non-autonomous Chaotic Oscillator”, Journal of 32-Bit ALU with VIO," 2018 2nd International Conference on Inventive
Nonlinear Dynamics. Systems and Control (ICISC), Coimbatore, 2018, pp. 495-499, doi:
10.1109/ICISC.2018.8399122.

331 | P a g e
www.ijacsa.thesai.org
View publication stats