LAB-MANUAL

IV Year VIII SEM ECE

8EC7A VLSI AND OFC LAB

DEPARTMENT OF
ELECTRONICS & COMMUNICATION
ENGINEERING
 INDEX

S.NO CONTENTS PAGE

NO.

Ex 1.1 :Introduction to VHDL

Ex 1.2 : Design 2-input NAND and NOR using VHDL . Obtain its static
and dynamic analysis for speed and power dissipation
Exp:- 1
Ex 1.3: Simulation of XOR gate using VHDL code through Xilinx

Sample Viva Question

Ex 2.1:Write a VHDL code for Half Adder

Exp:- 2 Ex 2.2:Write a VHDL code for Full Adder

Sample Viva Question

Design a SR-latch and D-latch using CMOS. Obtain its static and dynamic

Exp:- 3 analysis for speed and power dissipation.

Sample Viva Question

Objectives :- Combinational Multiplexer

4.1:Write VHDL code for 4*1 Multiplexer
Exp:-4
4.2:Write VHDL code for 1*4 De-multiplexer
Sample Viva Question
Design a 4- bit Serial in-serial out shift register. Obtain its number of gates,
area, and speed and power dissipation
Exp:-5
Sample Viva Question

Exp:-6 Design a 4-bit Comparator using VHDL code in Behavioral type of

modeling

Sample Viva Questions

Measurement of Propagation loss and numerical aperture.

Exp:- 7 Sample Viva Question

 To set up Fiber Optic Analog Link.

Exp:- 8 Sample Viva Question

To set up Fiber Optic Digital link.

Exp:- 9 Sample Viva Question

To study the characteristic of laser diode and light emitting diode.

Exp:- 10 Sample Viva Question

 DO’S

1. Student should get the record of previous experiment checked before starting the new
experiment.

2. Read the manual carefully before starting the experiment.

3. Before starting the experiment, get circuit diagram checked by the teacher.

4. Before switching on the power supply, get the circuit connections checked.

5. Get your readings checked by the teacher.

6. Apparatus must be handled carefully.

7. Maintain strict discipline.

8. Keep your mobile phone switched off or in vibration mode.

9. Students should get the experiment allotted for next turn, before leaving the lab.

DON’TS

1. Do not touch or attempt to touch the mains power supply wire with bare hands.
2. Do not overcrowd the tables.
3. Do not tamper with equipments.
4. Do not leave the lab without permission from the teacher.
INSTRUCTIONS TO THE STUDENTS

GENERAL INSTRUCTIONS

 Maintain separate observation copy for each laboratory.

 Observations or readings should be taken only in the observation copy.
 Get the readings counter signed by the faculty after the completion of the experiment.
 Maintain Index column in the observation copy and get the signature of the facult y
before leaving the lab.

BEFORE ENTERING THE LAB

 The previous experiment should have been written in the practical file, without
which the students will not be allowed to enter the lab.
 The students should have written the experiment in the observation copy that they
are supposed to perform in the lab.
 The experiment written in the observation copy should have aim, apparatus
required, circuit diagram/algorithm, blank observation table (if any), formula (if
any), programme (if any), model graph (if any) and space for result.

WHEN WORKING IN THE LAB

 Necessary equipments/apparatus should be taken only from the lab assistant by
making an issuing slip, which would contain name of the experiment, names of
batch members and apparatus or components required.
 Never switch on the power supply before getting the permission from the faculty.

BEFORE LEAVING THE LAB

 The equipments/components should be returned back to the lab assistant in good
condition after the completion of the experiment.
 The students should get the signature from the faculty in the observation copy.
They should also check whether their file is checked and counter signed in the index.
 EXPERIMENT 1
Objective 1.1 :Introductions to VHDL

THEORY: HDL stands for very high-speed integrated circuit hardware description language.
Which is one of the programming language used to model a digital system by dataflow,
behavioral and structural style of modeling. This language was first introduced in 1981 for the
department of Defense (DoD) under the VHSIC programe. In 1983 IBM, Texas instruments and
Intermetrics started to develop this language. In 1985 VHDL 7.2 version was released. In 1987
IEEE standardized the language.
Describing a design:

In VHDL an entity is used to describe a hardware module.

An entity can be described using,

1. Entity declaration.

2. Architecture.

3. Configuration

4. Package declaration.

5. Package body.

Let‟s see what are these?

Entity declaration:

It defines the names, input output signals and modes of a hardware module.

Syntax:
entity entity_name is
 Port declaration;
end entity_name;
An entity declaration should starts with „entity‟ and ends with „end‟ keywords.

Ports are interfaces through which an entity can communicate with its environment. Each
port must have a name, direction and a type. An entity may have no port declaration also. The
direction will be input, output or inout.

In Port can be read

Out Port can be written
Inout Port can be read and written
Buffer Port can be read and written, it
can have only one source.

Architecture:

It describes the internal description of design or it tells what is there inside design. Each entity
has atleast one architecture and an entity can have many architecture. Architecture can be
described using structural, dataflow, behavioral or mixed style. Architecture can be used to
describe a design at different levels of abstraction like gate level, register transfer level (RTL) or
behavior level.

Syntax:

architecture architecture_name of entity_name

architecture_declarative_part;
begin
Statements;
end architecture_name;
 Here we should specify the entity name for which we are writing the architecture body. The
architecture statements should be inside the begin and end keyword. Architecture declarative part
may contain variables, constants, or component declaration.

Configuration:

If an entity contains many architectures and any one of the possible architecture binding with
its entity is done using configuration. It is used to bind the architecture body to its entity and a
component with an entity.

Syntax:

configuration configuration_name of entity_name is

block_configuration;
end configuration_name.

Block_configuration defines the binding of components in a block. This can be written as

for block_name
component_binding;
end for;

block_name is the name of the architecture body. Component binding binds the components of
the block to entities. This can be written as,

for component_labels:component_name
block_configuration;
end for;

Package declaration:

Package declaration is used to declare components, types, constants, functions and so on.

Syntax:
 package package_name is
Declarations;
end package_name;

Package body:

A package body is used to declare the definitions and procedures that are declared in
corresponding package. Values can be assigned to constants declared in package in package
body.

Syntax:

package body package_name is

Function_procedure definitions;
end package_name;

The internal working of an entity can be defined using different modeling styles inside
architcture body. They are

1. Dataflow modeling.

2. Behavioral modeling.

3. Structural modeling.

Structure of an entity:
Let‟s try to understand with the help of one example.

Dataflow modeling:

In this style of modeling, the internal working of an entity can be implemented using
concurrent signal assignment.

Let‟s take half adder example which is having one XOR gate and a AND gate.

Library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ha_en is
port (A,B:in bit;S,C:out bit);
end ha_en;

architecture ha_ar of ha_en is

begin
S<=A xor B;
C<=A and B;

end ha_ar;

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called
STD_ULOGIC. use is a keyword, which imports all the declarations from this package. The
architecture body consists of concurrent signal assignments, which describes the functionality of
the design. Whenever there is a change in RHS, the expression is evaluated and the value is
assigned to LHS.
Behavioral modeling:

In this style of modeling, the internal working of an entity can be implemented using set of
statements.

It contains:

 Process statements
 Sequential statements
 Signal assignment statements
 Wait statements

Process statement is the primary mechanism used to model the behavior of an entity. It contains
sequential statements, variable assignment (:=) statements or signal assignment (<=) statements
etc. It may or may not contain sensitivity list. If there is an event occurs on any of the signals in
the sensitivity list, the statements within the process is executed.

Inside the process the execution of statements will be sequential and if one entity is having two
processes the execution of these processes will be concurrent. At the end it waits for another
event to occur.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ha_beha_en is
port(
A : in BIT;
B : in BIT;
S : out BIT;
C : out BIT
);
end ha_beha_en;

architecture ha_beha_ar of ha_beha_en is

 begin
process_beh:process(A,B)
begin
S<= A xor B;
C<=A and B;
end process process_beh;

end ha_beha_ar;

Here whenever there is a change in the value of a or b the process statements are executed.

Structural modeling:

The implementation of an entity is done through set of interconnected components.

It contains:

 Signal declaration.
 Component instances
 Port maps.
 Wait statements.

Component declaration:

Syntax:

component component_name [is]

List_of_interface ports;
end component component_name;

Before instantiating the component it should be declared using component declaration as shown
above. Component declaration declares the name of the entity and interface of a component.

Let‟s try to understand this by taking the example of full adder using 2 half adder and 1 OR
gate.
 library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity fa_en is
port(A,B,Cin:in bit; SUM, CARRY:out bit);
end fa_en;

architecture fa_ar of fa_en is

component ha_en
port(A,B:in bit;S,C:out bit);

end component;

signal C1,C2,S1:bit;

begin

HA1:ha_en port map(A,B,S1,C1);

HA2:ha_en port map(S1,Cin,SUM,C2);
CARRY <= C1 or C2;

end fa_ar;

The program we have written for half adder in dataflow modeling is instantiated as shown above.
ha_en is the name of the entity in dataflow modeling. C1, C2, S1 are the signals used for internal
connections of the component which are declared using the keyword signal. Port map is used to
connect different components as well as connect components to ports of the entity.

Component instantiation is done as follows.

 Component_label: component_name port map (signal_list);

Signal_list is the architecture signals which we are connecting to component ports. This can be
done in different ways. What we declared above is positional binding. One more type is the
named binding. The above can be written as,

HA1:ha_en port map(A => A,B => B, S => S1 ,C => C1 );

HA2:ha_en port map(A => S1,B => Cin, S=> SUM, C => C2);

Test bench:

The correctness of the above program can be checked by writing the test bench.

The test bench is used for generating stimulus for the entity under test. Let‟s write a simple test
bench for full adder.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity tb_en is

end tb_en;

architecture tb_ar of tb_en is

signal a_i,b_i,c_i,sum_i,carry_i:bit;

begin

eut: entity work.fa_en(fa_ar)

port map(A=>a_i,B=>b_i,Cin=>c_i,SUM=>sum_i,CARRY=>carry_i);

stimulus: process
begin
a_i<='1';b_i<='1';c_i<='1';
wait for 10ns;
a_i<='0';b_i<='1';c_i<='1';
wait for 10ns;
a_i<='1';b_i<='0';c_i<='0';
wait for 10ns;
 if now=30ns then
wait;
end if;

end process stimulus;

end tb_ar;

Here now is a predefined function that returns the current simulation time

What we saw upto this is component instantiation by positional and by name. In this test
bench example the entity is directly instantiated. The direct entity instantiation syntax is:

Component_label: entity entity_name (architecture_name)

port map(signal_list);
 EXPERIMENT 1.2
Objective 1.2:Design 2-input NAND, NOR and XOR using VHDL . Obtain its static and
dynamic analysis for speed and power dissipation.

APPARATUS: Xilinx ISE Design Suite 12.1

TRUTH TABLE

a b c=a.b

0 0 0

0 1 0

1 0 0

1 1 1

VHDL Module Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity vikas is

port (a: in STD_LOGIC;

b: in STD_LOGIC;

c: out STD_LOGIC);

end vikas;

architecture Behavioral of vikas is

begin

process(a,b)

begin

c <= a nand b;
 end process;

end Behavioral;

RESULT: We have successfully performed AND gate operation and drawn its characteristics.
 Experiment No:- 1.3

OBJECTIVE 1.3: Simulation of XOR gate using VHDL code through Xilinx.

APPARATUS: Xilinx ISE Design Suite 12.1

TRUTH TABLE:

a b c=a OR b

0 0 0

0 1 1

1 0 1

1 1 1

VHDL Module Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity vikas is

port (a: in STD_LOGIC;

b: in STD_LOGIC;

c: out STD_LOGIC);

end vikas;

architecture Behavioral of vikas is

begin

process(a,b)

begin

c <= a xor b;
 end process;

end Behavioral;

RESULT: We have successfully performed OR gate operation and drawn its characterstics.
SAMPLE VIVA QUESTIONS

Q 1. What do you mean by a 3 input NAND gate.

Q2. Explain the truth table of 3 input NAND gate.

Q3. Draw the gate level implementation of NAND gate using NOR gate.

Q 4. Draw the gate level implementation of NOT gate using NAND gate.

Q5. Draw the gate level implementation of OR gate using NAND gate.

Q6. Draw the gate level implementation of AND gate using NAND gate.

Q7. Draw the gate level implementation of NOR gate using NAND gate.

Q8. Draw the gate level implementation of XOR gate using NAND gate.

Q9. Draw the gate level implementation of XNOR gate using NAND gate.

Q 10 . What do you mean by an invert AND logic.

Q11. Draw the gate level implementation of AND gate using NOR gate

Q12.Draw the gate level implementation of OR gate using NOR gate

Q13. Why NAND and NOR gate are called universal gate.

Q14. Realize the XOR using minimum number of NAND gate.

Q15. Give the truth table for XNOR.

 Experiment 2.1

OBJECT- : Perform and draw the RTL and Technology circuit for the

2.1 Objective:- Write VHDL code for Half Adder

2.2 Objective:- Write VHDL code for Full Adder

APPARATUS: Xilinx ISE Design Suite 12.1

VHDL CODE-

APPARATUS: Xilinx ISE Design Suite 12.1

TRUTH TABLE:

a b c= a.b s

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

VHDL Module Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity vikas is

port (a: in STD_LOGIC;

b: in STD_LOGIC;

c: out STD_LOGIC;

s: out STD_LOGIC);

end vikas;
 architecture Behavioral of vikas is

begin

process(a,b)

begin

s <= a xor b;

c <= a and b;

end process;

end Behavioral;

Circuit Diagram:--
RESULT: We have successfully performed Half Adder operation and drawn its characterstics

EXPERIMENT 2.2

Objective 2.2: VHDL code for Full Adder

APPARATUS: Xilinx ISE Design Suite 12.1

TRUTH TABLE:

a b c cout s

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0
1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

VHDL Module Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity vikas is

port (a: in STD_LOGIC;

b: in STD_LOGIC;

c: in STD_LOGIC;

cout: out STD_LOGIC;

s: out STD_LOGIC);

end vikas;

architecture Behavioral of vikas is

begin

process(a,b,c)

begin

s <= a xor b xor c;

c <= (a and b) or (b and c) or (c and a);

end process;

end Behavioral;
Circuit Diagram:--

RESULT: We have successfully performed Full Adder operation and drawn its characterstics
SAMPLE VIVA QUESTIONS

Q1. Explain the working of half adder.

Q2. Draw the circuit of full adder using half adder.

Q3. Why we use half adder.

Q4. Give the gate table implementation of half adder.

Q5. Explain the truth table of half adder.

Q6. How can you implement half adder in multiplication of two binary number.

Q7. What is half adder.

Q8. What is full adder.

Q9. What are the application of adder

Q10. What is a half subtractor.

Q11. What is a full subtractor

Q12. What are the applications of subtractor.

Q13. Obtain the minimal expression for half adder circuit.

Q14. Realize a full adder using two half adder.

Q15. Realize a full subtractor using two half Subtractor

 Experiment 3

OBJECT: Design a SR-latch and D-latch using VHDL. Obtain its static and dynamic analysis
for speed and power dissipation.

APPARATUS: Xilinx ISE Design Suite 12.1

VHDL CODE-

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity FDRS is

port(Q : out std_ulogic;

C : in std_ulogic;

R : in std_ulogic;

S : in std_ulogic;

Clear: in std_ulogic

);

end FDRS;

architecture FDRS_arch of FDRS is

begin

process(C,Clear)

begin

if (rising edge(Clear)) then

Q <= '0';

end if;

if (rising_edge(C)) then

if (Clear = '1')

Q <=0;

elsif (R = '1') then

Q <= '0' ;

elsif (S = '1') then

Q <= '1' ;

end if;end if;

end process;end FDRS_arch;

 SAPMLE VIVA QUESTIONS

Q1. What do you mean by latch.

Q2. What do you mean by flip flop.

Q3. Give the gate level implementation of D-latch.

Q4. Give the gate level implementation of D-latch using NAND gate.

Q5. Explain the truth table of D-latch.

Q6. What is the basic difference between a latch and a flip flop.

Q7. What do you mean by synchronous and asynchronous triggering?

Q8. What do you mean by edge triggering?

Q9. What do you mean by level triggering?

Q10. How can you convert D-latch into SR flip flop.

Q11. How can you convert D-latch into JK flip flop.

Q12. How can you convert D-latch into T flip flop.

Q13. Implement Master Slave D flip flop using D latch.

Q14. What do you mean by positive edge triggering and negative edge triggering.

Q15. Give example for synchronous and asynchronous input.

 EPERIMENT 4
OBJECT 4.1 : Write VHDL code for 4:1 Multiplexer

APPARATUS: Xilinx ISE Design Suite 12.1

VHDL CODE-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity abcde is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;

i2 : in STD_LOGIC;

i3 : in STD_LOGIC;

sel : in STD_LOGIC_vector (1 downto 0);

y : out STD_LOGIC);

end abcde;

architecture Behavioral of abcde is

begin

process(i0,i1,i2,i3,sel)

begin

case sel is

when"00"=> y <=i0;

when"01"=> y <=i1;

when"10"=> y <=i2;

when others=> y <=i3;

end case;

end process;

end Behavioral;

Circuit Diagram:--
 Experiment 4.2
OBJECT 4.2 : Write VHDL code for 1:4 De- Multiplexer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demux1_4 is
port (
out0 : out std_logic; --output bit
out1 : out std_logic; --output bit
out2 : out std_logic; --output bit
out3 : out std_logic; --output bit
sel : in std_logic_vector(1 downto 0);
bitin : in std_logic --input bit
);
end demux1_4;

architecture Behavioral of demux1_4 is

begin
process(bitin,sel)
begin
case sel is
when "00" => out0 <= bitin; out1 <= '0'; out2 <= '0'; out3 <='0';
when "01" => out1 <= bitin; out0 <= '0'; out2 <= '0'; out3 <='0';
when "10" => out2 <= bitin; out0 <= '0'; out1 <= '0'; out3 <='0';
when others => out3 <= bitin; out0 <= '0'; out1 <= '0'; out2 <='0';
end case;
end process;

end Behavioral;
 Sample Viva Question

Q1.Draw the block diagram for 4:1 Mux

Q2.Draw the block diagram for 1:4 Demux
Q3.Write characteristic table for 1:4 Demux.
Q4.What is application of a digital multiplexer?
Q5.Q1.Explain difference between Multiplexer and De-multiplexer?
Q6.What is ripple counter?
Q7.What is meant by stable state?
Q8.What is Unstable State?
Q9.What is Encoder?
Q10.What is Entity?
Q11.Write syntax for Entity Declaration?
Q12.Design 16 : 1 MUX using 4 : 1 MUX ?
Q13.What is IEEE?
Q14.Write modeling style in VHDL.
Q15.Write state reduction technique in VHDL.
 EXPERIMENT 5

OBJECTIVE: Design a 4- bit Serial in-serial out shift register. Obtain its number of gates,
area, and speed and power dissipation

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity siso_behavior is

port(

din : in STD_LOGIC;

clk : in STD_LOGIC;

reset : in STD_LOGIC;

dout : out STD_LOGIC

);

end siso_behavior;

architecture siso_behavior_arc of siso_behavior is

begin

siso : process (clk,din,reset) is

variable s : std_logic_vector(3 downto 0) := "0000" ;

begin

if (reset='1') then

s := "0000";

elsif (rising_edge (clk)) then

s := (din & s(3 downto 1));

 dout <= s(0);

end if;

end process siso;

end siso_behavior_arc;
 SAMPLE VIVA QUESTIONS

Q1. What do you mean by register?

Q2. Explain the block diagram of 4 bit register.

Q3. What do you mean by a SISO register?

Q4. Explain the block diagram of 4 bit shift register.

Q5. What do you mean by shift register?

Q6. Write down ant three types of register?

Q7. What do you mean by a counter?

Q8. What is the difference between counter and register?

Q9. What do you mean by synchronous Counter?

Q10. What is the difference between serial and parallel transfer?

Q11. Why we use left shift and right shift operation?

Q12. What are PISO, SIPO and SISO with respect to shift register?

Q13. What is the use of shift register?

Q14. Is the SISO is efficient than any other register?

Q15. The bit sequence 0010 is serially entered (right most first bit) into 4 bit parallel out shift
register that is initially clear. What are the Q outputs after two pulses?
 EXPERIMENT 6
OBJECTIVE: Design a 4-bit Comparator. Obtain its number of gates, area, and
speed and power dissipation

VHDL CODE:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE Behavior OF compare IS
BEGIN
AeqB <= „1‟ WHEN A = B ELSE „0‟ ;
AgtB <= „1‟ WHEN A > B ELSE „0‟ ;
AltB <= „1‟ WHEN A < B ELSE „0‟ ;
END Behavior ;

OR
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comparator_4bit is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
equal : out STD_LOGIC;
greater : out STD_LOGIC;
lower : out STD_LOGIC
);
end comparator_4bit;

architecture comparator_4bit_arc of comparator_4bit is

begin

comparator : process (a,b) is

begin
 if (a=b) then
equal <= '1';
greater <= '0';
lower <= '0';
elsif (a<b) then
equal <= '0';
greater <= '0';
lower <= '1';
else
equal <= '0';
greater <= '1';
lower <= '0';
end if;
end process comparator;
end comparator_4bit_arc;
 Sample Viva Questions
Q1. How many 4-bit comparators are needed to construct 12-bit comparator?

Q2.What does a digital comparator mean?.

Q3. Design a 2-bit comparator using gates?

Q4. Explain the phases of a simulation?

Q5.Explain briefly about wait statement?

Q6. What is meant by multiplexer?

Q7. What are the two kinds of subprograms?

Q8. Explain briefly about operator overloading?

Q9. Write the syntax of package declaration?

Q10. Write the syntax of package body?

Q11. What are the differences between RAM and RAM?

Q12. Write the syntax for component declaration.

Q13. What is subprogram in vhdl?

Q15. Explain the types of design units.

 EXPERIMENT 7
OBJECTIVE- Measurement of propagation loss & Numerical aperture.

EQUIPMENTS:
1. OFT
2. Two channel,20MHz Oscilloscope.
3. Function Generator, 1Hz- 10MHz
4. Fiber alignment unit
5. Numerical aperture measurement unit

THEORY:

LOSSES IN OPTICAL FIBER:

INTRODUCTION

The FIBER used in OFT is multimode plastic fiber 1000 µm core diameter. Unlike its Glass-
Glass and Plastic coated Silica FIBER counterparts, this FIBER has very high attenuation. It is useful
mainly for short links such as in Local Area Networks, especially where there could be serious EMI
problems. This FIBER has been selected for the OFT because of the ease of handling it affords. While the
loss in plastic FIBER is high for all wavelength regions, the loss at 850 µm is much higher than at 650
µm. Apart from the above propagation loss in a FIBER, bending of FIBER, connectors, splices and
couplers may all contribute significantly to the losses in a FIBER optic communication link. An optical
FIBER is a circular waveguide. A small bend in a FIBER will not significantly affect the propagation
characteristic and there for the losses in the FIBER. Howver,if the FIBER is bent with a radius of
curvature smaller than a certain value (usually about a centimeter), the propagating signal may suffer
significant bending losses. Two optical FIBERs are joined using either a connector or a splice. The
alignment of the cores of the two FIBERs is critical in both the situations, as even the minutest
misalignment or gap between the FIBERs may cause significant coupling losses.

PROCEDURE

Set Up

1. The interfaces used in the experiment are summarized in table 3.1. Indentify them on the OFT with
the help of the layout diagram (Fig 3.1)
S.No. Identification Name Function Location

1 SW8 Analog/Digital Selection Switch

Should be set to ANALOG position

2 LED 850 nm LED Optical Tx1 Block

850 nm

3 LED 650 nm LED Optical Tx2 Block

650 nm LED

4 PD1 PIN Detector Optical Rx1 Block

5 JP2 PD1/PD2 Receiver Select

Posts B & A1should be shorted

6 GAIN GAIN Control Potentiometer Optical Rx1 Block

7 P11 Analog IN

ANALOG IN

8 P31 PIN Detector signal after gain Optical Rx1 Block

9 I/O1,I/O2,I/O3 Input/output BNCs and posts for

feeding in and observing signals

10 S6 Manchester Coded Data Manchester Coded Block

Coded data

S26 Received Manchester Coded Data Decoder and clock

shorting link recovery block
11 Coded data
Post A: Receiver output (Rx1/Rx2)

Post B:Input to decoder and clock

recovery block

Posts A & B should be shorted

 Table 3.1 : Interface Detail for Experiment 3

The block diagram of the circuit used in this experiment is shown in Fig. 3.2 Set the jumpers
and switches as given in Table 3.2
2. Set the switch SW8 to the ANALOG position. Ensure that the shorting plug of the jumper JP2
is across the posts B & A1 (for PD1 selection). Remove the shorting plugs from coded data
shorting links S6 in the Manchester coder block and S26 in the Decoder & clock recovery
block.

Attenuation at 850 nm

3. take the 1m FIBER ansd set up an analog link using LED 1 in the optical Tx1 block and
detector PD1 in the optical Rx1 block [850 NM LINK]. Drive a 1V p-p 10 KHz sinusoidal
signal with zero d.c. at P11. Observe the signal at P31 on tha Oscilloscope. Use the BNC I/Os
for feeding in and observing signals as described in Experiment 1. Adjust the GAIN such that
the received signal is not saturated. Do not disturb the level of the signal at the function
generator or the gain setting throughout the rest of the experiment.
4. Note the peak value of the signal received at P31 and designate it V1. Replace the 1m FIBER
by the 3m FIBER between LED1 and PD1. Againnote the peak value of the received signal
and desidnated it as V3. If α is the attenuation in the FIBER and and are the exact length
of the 1m and 3m FIBERs in meters respectively, we have

( )

Where α is in nepers/m, and P1 and P3 are received Optical power with 1m and 3m FIBER
respectively.

Compute α‟in dB/m for 850 nm wavelength using α‟=4.343α where α is in nepers/m.

Attenuation at 650 nm

Now set up the 650nm link using LED2 ,detector PD1 and the one meter FIBER. Remove the shorting
plugs from S6 and S26 and feed in a TTL signal of 10 khz at post B of S6. Observe the signal at P31 on
the oscilloscope. Adjust the GAIN such that the received at P31 and designate it as V1. Replace the one
meter FIBER between LED2 and PD1. Again, without disturbing the GAIN, note the peek value of the
receive signal and designate it as V3. Compute α‟ in dB/m for a 650 nm wavelength using the expression
given in Step 4.

NOTE=>

The propagation losses in plastic FIBER are minimum in the region of 650 nm. The loss is much higher at
850nm. This is in contrast with glass- glass FIBER where the loss at 850 nm is much lover than that at
650nm.
As mentioned earlier, this loss is much lower than that plastic FIBER and as a value close to 3dB/Km at
850nm. Glass-glass FIBER has its lowest loss at 1550nm and its value is as low as .15dB/Km.

Bending loss :-

Setup the 850nm analog link using the 1m FIBER. Drive a 1 V p-p sinusoidal signal of 10khz with zero
dc at P11 and observe the received signal at P31 on the oscilloscope. Now bend the FIBER in loop as
show in fig 3.3. Reduce the diameter of the loop slowly and observe the reduction of receive signal at
P31. Keep reducing the diameter of the loop to about 2cm and plot the amplitude of the receive signal of
the versus the diameter of the loop. [Do not reduce the loop diameter to less than 1cm.]

Coupling loss :-

Connect one end of the 1m FIBER to LED2 and the other end to the detector PD1. Drive the LED with
a10khz TTL signal at post B of S6. Not the peek signal receive at P31 and designate it as V1 [ensure that
the GAIN is low to prevent saturation.] Now disconnect the FIBER from the detector. Take the 3m
FIBER and connect one end to the detector PD1. The optical signal can be seen emerging from the other
end of the 1m FIBER. Bring the free end of the two FIBER as close as possible and align them as shown
in fig3.4 using the FIBER alignment unit. Observe that the receive signal at P31 varies as the free ends of
the FIBERs are brought closer and moved apart. Note the receive signal level with the best possible
alignment and design it as V4. Using the attenuation constant value obtained in step 4, compute the
coupling loss associated with the above coupling of the two FIBER using

η = -10log(V4 /V1 )-α‟(l3+l1)

where α‟ is the attenuation constant in dB/m at 650nm and η is the coupling loss in dB.

Now move the two FIBERs a bit apart in the FIBER Alignment Unit and note the decrease in the output
voltage. What is the coupling loss now?

8. With the two ends of the FIBER are aligned the as close as possible, place drop of
glycerine/isopropylene through the hole provided in the FIBER Alignment Unit so as to cover the FIBER
ends. Note the received signal now increases . Compute the coupling loss in the presence of the index
matching fluid like glycerine. Why does the index matching fluid effect the coupling loss?

9. Now try aligning the two FIBERs without using the FIBER Alignment Unit. How wellare you able to
align the FIBERs ? Estimate the loss as the two FIBERs are offset laterally and also when the two
FIBERs are at an angle as showh in fig. 3.5.

RESULT :-in this experiment we have measured propagation loss of a FIBER using the two FIBER
method. The losses were measured both at 850nm and 650nm, and as expected loss in a plastic FIBER is
lower at 650nm.
MEASUREMENT OF NUMERICAL APERTURE

Numerical aperture of a FIBER is a measure of the acceptance angle of the light in the FIBER
Light which is launched at angles greater than this maximum acceptance angle does not get coupled to
propagating modes in the FIBER and therefore does not reach the receiver at the other end of the FIBER .
the numerical aperture is useful in the computation of optical power coupled from an optical source to the
FIBER, from the FIBER to a photodetector , and between two FIBERs.

PROCEDURE

Set up:

1. The interfaces used in the experiment are summarized in table 4.1. identify them on the OFT With
the help of the layout diagram (fig4.1) . the block diagram is shown in fig4.2 ensure that The shorting
plugs of Tx data shorting link S4, coded data shorting link S6, and Tx clock shorting link S5 in the
Manchester code block are in position . also ensure that the shortning plug of clock select jumper JP1
is across the posts B AND A1 . a TTL signal from the multiplexer should now be
driving LED 2 in optical Tx2 block . this experiment is best performed in a less illuminated room .
2. Ensure that the cut planes of the 1m plastic FIBER are perpendicular to the axis of the FIBER . if
Required , prepare 1m of plastic FIBER as per the instruction in appendix A.

Numerical Aperture measurement:

3. Insert one end of the FIBER into the numerical aperture measurement unit as shown in fig4.3.
Adjust the FIBER such that its tip is 10mm from the screen .
4. Gently tighten the screw to hold the FIBER firmly in place .
5. Connect the other end of the FIBER to LED2 through the simplex connector . the FIBER will project
a Circular patch of red light onto the screen . let D be the distance between the FIBER tip and the
Screen . now measure the diameter of the circular patch of red light in two perpendicular Directions
(BCand DE IN FIG4.4) . the mean radius of the circular patch is given by :
X= (DE+BE)/4

Sl.no. Identification name Function Location

1 LED2 650nm 650nm LED Optical Tx2 block

2 S6 coded data Manchester coded data Manchester coder block

shorting link

Post A: Coder output

Post B: input to
transmitters
Tx1/Tx2/electrical

Post A&B : should be

 shorted

3 S4 Tx Data Multiplexed transmit Manchester coder block

data shorting link

Post A: MUX output

Post B : Manchester
coder input

Post A&B : should be

shorted

4 S5 Tx clock Transmitter clock Manchester coder block

shorting link

Post A: transmitter
clock

Post B: Manchester
coder input

Post A&B : should be

shorted

5 JP1 Clock select Transmitter clock Timing & control block

selection

Post A1&B should be

shorted

1. Carefully measure the distance D between the tip of the FIBER and the illuminated screen (OA in fig
4.3) . the numerical aperture of the FIBER is given by :
NA=sinθ= x/√

2. repeat steps 3to 6 for different values of D . compute the average value of numerical aperture

RESULT
We have successfully measured the numerical aperture of the FIBER .
 SAMPLE VIVA QUESTIONS

Q1.How far can I bend optical fiber during installation?

Q2.What happen if I bend fiber too far?

Q3.What special care is needed when connecting fiber using a connector?

Q4.When do I clean the fiber optic connector?

Q5.Why do I need to clean fiber optic connector?

Q6.What do I use to clean fiber optic connector?

Q7.What are the losses in optical fiber?

Q8.What is the basic requirement of single mode fiber?

Q9.What is Numerical Aperture?

Q10.What is Modulation?

Q11.What do you mean by Core and Cladding?

Q12.What is Step Index fiber?

Q13.What is Sellmeier Equation?

Q14.What is graded index fiber?

Q15.What is refractive index of air?

 EXPERIMENT 8
OBJECTIVE: To set up Fiber Optic Analog link.

EQUIPMENTS:
OFT

Two channel, 20MHz Oscilloscope

Function generator, 1Hz- 10MHz

INTRODUCTION:

This experiment is designed to familiarize the user with OFT. An analog fiber optics link is to be set up in
this experiment. The preparation of the optical fiber for coupling light into it and the coupling of the fiber
to the LED and detector are described in Appendix A. The LED used is an 850nm LED. The fiber is a
multimode fiber with a core diameter of 1000 micrometer. The detector is a simple PIN detector.

The LED optical power output is directly proportional to the current driving the LED. Similarly, for the
PIN diode , the current is proportional to amount of light falling on the detector. Thus , even though the
LED and the PIN diode is directly proportional to the driving current of the LED. This makes the optical
communication system a linear system.

PROCEDURE:

1. Set Up
The interfaces used in the experiment are summarized in Table1.1. Identify them on the OFT
with the help of the layout diagram (fig 1.1). The block diagram of the subsystem used in this
experiment is shown in fig 1.2 .
The 1m and 3m optical fiber provided with OFT are to be used. Ensure that the ends of the
fiber are clean and prepared as described in Appendix A.
2. Setting up the Analog Link
Set the switch SW8 to the ANALOG position. Switch the power on. The power on switch is
located at the top right hand corner.
S.NO Identification Name Function Location

1. P11 ANALOG IN Used to feed in analog sinusoidal 1 Vp-p signal Transmitter

Block

2. P32 PD1 O/P PIN Detector signal monitoring post Optical Rx1

3. P31 Received signal with amplification Optical Rx1

4. GAIN Gain adjustment Potentiometer Optical Rx1

5. SW8 Analog/Digital selection switch

(Should be sent to ANALOG position)

6. LED1 , 850nm 850nm LED (source) Optical Rx1

7. PD1 Pin Detector Optical Rx1

8. I/O1,I/O2,I/O3 Input/Output BNCs and Posts

i)For feeding in signal to the Experimentor from

function generator or

ii) to observe signal from the Experimentor on the

Oscilloscope.

Table 1.1 – Interface Details for Experiment 1

3. Feed a 1v p-p (peak to peak) sinusoidal signal at 1Khz [with zero d.c.], from a function generator , to
the ANALOG IN post P11 using the following procedure:

i)Connect a BNC-BNC cable from the function generator to the BNC socket I/O3.

ii)Connect the signal post I/O3 to the ANALOG IN post P11 using a patch cord.

With this , the signal from the function generator is fed through to the ANALOG IN signal post P11 from
the I/O3 BNC socket.
Connect one end of the 1m fiber to the LED Source LED1 in the optical Tx1 block. [See Appendix A for
the connection procedure.]

Observe the light output [red tinge] at the other end of the fiber.

Take care to keep the fiber at a distance from the eyes , and avoid direct eye contact with the infer-red
radiation as it can otherwise cause eye-damage.

Increase and decrease the amplitude level of the sinusoidal signal [from 0v to max 2v p-p].What happens
to the light output at the other end of the fiber?

Note: To observe a fed-in-signal on an oscilloscope:

i) Use a 3-plug patch cord to connect the signal post I/O3 to the required input post. Uses
the long half of the patch cord for this, and plug the center plug into I/O3 . (Here , use the
3-plug patch cord to connect signal post I/O3 to the ANALOG IN post P11 in(ii) above
,instead of a regular patch cord.)
ii) Connect a BNC-BNC cable between the BNC socket I/O2 and the oscilloscope.
iii) Connect signal posts I/O3 and I/O2 together using the short half of the 3-plug patch
cord.(The signal interface procedure is also given in Appendix H).

4.Feed a 5v p-p rectangular signal at 0.5 hz at p11. Observe the signal on the oscilloscope. Now observe
the intensity of the light output at the other end of the fibre.

Take care to keep the fibre well away from the eyes.

You will notice the light turning on and off (bright and dull ) as the driving signal observed on the
oscilloscope becomes positive and negative.

Now feed a 5v p-p sinusoidal signal at 0.5 hz at p11. Observe the variation in the brightness of the light
output at other end of the fibre as the driving signal varies sinusoidal.

5.connect the other end of the fibre to the detector PD1 in the optical Rx1 block.

6. Feed a sinusoidal wave of 1 khz ,1vp-p[with zero d.c.] from the function generator to p11.the PIN
detector output signal is available at P32 in the optical Rx1 block . vary the input signal level driving the
led and observe the received signsl at the PIN detector. Plot the received signal peak to peak amplitude
with respect to the input signal peak to peak amplitude . What is the relationship?
7. Repeat step 6 using the3m fibre instead of the 1m fibre . plot the received signal amplitude at the PIN
detector as afunction of the input signal amplitude.

The led output optical power is directly proportional to the current driving it.the PIN diode current is also
directly proportional to the optical power incident on it. Therefore,the relationship between the input
electrical signal and the output electrical signal is linear. Thus, the fibre optic link is alinear element.

Gain control :

The PIN detector signal at P32 is amplified , with amplifier gain controlled by the gain potentiometer as
shown in fig 1.3with a 3vp-p input signal at P11 as the gain potentiometer is varied.

Note that the signal at P31 gts clipped below 0v and above 3.5v as shown in fig 1.4.

Bandwidth of the fibre link :

9. measure the bandwidth of the link as follows.

Apply a 2vp-p sinusoidal signal [with zero d.c.] at P11 and observe the output at P31 . adjust gain such
that no clipping take places . vary the frequency of the input signal from 100 hz to 5 mhz and measure the
amplitude of the received signal . plot the received signal amplitude as a function of frequency [using a
logarithmic scale for frequency]. Note the frequency range for which response is flat.

10. Apply a squre wave or a triangular wave with 1vp-p and zero d.c. at the input of the transmitter [at
P11]. Vary the frequency and observe the output at P31.

Note the frequency at which the received signal starts getting distorted. Explain this using the bandwidth
obtained in the previous step.

RESULT:
We have measure the following
i)To set up analog fibre optic link.
ii) To modulate the light intensity
iii) The relationshi8p between the input signal driving the LED and the received signal at the PIN
diode
iv) The bandwidth that the link can support
 SAMPLE VIVA QUESTIONS

Q1.What is Analog Signal?

Q2.How do you classify fiber optic cable

Q3.What type of fiber is required to run at gigabit speed?

Q4.Do you see any real serious problem in splicing together fiber cables from different
manufacturer ,as long as the cable is manufactured to the same specification?

Q5.Define Fiber optics?

Q6.Is it possible to send a forward and reverse signal along the fiber?

Q7.In fiber what is “mode”?

Q8.Will a single mode connector work on multi-mode cable?

Q9.Explain what optical return losses is?

Q10.What are the problem with transmission of analog video signal over optical cable?

Q11.How does Extron handle analog video signal in its fiber optic product?

Q12.How far can we transmit an AV signal on an optical fiber?

Q13.What AV application requires fiber technology?

Q14.What is the difference between Analog and Digital Signal?

Q15.What type of losses are there in optical fiber?

 EXPERIMENT 9
OBJECTIVE: : To set up Fiber Optic Digital link.
EQUIPMENTS:
OFT

Two channel, 20MHz Oscilloscope

Function generator, 1Hz- 10MHz

INTRODUCTION:

The OFT can be used to set up two fiber optic digital links, one at a wavelength of
650 nm and the other at 850 nm. LED1, in the Optical Tx1 block, is an 850 nm LED, and LED2, in the
Optical Tx2 block, is a 650 nm LED.

PD1, in the Optical Rx1 block, is a PIN detector which gives a current proportional to the optical power
falling on the detector. The received signal is amplified & converted to a TTL signal using a comparator.
The GAIN control plays a crucial role in this conversion.

PD2, in the optical Rx2 block, is another receiver which directly gives out a TTL signal. Both the PIN
detectors can receive 650 nm as well as 850 nm signals, though their sensitivity is lower at 650 nm.

PROCEDURE:

Set up:

1. The interfaces used in the experiment are summarized in Table given below. Identify them on the
OFT with the help of layout diagram shown in fig.1
The block diagram of the subsystems used in this experiment is shown in fig 2. Set the jumpers &
switches as given in Table to start the experiment.

Setting up a digital Link at 850 nm:

2. Set the switch SW8 to the DIGITAL position.

3. Connect a 1m optical fiber between LED1 and the PIN diode PD1. Remove the shorting plugs of
the coded data shorting links, S6 in the Manchester coder block & S26 in the Decoder & clock
 recovery block. Ensure that the shortening plug of jumper JP2 is across the posts B & A1[for PD1
receiver selection].
4. Feed a TTL signal of about 20KHz from the function generator to post B of S6. Use the BNC
I/Os for feeding & observing signals. Observe the received analog signal at the amplifier post P31
on channel 1 of the oscilloscope [trigger the oscilloscope with the channel 1 signal] . note that the
signal at P31 gets cut off above 3.5V . Increase & decrease the GAIN & observe the effect.
5. Observe the received signal at post A of S26 on channel 2 of the oscilloscope while still
observing the signal at P31 on channel 1 [trigger the oscilloscope on channel 1]. Note that the
signal at S26 is the inverted version of the signal at P31. Vary the GAIN potentiometer setting.
Note that even through the received signal at P31changes with gain, the output at S26 does not.
Reduce the gain till the signal at P31 is less than 0.5V. [if the signal does not drop below 0.5V
even at the lowest gain setting,pull the fibre out slightly at the receiver to reduce the level below
0.5V]. Note that the signal at S26 as shown in fig 3. The comparator reference voltage is 0.55V,
& unless the signal amplitude is greter than 0.55V, the comparator output is high.
6. Set the signal gain such that the signal at P31 is about 2V. observe the input signal from the
function generator on channel 1 and the received TTL signal at post A of S26 on channel 2. Vary
the frequency of the input signal and observe the output response. What is the maximu bit rate
that can be transmitted on this digital link?
7. Repeat steps 4, 5 & 6 with the 3m fibre.

Setting up a digital Link at 650 nm:

8. Use the 1m fibre and insert it into LED2 . Observe the light output at the other end of the fibre
[keeping it away from the eye]. The output is bright red signal. This is because the light output at
around 650nm is in the visible range.
The other end of the fibre should now be inserted into PD1.

9. Repeat steps 4, 5 & 6 with this new link.

10. Use the 3m fibre & set up the 650nm digital link between LED2 and PD1. Repeat 4, 5, & 6.

Setting up a TTL to TTL digital Link at 650 nm:

11. Change the shorting plug in jumper JP2 across the posts B & A2 [for selection of PD2 receiver].
Use the 1m fiber to connect LED2 & optical receiver PD2.
12. Feed a TTL signal of 20KHz at post B of S6 and observe the received TTL signal at post A S26.
Display both the signals on oscilloscope on channels 1 & 2 respectively [triggering with channel
1]. Note that the GAIN control does not play any role now in the operation of the link. The
receiver at PD2 is an integrated PIN diode & comparator that directly gives out a TTL signal.
Vary athe frequency & find the maximum bit rate that can be transmitted on this link.
13. Repeat steps 11 & 12 using 3m fibre.

Setting up a 850nm TTL to Direct digital Link:

14. Use the 1m fibre to connect LED1 & PD2. Feed a TTL signal at 20KHz at post B of S6 and
observe the received signal at post A of s26. Display both the signals on the oscilloscope. An
850nm TTL to direct digital link is obtained. Vary the frequency & find the maximum bit-rate
that can be transmitted on this link.
15. Repeat step 14 with 3m fibre.
Comparing responsitivity of PIN diode at 850 nm and 650nm:

16. Change the shorting plug in JP2 to connect A1 and B(for PD1 receiver selection). Using the 1m
fibre connect LED1 (850nm) and PD1. Let the GAIN control be at the minimum level. Feed a
20KHz TTL signal at post B of S6. Measure the peak to peak voltage at P31 & designated it as
V1.
17. Now connect the fibre between LED2 (650nm) & PD1 without changing any other setting.
Measure the peak to peak voltage at P31 & designated it as V2.
18. The factory setting for the light output at the end of 1m fibre for LED1 is 3db higher (two times)
than that of LED2. The PIN diode current “I” can be written as
I= ρP

Where P is the optical intensity of the light fallin on the detector & ρ is the responsitivity. The
voltage at P31 is directly proportional to the PIN diode current “I”. Using the results of steps 16
& 17, compare the responsitivity of the diode at 650 nm & 850 nm using the expression

V1/V2={ρ1P1/ρ2P2}

Where P1 is twice P2 (at factory setting) & ρ1and ρ2 are responsitivities of the diode at 850 nm
& 650 nm respectively.

RESULT: In this experiment we have learned to set up a digital links at 650 nm & 850 nm using the
available transmitters & receivers.
 SAMPLE VIVA QUESTIONS

Q1.Explain in simple terms what the difference in fiber optics and traditional copper cable.

Q2.Do signals really travel faster in fiber optic?

Q3.What are some of the uses of fiber optic cabling in the business world?

Q4.Will “intelligent building” uses fiber optics or copper wiring to carry voice/data/video
throughout the structure?

Q5.What are the advantage of fiber optics?

Q6.What is single mode fiber?

Q7.What is Multi-Mode fiber?

Q8.How is an AV signal transmitted down a fiber?

Q9.What is the advantage of transmitting video,audio and control signal on a single fiber?

Q10.How do you identify the type of dark fiber installed if it poorly documented?

Q11.What is a fusion splice?

Q12.What is Mechanical splice?

Q13.How do you repair broken fiber?

Q14.What cable marking are used for riser-rated optical cable?

Q15.What do you understand by Digital Link?

 EXPERIMENT 10
OBJECTIVE: To study the characteristic of laser diode and light emitting diode.

THEORY:
LASER DIODE:

The laser diode is a laser where the active medium is a semiconductor similar to that found in a light-
emitting diode. The most common type of laser diode is formed from a p-n junction and powered by
injected electric current. The former devices are sometimes referred to as injection laser diodes to
distinguish them from optically pumped laser diodes.

MOUNTING POST SETUP

Mounting posts are used only for 650nm LD unit as its beam is collimated using a collimating
lens and users air as the medium. The mounting post helps to align the 650nm laser beam with a receiver
or a power meter in a straight line.

The mounting post consists of a cylindrical post for mounting either the LD unit or the power meter for
measuring the optical power output of the laser diode. There is a screw provided at the base of the
mounting post. By loosening this screw, the height of the mounting base. The height of the mounting
base can be adjusted coarsely by rotating the mounting base itself. After adjusting the height of the
mounting base to the required height the upper lock nut is tightened to lock the position of the mounting
base. By using the lower lock nut fine adjustment of the height of the mounting base can be done. After
this the two lock nuts should be tightened and the screw at the base of the mounting post also should be
tightened. The two screws provided at the bottom of the mounting base are used to fix the LD unit and the
power meter. The LD and the power meter are having two screw holes at the bottom.

LD MODULE SETUP

The LD module consists of4units-viz.LDdriver, LD modulator, LD unit(650nm or

1300nm or 1550nm) and a receiver (FORX-200 for 650nm region or FORX-500 for 1300nm and 1550nm
region). The LD driver unit is having the driving circuitry required for driving the current through LD for
LD characteristics study. The LD unit is having the LD with a feedback PD. The LD modulator unit and
the receiver combination is used to setup a 650nm LoS LINK OR 1300NM FIBER OPTIC LINK OR
1550NM FIBER OPTIC LINK. The modulator unit does the signal conditioning and optical modulation
while the receiver receives the optical signal and converts back to the electrical signal.

650nm LD unit
 The visible LD is placed in this unit with the collimating lens. The signal interface to
this unit is through a D9 connector provided at one side of this unit. Through this interface the driver
drives the current and controls the LD. Mount the LD unit onto the mounting post as explained in the
mounting post setup. The LD unit is provided with the collimating lens at the front side. This collimating
lens can be adjusted to focus the LD to a narrow beam of light.

1300nm LD unit
The 1300nm LD with ST interface is placed in this unit. The signal interface to this unit is
through a D9 connector provided at one side of this unit. Through this interface the driver drives the
current and controls the LD. Use the ST-ST patch cord supplied with this unit for power measurements
and for the link establishment.

1550nm LD unit
The 1550nm LD with SC interface is placed in this unit. The signal interface to this unit is
through a D9 connector provided at one side of this unit. Through this interface the driver drives the
current and controls the LD. Use the SC-ST patch cord supplied with this unit for power measurements
and for the link establishment.

LD driver
The LD driver can be used with either 650nm LD unit or 1300nm or 1550nm LD unit. It
has the basic circuit diagram as shown in fig.2.1 it has a multi turn potentiometer for varying the current
through LD, and a resistor for calculating the current. It has a 10x2 header at the top. A flat cable with
10x2header at one end and 9 pin D-type connector at the other end is used to connect the LD unit to this
driver.

LD modulator
The LD modulator can be used with either 650nm or 1300nm or 1550nm LD unit .it
has a 10x2 header at the top. A flat cable with 10x2header at one end and 9 pin D-type connector at the
other end is used to connect the LD unit to this modulator. It accepts TTL signals through BNC
connectors and modulates the LD current.

Setting up the LD module for characteristics study

 Caution laser radiation. Avoid direct eye or skin exposure to laser beam while setting up the
system or conducting experiments. Always view only the reflected rays in case of visible LDs
while setting up the system or while conducting experiments.
 Caution Always keep the multi-turn pot in its minimum position while power on and power off
the unit to avoid damage to the LD.

Connect the power supply properly to the LD driver unit using the DIN-DIN cable provided with the
power supply. Turn the multi-turn pot to its minimum position. This ensures that high current is not
rushed in to the LD and damaging it. Connect the LD driver with the LD unit using the flat cable provided
with the LD driver.

FOR 650nm LD unit

 Mount the LD unit onto the mounting post provided as explained in mounting post setup. Mount
the power meter also (with its ST adaptor) onto another post and keep them close to each other
and in line with each other.
 Adjust the height of the power meter and the LD unit by adjusting the mounting base of the posts
as explained in mounting post set up in such a way that both of them are of same height and in
line with each other.
 Keep the multi-turn pot in its minimum position. Turn on the LD driver. Adjust the multi-turn pot
in its maximum position slowly so that a bright spot coming out of the laser diode can be seen
falling somewhere on the meter.
 Adjust the collimating lens of the LD unit such that the bright spot turns to a very small focused
bright spot. Adjust the mounting post of either power meter or the LD unit such that this spot
passes through the bare fiber adaptor of the meter and the meter reads a value of approximately -
20dBm. If the power is not reached the beam may not be focused for the following two reasons:
a. Both LD and power meter are not in a straight line- line of sight
b. The height are not adjusted so that the beam exactly passes through the ST adaptor and falls
onto the PD in the meter

For 1300nm LD unit

 Connect the ST-ST patch cord between the LD unit and the power meter.

V-I & P-I CHARACTERISTICS

3.1.1 Equipments needed

1. A digital multi-meter.

2. Benchmark 650nm LD unit (or) 1300nm (or) 1550nmLDunit.

3. Benchmark LD driver module with its accessories.

4. Benchmark fiber optic power meter with ST adaptor.

5. Mounting posts for 650nm LD unit (or) ST-ST patch cord for 1300nm

LD unit or SC-ST patch cord for 1550nm LD unit

PROCEDURE:
Caution Laser radiation avoid direct eye or skin exposure to laser beam while setting up the system or
conducting experiments. Always view only the reflected rays in case of visible LDs while setting up the
system or while conducting experiments.

1. Set up the LD driver module as said in the system set up procedure in the previous chapter and
turn it off as recommended.
2. Do not disturb the mechanical set up if the LD unit is 650nm until the experiments is over. Keep
the pot at the minimum position. Turn on the power to the module.
3. Measure the voltage V1across the resistor R1 (where R1 is 68ohms) and calculate the current ILD
through the LD which is given as
ILD =V1/R1

4. Measure the voltage VLD across the LD.

5. Now without changing any voltage or the multi-turn pot position, measure the optical power
output P of the LD.

LED module
Introduction:
LED is the vital part in a fiber optic communication link. It forms the E-O section
of the transmitter in any link. In LED module the injection current through an 850nm/ 1300nm
fiber optics LED (DEPENDING ON THE MODEL) is varied and thereby its characteristics are
studied. The injection current through the LED is controlled using a multi-turn potentiometer,
which enables the user to have a control over it. The LED module “850nm PF” is shown in fig 2.1
and the LED module “1300nm GF-MM” is shown in module needs an external DC power supply
to operate. The LED module is provided with appropriate monitoring posts for taking the
necessary measurements.

2.1 LED module set up

The LED module has the basic circuit diag. as shown in the above fig. it mainly consists
of a fiber optic LED for which the characteristics will be studied, a multi-turn potentiometer for
varying the current through LED, a high precision resistor for calculating the current. The
following chapter describes steps to be followed by the user to study DC characteristics of LED,
using this module.

V-I characteristics & P-I characteristics

3.1 Equipments needed
 1. OFT power supply
2. A digital multi-meter
3. LED module- 850nm PF or 1300nm GF-MM
4. Benchmark fiber optic power meter
5. Bare fiber adaptor- plastic (for 850nm PF)
6. ST adaptor for meter (for 1300nm GF-MM)
7. 1.25m plastic fiber (for 850nm PF)
8. 1m ST-ST patch cord (for 1300nm GF-MM)

3.2 Procedure

Connect the OFT power supply properly to the module using the DIN-DIN cable
provided with the power supply . turn the multi-turn pot to its minimum position and switch on
the module

1. Measure the voltage V1 across the resistor R1(180ohms for 850nm PF or 150ohms for
1300nm GF-mm) and calculate the current through the LED If which is given as

If =V1/180 for 850nm PF

If =V1/150 for 1300nm GF-MM

2. Now measure the voltage VLED across the LED and note down.
3. FOR 850nm PF MODULE

Remove the dummy adaptor cap from the power meter PD exposing the large
area photo-detector. Mount the bare fiber adaptor – plastic over the PD. Carefully hold the LED
source very close to the photo-detector window perpendicular to it couple all the optical power
from the LED the power meter. Now without changing any voltage or the potentiometer, measure
the optical power output P of the LED.

Calculate the power in mW and note it down which is given as

Po=10P/10

4. Turn the potentiometer clockwise direction slightly towards the maximum till you get a
convenient readingV1 and repeat the steps 1

5. Repeat step 4 and note down several readings till the potentiometer reaches its maximum
position and plot the graph for VLED VS If and If VSPO.

THE graphs should be similar to the one shown in fig. 3.1 and fig3.2 respectively for 850nm
PF module.
 6. Calculate the E-O conversion efficiency „n‟ of the LED from the plotted graph „ If‟ VSPO
which is given as
n=Po/If

7. FOR 850nmPF MODULE

Unscrew the self locking cap in the LED without removing it completely and insert the 1.25m
plastic fiber into the cap. Now tighten the cap. Remove the ST adaptor from the power meter
PD and mount the bare fiber adaptor –plastic on to the PD. Insert the other end of the plastic
fiber to this adaptor. Repeat the optical power measurements as said in this previous steps
but now with a plastic fiber connected between the LED module and power meter.
For 1300nm GF-MM Module

Connect one end of the ST-ST patch cord to the LED and the other end to the ST adaptor for
power meter. Repeat the optical power measurement as said in the previous steps but now
with a ST-ST patch cord connected between the LED modules and the power meter

Plot the optical power values and what do you see in the plots and what happens to the E-O conversion
efficient
 SAMPLE VIVA QUESTIONS

Q1.What is light emitting diode?

Q2.What is laser diode?
Q3.Can laser diode or LED cause harm?
Q4.How do you repair broken fiber?
Q5.How do diode work?
Q6.What are application of LED?
Q7.What are application of LaserDiode

Q8.What are advantage of LED?

Q9.What are advantage of Laser Diode?

Q10.Waht is difference between LED and LD‟s?
Q11.What are characteristic of Laser Radiation?
Q12.What is mean by Interference of light?
Q13.Is there any energy loss in interference phenomena ?
Q14.What are interference fringes?
Q15.What is Zener breakdown?