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Step-6 Timing Diagram: Step-7 Truth Table Clock Number Q Q Q Q Counting

The document describes the operation of an asynchronous 3-bit up/down counter. It includes a truth table showing the counter's output states from 0 to 15 as the clock cycles. It also explains the logic operations for each counter state type as the clock pulses progress from 001 to 111. Finally, it provides a brief overview of up/down ripple counters and includes a block diagram of a 3-bit binary up/down counter.

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Shravan Kumar Namdeo
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122 views4 pages

Step-6 Timing Diagram: Step-7 Truth Table Clock Number Q Q Q Q Counting

The document describes the operation of an asynchronous 3-bit up/down counter. It includes a truth table showing the counter's output states from 0 to 15 as the clock cycles. It also explains the logic operations for each counter state type as the clock pulses progress from 001 to 111. Finally, it provides a brief overview of up/down ripple counters and includes a block diagram of a 3-bit binary up/down counter.

Uploaded by

Shravan Kumar Namdeo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Step-6 Timing Diagram

Step-7 Truth Table


Clock Number Q3 Q2 Q1 Q0 Counting
0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2

3 0 0 1 1 3
4 0 1 0 0 4
5 0 1 0 1 5
6 0 1 1 0 6
7 0 1 1 1 7
8 1 0 0 0 8
9 1 0 0 1 9
10 1 0 1 0 10
11 1 0 1 1 11
12 1 1 0 0 12
13 1 1 0 1 13
14 1 1 1 0 14
15 1 1 1 1 15

Step-8 State Diagram


Step-9 Logic Operation
Initially all flip flop set at zero postion and the logic operatioinn of asynchronous counter are
divede into following type
Type-1 When all flip flop initially zero and first clock pulse applied to first Flip Flop So first
flip state change 0 to 1 and all other flip flop state remain same so output after first clock pulse
is
Q2 Q1 Q0 = 001
Type-2 After the first clock pulse output is 001 and when second clock pulse applied then first
flip state change 1 to 0 and second flips state 0 to 1 and third flip flop state remain same so
output after second clock pulse is
Q2 Q1 Q0 = 010
Type-3 After the first clock pulse output is 010 and when second clock pulse applied then first
flip state change 0 to 1 and second flips state 0 to 1 and third flip flop state remain same so
output after second clock pulse is
Q2 Q1 Q0 = 011
Type-4 After the first clock pulse output is 011 and when second clock pulse applied then first
flip state change 1 to 0 and second flip state 1 to 0 and third flip flop state Change 0 to 1 so
output after second clock pulse is
Q2 Q1 Q0 = 100
Type-5 After the first clock pulse output is 100 and when second clock pulse applied then first
flip state change 0 to 1 and second flips state not change and third flip flop state remain same so
output after second clock pulse is
Q2 Q1 Q0 = 101
Type-6 After the first clock pulse output is 101 and when second clock pulse applied then first
flip state change 1 to 0 and second flips state 0 to 1 and third flip flop state remain same so
output after second clock pulse is
Q2 Q1 Q0 = 110
Type-7 After the first clock pulse output is 110 and when second clock pulse applied then first
flip state change 0 to 1 and second flips state remain same and third flip flop state remain same
so output after second clock pulse is
Q2 Q1 Q0 = 111
UP/DOWN Ripple Counters

It is sequential Circuit which count bit in up direction and then down direction .There are two
type of operation in UP Down Counter
 UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock
of the next stage if up counting is to be achieved. For this mode, the mode select input
M is at logic 0 (M=0).
 DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is
connected to the next FF. This will operate the counter in the counting mode.
3-bit binary up/down ripple counter.
 3-bit − hence three FFs are required.
 UP/DOWN − So a mode control input is essential.
 For a ripple up counter, the Q output of preceding FF is connected to the clock input of
the next one.
 For a ripple up counter, the Q output of preceding FF is connected to the clock input of
the next one.
 For a ripple down counter, the Q bar output of preceding FF is connected to the clock
input of the next one.
 Let the selection of Q and Q bar output of the preceding FF be controlled by the mode
control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1,
DOWN counting. So connect Q bar to CLK.
Block Diagram

Truth Table

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