xx

DDR Analysis
ZZZ

Online Help

*P077023108*
077-0231-08
 DDR Analysis
ZZZ

Online Help

www.tektronix.com
077-0231-08
Copyright © Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its
subsidiaries or suppliers, and are protected by national copyright laws and international treaty provisions.
Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this
publication supersedes that in all previously published material. Specifications and price change privileges
reserved.
TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.
DDR Analysis Online Help Part Number, 076-0178-08, November 16, 2013.

Contacting Tektronix
Tektronix, Inc.
14150 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA

For product information, sales, service, and technical support:

In North America, call 1-800-833-9200.
Worldwide, visit www.tektronix.com to find contacts in your area.
 Table of Contents

Table of Contents
General safety summary .......................................................................................... xi

Introduction to the Application

Welcome ............................................................................................................. 1
Related Documentation ............................................................................................ 3
Conventions ......................................................................................................... 4
Technical Support .................................................................................................. 4
Customer Feedback ................................................................................................ 5

Getting Started
Product Description ................................................................................................ 7
DDRA Prerequisites................................................................................................ 7
Requirements and Restrictions ................................................................................... 7
Supported Probes ................................................................................................... 8
Installing the Application ......................................................................................... 9
About DDRA ...................................................................................................... 10

Operating Basics
About Basic Operations
Starting the Application ...................................................................................... 11
Menu Controls ................................................................................................ 11
Virtual Keypad ................................................................................................ 12
Tips on the DDRA User Interface .......................................................................... 12
Basic Oscilloscope Functions
Application Directories ...................................................................................... 13
File Name Extensions ........................................................................................ 13
Returning to the Application ................................................................................ 13
Control Panel .................................................................................................. 14
Saving and Recalling Setups
Saving a Setup ................................................................................................ 15
Recalling a Saved Setup ..................................................................................... 15
Recalling the Default Setup.................................................................................. 16
Limits ............................................................................................................... 16
Search and Mark ................................................................................................... 17
Dynamic Limits.................................................................................................... 18
Setting up DDR for Analysis
DDR Standards and their Measurements................................................................... 19
Derating ........................................................................................................ 27
About DDR Analysis......................................................................................... 30

DDR Analysis i
Table of Contents

Step1: Generation, Rate and Levels ........................................................................ 31

Step2: Interposer Filter....................................................................................... 34
Step3: Measurements and Sources ......................................................................... 35
Step4: Burst Detection Method ............................................................................. 40
Step5: Burst Detection Settings ............................................................................. 40
DQ/DQS Phase Alignment .................................................................................. 41
Chip Select, Latency + DQ/DQS Phase Alignment....................................................... 43
Logic State + Burst Latency ................................................................................. 44
Visual Search .................................................................................................. 47
Step6: Thresholds and Scaling .............................................................................. 51
Measurement Levels.......................................................................................... 55
Hints............................................................................................................ 56
Results as Statistics ........................................................................................... 57
Plots ............................................................................................................ 58
Reports ......................................................................................................... 58
Switching between the DDRA and DPOJET Applications .............................................. 59
Salient Features of MSO-DDRA Integration .............................................................. 60

Tutorial
Introduction to the Tutorial ....................................................................................... 61
Setting Up the Oscilloscope ...................................................................................... 61
Starting the Application........................................................................................... 61
Waveform Files .................................................................................................... 61
Recalling a Waveform File ....................................................................................... 62
Taking a Measurement ............................................................................................ 62

Parameters
About Parameters.................................................................................................. 67
Step1: Generation, Rate and Levels Parameters ............................................................... 68
Step2: Interposer Filter Parameters.............................................................................. 69
Step3: Measurement and Sources Parameters.................................................................. 70
Step4: Burst Detection Method Parameters .................................................................... 71
Step5: Burst Detection Settings Parameters .................................................................... 71
Step6: Thresholds and Scaling Parameters ..................................................................... 73

References
LPDDR Measurement Sources................................................................................... 75
LPDDR2 Measurement Sources ................................................................................. 77
LPDDR3 Measurement Sources ................................................................................. 82
DDR Measurement Sources ...................................................................................... 86
DDR2 Measurement Sources .................................................................................... 89
DDR3 Measurement Sources .................................................................................... 93

ii DDR Analysis
 Table of Contents

DDR3L Measurement Sources .................................................................................. 97

DDR4 Measurement Sources .................................................................................. 100
GDDR5 Measurement Sources ................................................................................ 104
Measurement Range Limits .................................................................................... 107
Dynamic Limits for LPDDR Measurements ................................................................. 108
Dynamic Limits for LPDDR2 Measurements ................................................................ 109
Dynamic Limits for LPDDR3 Measurments ................................................................. 110
Dynamic Limits for DDR Measurements ..................................................................... 111
Dynamic Limits for DDR2 Measurements ................................................................... 112
Dynamic Limits for DDR3 Measurements ................................................................... 113
Dynamic Limits for DDR3L Measurements.................................................................. 114
Dynamic Limits for DDR4 Measurements ................................................................... 115
Vih/Vil Reference Levels ....................................................................................... 115
Using Digital Channels ......................................................................................... 118
Error Codes and Warnings...................................................................................... 125

Algorithms
About Algorithms ............................................................................................... 131
Write Measurements
tDQSS........................................................................................................ 131
Data Eye Width ............................................................................................. 132
Data Eye Height ............................................................................................ 133
Differential DQS Measurements
Input Slew-Diff-Rise(DQS)........................................................................... 134
Input Slew-Diff-Fall(DQS) ........................................................................... 134
tDH-Diff(base) ......................................................................................... 135
tDH-Diff(derated)...................................................................................... 135
tDH-Diff(Vref-based).................................................................................. 135
tDS-Diff(base).......................................................................................... 135
tDS-Diff(derated) ...................................................................................... 137
tDS-Diff(Vref-based) .................................................................................. 137
tDQSH .................................................................................................. 138
tDQSL................................................................................................... 138
tDSS-Diff ............................................................................................... 138
tDSH-Diff............................................................................................... 139
tDQSS-Diff ............................................................................................. 139
Single Ended DQS
Slew Rate-Hold-SE-Fall(DQS)....................................................................... 139
Slew Rate-Hold-SE-Rise(DQS) ...................................................................... 139
Slew Rate-Setup-SE-Fall(DQS) ...................................................................... 139
Slew Rate-Setup-SE-Rise(DQS) ..................................................................... 140
tDS-SE(base) ........................................................................................... 140

DDR Analysis iii

Table of Contents

tDIPW-SE............................................................................................... 140
tDSS-SE................................................................................................. 140
tDSH-SE ................................................................................................ 140
tDQSS-SE............................................................................................... 141
tDH-SE(base)........................................................................................... 141
tDVAC(CK) ................................................................................................. 141
tWPRE ....................................................................................................... 142
tWPST ....................................................................................................... 143
tWRPDE ..................................................................................................... 143
tWRSRE ..................................................................................................... 143
Read Measurements
Differential DQS
tDQSCK-Diff........................................................................................... 144
tDQSQ-Diff............................................................................................. 144
tAC-Diff................................................................................................. 145
tQH ...................................................................................................... 145
SRQdiff-Rise(DQS) ................................................................................... 146
SRQdiff-Fall(DQS) .................................................................................... 146
Single Ended DQS
tDQSQ-SE .............................................................................................. 147
tDQSCK-SE ............................................................................................ 147
DDR2-tDQSCK ........................................................................................ 148
Slew Rate DQ
SRQse-Fall(DQ) ....................................................................................... 148
SRQse-Rise(DQ)....................................................................................... 149
tRDPDE...................................................................................................... 149
tRDSRE...................................................................................................... 149
tRPRE ........................................................................................................ 150
tRPST ........................................................................................................ 150
DQ Measurements
Slew Rate-Hold-Fall(DQ) ................................................................................. 150
Slew Rate-Hold-Rise(DQ) ................................................................................. 150
Slew Rate-Setup-Fall(DQ)................................................................................. 150
Slew Rate-Setup-Rise(DQ) ................................................................................ 151
Clock(Diff) Measurements
SSC Downspread(CK) ..................................................................................... 151
SSC Mod Freq(CK) ........................................................................................ 151
SSC Profile(CK) ............................................................................................ 151
tCH ........................................................................................................... 151
tCK ........................................................................................................... 152
tCL ........................................................................................................... 152
tCH(abs) ..................................................................................................... 152

iv DDR Analysis
 Table of Contents

tCH(avg) ..................................................................................................... 153

tCK(abs) ..................................................................................................... 153
tCK(avg) ..................................................................................................... 153
tCL(abs)...................................................................................................... 154
tCL(avg) ..................................................................................................... 154
tHP ........................................................................................................... 154
tERR.......................................................................................................... 155
tJIT(cc)....................................................................................................... 156
tJIT(duty) .................................................................................................... 156
tJIT(per)...................................................................................................... 157
VID(ac) ...................................................................................................... 157
Input Slew-Diff-Rise(CK) ................................................................................. 157
Input Slew-Diff-Fall(CK) .................................................................................. 158
Clock (Single Ended)
AC-Overshoot(CK#) ....................................................................................... 158
AC-Overshoot(CK)......................................................................................... 158
AC-OvershootArea(CK#).................................................................................. 159
AC-OvershootArea(CK) ................................................................................... 160
AC-Undershoot(CK#) ...................................................................................... 160
AC-Undershoot(CK) ....................................................................................... 161
AC-UndershootArea(CK#) ................................................................................ 161
AC-UndershootArea(CK).................................................................................. 162
CKslew-Fall(CK) ........................................................................................... 162
CKslew-Fall(CK#).......................................................................................... 162
CKslew-Rise(CK) .......................................................................................... 163
CKslew-Rise(CK#) ......................................................................................... 163
VIN(CK) ..................................................................................................... 163
VIN(CK#) ................................................................................................... 163
Vix(ac)CK ................................................................................................... 164
Vox(ac)CK................................................................................................... 164
VSWING(MAX)CK# ...................................................................................... 164
VSWING(MAX)CK ....................................................................................... 165
VSEH(AC)CK .............................................................................................. 165
VSEH(AC)CK# ............................................................................................. 166
VSEH(CK#) ................................................................................................. 166
VSEH(CK) .................................................................................................. 166
VSEL(AC)CK# ............................................................................................. 166
VSEL(AC)CK............................................................................................... 167
VSEL(CK#) ................................................................................................. 167
VSEL(CK)................................................................................................... 167
DQS(Single Ended) Measurements
Vix(ac)DQS ................................................................................................. 168

DDR Analysis v
Table of Contents

Vox(ac)DQS ................................................................................................. 168

AC-Overshoot(DQS) ....................................................................................... 168
AC-Overshoot(DQS#) ..................................................................................... 169
AC-OvershootArea(DQS#)................................................................................ 169
AC-OvershootArea(DQS) ................................................................................. 170
AC-Undershoot(DQS) ..................................................................................... 170
AC-Undershoot(DQS#) .................................................................................... 171
AC-UndershootArea(DQS#) .............................................................................. 171
AC-UndershootArea(DQS)................................................................................ 172
WCK (Diff)
SSC Downspread(WCK) .................................................................................. 172
SSC Mod Freq(WCK)...................................................................................... 172
SSC Profile(WCK) ......................................................................................... 173
tDVAC(WCK) .............................................................................................. 173
tWCK ........................................................................................................ 173
tWCK-DJ .................................................................................................... 173
tWCKH ...................................................................................................... 173
tWCKHP..................................................................................................... 174
tWCKL....................................................................................................... 174
tWCK-Rise-Slew ........................................................................................... 174
tWCK-Fall-Slew ............................................................................................ 174
tWCK-RJ .................................................................................................... 174
tWCK-TJ .................................................................................................... 175
VWCK-Swing............................................................................................... 175
WCK (Single Ended)
VIN(WCK) .................................................................................................. 175
VIN(WCK#)................................................................................................. 175
Vix(ac)WCK ................................................................................................ 176
VOL(WCK) ................................................................................................. 176
VOH(WCK) ................................................................................................. 176
VOL(WCK#)................................................................................................ 176
VOH(WCK#) ............................................................................................... 177
WCKslew-Fall(WCK) ..................................................................................... 177
WCKslew-Fall(WCK#) .................................................................................... 177
WCKslew-Rise(WCK) ..................................................................................... 177
WCKslew-Rise(WCK#) ................................................................................... 177
Address/Command Measurements
AC-Overshoot............................................................................................... 178
AC-OvershootArea ......................................................................................... 178
AC-Undershoot ............................................................................................. 179
AC-UndershootArea........................................................................................ 179
Slew Rate-Hold-Fall(Addr/Cmd) ......................................................................... 180

vi DDR Analysis
 Table of Contents

Slew Rate-Hold-Rise(Addr/Cmd)......................................................................... 180

Slew Rate-Setup-Fall(Addr/Cmd) ........................................................................ 180
Slew Rate-Setup-Rise(Addr/Cmd)........................................................................ 180
tAH ........................................................................................................... 181
tAPW......................................................................................................... 181
tAS ........................................................................................................... 181
tCMDH ...................................................................................................... 181
tCMDPW .................................................................................................... 181
tCMDS ....................................................................................................... 182
tIS(base) ..................................................................................................... 182
tIH(base) ..................................................................................................... 182
tIS(derated) .................................................................................................. 182
tIH(derated).................................................................................................. 183
tIPW-High ................................................................................................... 183
tIPW-Low.................................................................................................... 183
Refresh
tCKSRE...................................................................................................... 183
tCKSRX ..................................................................................................... 183
tRFC.......................................................................................................... 184
tREFTR(Read) .............................................................................................. 184
tREFTR(Write).............................................................................................. 184
tXSNRW..................................................................................................... 184
Power Down
tPD ........................................................................................................... 184
Active
tRAS.......................................................................................................... 185
tRC ........................................................................................................... 185
tRCDRD ..................................................................................................... 186
tRCDWR .................................................................................................... 186
Precharge
tPPD .......................................................................................................... 187
tRP(ACT) .................................................................................................... 187
tRP(MRS) ................................................................................................... 188
tRP(REF) .................................................................................................... 188
tRP(SRE) .................................................................................................... 188
tRTPL ........................................................................................................ 188

GPIB Commands
About the GPIB Program ....................................................................................... 189
GPIB Reference Materials...................................................................................... 189
Argument Types ................................................................................................. 190
DDRA:ADDMeas ............................................................................................... 190

DDR Analysis vii

Table of Contents

DDRA:ADDALLDiffdqs....................................................................................... 192
DDRA:ADDALLSEdqs ........................................................................................ 192
DDRA:ADDALLSLewdq ...................................................................................... 193
DDRA:ADDALLTerr ........................................................................................... 193
DDRA:CLEARALLMeas ...................................................................................... 194
DDRA:LASTError? ............................................................................................ 194
DDRA:GENeration.............................................................................................. 195
DDRA:DATARate............................................................................................... 196
DDRA:CUSTOMRate .......................................................................................... 197
DDRA:MEASType.............................................................................................. 198
DDRA:VDDMode............................................................................................... 198
DDRA:VDD ..................................................................................................... 199
DDRA:VREFMode ............................................................................................. 199
DDRA:VREF .................................................................................................... 200
DDRA:VIHACMin? ............................................................................................ 200
DDRA:VIHDCMin? ............................................................................................ 201
DDRA:VREFDC? ............................................................................................... 201
DDRA:VILDCMax? ............................................................................................ 202
DDRA:VILACMax? ............................................................................................ 202
DDRA:SOURCE? ............................................................................................... 203
DDRA:SOURCE:STROBE .................................................................................... 203
DDRA:SOURCE:STRObebar ................................................................................. 204
DDRA:SOURCE:DATa......................................................................................... 205
DDRA:SOURCE:CLOCK ..................................................................................... 206
DDRA:SOURCE:CLOCKBar ................................................................................. 207
DDRA:SOURCE:WCK......................................................................................... 208
DDRA:SOURCE:WCKBar .................................................................................... 209
DDRA:BURSTDETectmethod................................................................................. 210
DDRA:BUS ...................................................................................................... 211
DDRA:SYMBOLFile ........................................................................................... 212
DDRA:LOGICTrigger .......................................................................................... 212
DDRA:BURSTTOlerance ...................................................................................... 213
DDRA:BURSTLAtency ........................................................................................ 213
DDRA:BURSTLEngth ......................................................................................... 214
DDRA:ALTernatethresholds ................................................................................... 215
DDRA:VERTicalscaling ........................................................................................ 216
DDRA:HORIzontalscaling ..................................................................................... 217
DDRA:CSSOUrce............................................................................................... 217
DDRA:CASMIN ................................................................................................ 218
DDRA:CASMAX ............................................................................................... 218
DDRA:CSLEvel ................................................................................................. 219
DDRA:CSMOde................................................................................................. 219

viii DDR Analysis

 Table of Contents

DDRA:CSACTive ............................................................................................... 220

DDRA:VERsion?................................................................................................ 220
DDRA:BURSTLevelmode ..................................................................................... 221
DDRA:STROBEHIGH ......................................................................................... 221
DDRA:STROBELOW .......................................................................................... 222
DDRA:STROBEMID........................................................................................... 222
DDRA:DATALOW ............................................................................................. 223
DDRA:DATAHIGH ............................................................................................. 223
DDRA:DATAMID .............................................................................................. 224
DDRA:HYSTEREsis ........................................................................................... 224
DDRA:MARGIN ................................................................................................ 225
DDRA:DQDQSLEVELSTAtus? .............................................................................. 225
DDRA:VCENTDQ.............................................................................................. 226
DDRA:FLTtype.................................................................................................. 226
DDRA:PTYPDQS............................................................................................... 227
DDRA:PTYPCLK............................................................................................... 227
DDRA:PTYPWCK.............................................................................................. 228
DDRA:SEFLTFile ............................................................................................... 228
DDRA:DIFFFLTFile ............................................................................................ 229
DDRA:TCKAVGMIN .......................................................................................... 229
DDRA:TCKAVG ................................................................................................ 230

Index

DDR Analysis ix
Table of Contents

x DDR Analysis
 General safety summary

General safety summary

Review the following safety precautions to avoid injury and prevent damage to this product or any
products connected to it.
To avoid potential hazards, use this product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of a larger system. Read the safety sections
of the other component manuals for warnings and cautions related to operating the system.

To avoid fire or personal injury

Use proper power cord. Use only the power cord specified for this product and certified for the country
of use.
Connect and disconnect properly. Do not connect or disconnect probes or test leads while they are
connected to a voltage source.
Connect and disconnect properly. Connect the probe output to the measurement instrument before
connecting the probe to the circuit under test. Connect the probe reference lead to the circuit under test
before connecting the probe input. Disconnect the probe input and the probe reference lead from the circuit
under test before disconnecting the probe from the measurement instrument.
Observe all terminal ratings. To avoid fire or shock hazard, observe all ratings and markings on the product.
Consult the product manual for further ratings information before making connections to the product.
Do not operate without covers. Do not operate this product with covers or panels removed.
Do not operate with suspected failures. If you suspect that there is damage to this product, have it inspected
by qualified service personnel.
Avoid exposed circuitry. Do not touch exposed connections and components when power is present.

DDR Analysis xi
General safety summary

Terms in this manual

These terms may appear in this manual:

WARNING. Warning statements identify conditions or practices that could result in injury or loss of life.

CAUTION. Caution statements identify conditions or practices that could result in damage to this product
or other property.

xii DDR Analysis

Introduction to the Application Welcome

Welcome
DDR (Dual Data Rate) is a dominant and fast-growing memory technology. It offers the high data transfer
rates needed for virtually all computing applications, from consumer products to the most powerful
servers. The high speeds of these signals require high performance measurement tools.
The DDRA application includes compliance measurements as part of our DDR Analysis solution. The
DDR Analysis solution enables you to achieve new levels of productivity, efficiency, and measurement
reliability. It requires the Jitter and Eye Diagram Analysis tool (Opt. DJA) and the Advanced Search and
Mark capability (Opt. ASM).
Some of the DDRA features are:
Provides debug, analysis, and compliance in one solution for multiple DDR standards such as DDR
(see page 1), DDR2 (see page 2), DDR3 (see page 2), DDR3L (see page 2), DDR4 (see page 2).
LPDDR (see page 2), LPDDR2 (see page 2), LPDDR3 (see page 2), GDDR3 (see page 2), and
GDDR5 (see page 3).
Enables analysis of compliance measurements either through the DDRA or DPOJET application for
all bursts in an acquisition
Differentiates data reads from writes, or analyzes signal integrity on the clock or on a data (DQ) line
during Read or Write cycles, or measures Data to Strobe setup and hold during Write cycles
Includes limit files to test measurement pass/fail status per standard, speed grades and speed bins.
Supports non-standard speed grades
Provides both single-ended and differential measurements on Data, Strobe, Clock, Address and
Command signals
Includes comprehensive measurement statistics
Includes sophisticated graphical analysis tools such as Histograms, Time Trends, Spectrums, Bathtub
Plots, and Real-Time Eye® diagrams with superimposition of the strobe eye with the data eye
Produces consolidated reports automatically with pass/fail information, statistical measurement results,
setup information, limits information, waveform path location, plots and user comments, if any.
Automatically applies signal slew rate derating of measurement limits for Address/Command and
data signals
Dynamically normalizes limits for clock measurements such as tERR based on the measured tCK(avg)
Logic state configuration using the DDRA user interface.

DDR
DDR is the DRAM (Dynamic Random Access Memory) technology responsible for increasing data
transfer rates to meet high-speed requirements and data capacity of computer systems.

DDR Analysis 1
Introduction to the Application Welcome

DDR2
DDR2 is the Double Data Rate 2 SDRAM and is widely available in products with data rates up to
1066MT/s.

DDR3
DDR3 DRAM memory is widely available in products and extends data rates to 1600 MT/s and
faster rates to come.

DDR3L
DDR3L (low voltage) DRAM memory is widely available in products and extends data rates to
1600 MT/s and faster rates to come.

DDR4
DDR4 DRAM memory is widely available in products and extends data rates to 3200 MT/s and
faster rates to come.

Low Power DDR

LPDDR (Low Power DDR) is an emerging technology for mobile phones and portable computing
devices, driven by the need for faster operation with long battery life.

Low Power DDR2

LPDDR2 (Low Power DDR2) is an emerging technology for mobile phones and portable computing
devices as it supports advanced power management. Includes a reduced interface voltage of 1.2 V
from the 1.8 V specification as compared to LPDDR memory technology. This results in a power
consumption reduced by over 50%.

Low Power DDR3

LPDDR3 (Low Power DDR3) is an emerging technology for mobile phones and portable computing
devices as it supports advanced power management. Includes a reduced interface voltage of 1.2 V
from the 1.8 V specification as compared to LPDDR memory technology. This results in a power
consumption reduced by over 50%.

Graphic DDR3
GDDR3 (Graphic DDR) offers faster access and is used in graphics-intensive applications such
as video cards and gaming systems.

2 DDR Analysis
Introduction to the Application Related Documentation

GDDR5
GDDR5 (Graphic DDR) is a type of high performance dynamic random-access graphics card memory
designed for applications requiring high bandwidth.

Related Documentation
Tektronix manuals are available at: www.tektronix.com/manuals and www.tektronix.com/software. Use
the following table to determine the document that you need:

Table 1: List of reference documents

For information on Refer to
Operating the Oscilloscope Oscilloscope user manual.
Oscilloscope user online help.
Software warranty Optional Applications Software on Windows-Based
Oscilloscopes Installation Manual, which is provided on
List of available applications the Optional Applications Software on Windows-Based
Compatible oscilloscopes Oscilloscopes DVD, in the Documents directory.

Relevant software and firmware version numbers

Applying a new option key label
Installing an application
Enabling an application
Downloading updates from the Tektronix Web site
xxx

DDR Analysis 3
Introduction to the Application Conventions

Conventions
Online Help uses the following conventions:
When steps require a sequence of selections using the application interface, the “>” delimiter marks
each transition between a menu and an option. For example, Analyze > DDR Analysis.
The terms “DDR application” and “application” refer to DDRA.
The term “DPOJET application” or “DPOJET” refers to Jitter and Eye Diagram Analysis Tool.
The term “oscilloscope” refers to any product on which this application runs.
The term “DUT” is an abbreviation for Device Under Test.
The term “select” is a generic term that applies to the methods of choosing an option: with a mouse or
with the touch screen.
User interface screen graphics are taken from a DPO7000 series oscilloscope.

You can find a PDF (portable document format) file for this document in the Documents directory on the
Optional Applications Software on Windows-Based Oscilloscopes DVD. The DVD booklet contains
information on installing the application from the DVD and on how to apply a new label.
Table 2: Icon descriptions
Icon Meaning
This icon identifies important information.

This icon identifies conditions or practices that could result

in loss of data.

This icon identifies additional information that will help you

use the application more efficiently.

xxx

Technical Support
Tektronix welcomes your comments about products and services. Contact Tektronix through mail,
telephone, or the Web site. Click Contacting Tektronix for more information. Tektronix also welcomes
your feedback. Click Customer feedback for suggestions for providing feedback to Tektronix.

4 DDR Analysis
Introduction to the Application Customer Feedback

Customer Feedback
Tektronix values your feedback on our products. To help us serve you better, please send us your
suggestions, ideas, or other comments you may have regarding the application or oscilloscope.
Direct your feedback via e-mail to
techsupport@tektronix.com
Or FAX at (503) 627-5695, and include the following information:

General Information
Oscilloscope model number (for example: DPO7000C or DSA/DPO/MSO70000C/D/DX series)
and hardware options, if any.
Software version number.
Probes used.

Application-specific Information
Description of the problem such that technical support can duplicate the problem.
If possible, save the oscilloscope and application setup files as .set and associated .xml files.
If possible, save the waveform on which you are performing the measurement as a .wfm file.
Once you have gathered this information, you can contact technical support by phone or through e-mail.
In the subject field, please indicate “DDRA Problem” and attach the .set, .xml and .wfm files to your
e-mail. If there is any query related to the actual measurement results, then you can generate a .mht report
and send it. If you need to send very large files, technical support can assist you to transfer the files
via ftp (file transfer protocol).
The following items are important, but optional:
Your name
Your company
Your mailing address
Your phone number
Your FAX number
Enter your suggestion. Please be as specific as possible.
Please indicate if you would like to be contacted by Tektronix regarding your suggestion or comments.

DDR Analysis 5
Introduction to the Application Customer Feedback

6 DDR Analysis
Getting Started Product Description

Product Description
DDR Analysis is a standard specific solution tool for Tektronix Performance Digital Oscilloscopes
(DPO7000C or DSA/DPO/MSO70000C/D/DX series). DDR Analysis requires Jitter and Eye Diagram
Analysis Tool (Opt.DJA) and the advanced Search and Mark capability (Opt. ASM).
The features of DDRA are:
Provides debug, analysis, and compliance in one solution for multiple DDR standards such as DDR
(see page 1), DDR2 (see page 2), DDR3 (see page 2), DDR3L (see page 2), DDR4 (see page 2).
LPDDR (see page 2), LPDDR2 (see page 2), LPDDR3 (see page 2), GDDR3 (see page 2), and
GDDR5 (see page 3).
Identifies Read and/or Write operations automatically
Custom data rates and input levels to tailor DDRA Read and/or Write burst identification
Provides both single-ended and differential measurements on Data, Strobe, Clock, Address and
Command signals
Analyze compliance measurements either through DDRA or Jitter and Eye Diagram Analysis Tool
Limit files to test measurement pass/fail status
Automatically applies signal slew rate derating of measurement limits for Address/Command and
data signals
Preferences shortcut available for all DDRA steps. For more details, refer to the DPOJET online help.
Logic state configuration using the DDRA user interface.

DDRA Prerequisites
To use the DDRA application on instruments using 32-bit operating systems, you need Opt. ASM
(Advanced Search and Mark Tool) and DPOJET Advanced (Opt. DJA) enabled.

Requirements and Restrictions

DPOJET (DJA) is required to operate DDRA on your oscilloscope. Also refer to subsequent requirements
for DPOJET.

DDR Analysis 7
Getting Started Supported Probes

Supported Probes
The application supports the following probes:
TAP2500
TAP1500
TCP0030
P6158
P6101B
P6246
P6247 (DPO7254 only)
P6248 (DPO7254 only)
P6249
P6150
P6158
P7240
P7260
P7330
P7340A
P7350
P7360A
P7380A
P7313A
P7513
P7520A
P7520
P7500 Series TriMode

8 DDR Analysis
Getting Started Installing the Application

Installing the Application

Refer to the Optional Applications Software on Windows-Based Oscilloscopes Installation Manual for the
following information:
Software warranty.
List of available applications, compatible oscilloscopes, and relevant software and firmware version
numbers.
Applying a new option installation key label.
Installing an application.
Enabling an application.
Downloading updates from the Tektronix Web site.
You can find a PDF (portable document format) file for this document in the Documents directory on the
Optional Applications Software on Windows-Based Oscilloscopes DVD. The DVD booklet contains
information on how to install the application from the DVD and on how to apply a new option installation
key label.

DDR Analysis 9
Getting Started About DDRA

About DDRA
Click Help > About DPOJET to view DDRA application details such as the software released version
number, application name and copyright.

NOTE. The version displayed above is indicative only, the version number displayed will vary depending
upon the exact version of the application installed.

10 DDR Analysis
Operating Basics Starting the Application

Starting the Application

On the oscilloscope menu bar, click Analyze > DDR Analysis to open the application.

Menu Controls
Table 3: Application Menu Controls descriptions
Item Description
Tab Shortcut to a menu in the menu bar or a category of menu
options; most tabs are short cuts.
Area Visual frame with a set of related options.
Option button Button that defines a particular command or task.
Field Box that you can use to type in text, or to enter a value with
the Keypad or a Multipurpose knob.
Check Boxes Use to select configuration options or clear preferences.
Browse Displays a window where you can look through a list of
directories and files.
Command button Button that initiates an immediate action such as Run
command button in the control panel.
Click to use on-screen keypad to enter alphanumeric values.
Virtual Keypad icon
MP knob references (a or b) Identifiers that show which Multi Purpose Knob (MPK) may
be used as an alternate means to control a parameter;
turn the knob on the oscilloscope front panel to adjust the
corresponding parameter. Also, the value can be entered
directly on the MPK display component.
xxx

DDR Analysis 11
Operating Basics Virtual Keypad

Virtual Keypad

Select the icon and use the virtual keypad to enter alphanumeric values, such as reference voltage
levels.

Tips on the DDRA User Interface

Here are some tips to help you with the application user interface:

Use the Single button to obtain a set of measurements from a single new waveform acquisition.
Pushing the button again before processing has completed will interrupt the processing cycle.

Use the Run button to continuously acquire and accumulate measurements. If prior
measurements have been acquired and have not been cleared, the new measurement are added to the
existing set. Push the button again to interrupt the current acquisition.

Use the Recalc button to perform measurements on the waveform currently displayed on the
oscilloscope without performing a new acquisition. This is useful if you wish to modify a configuration
parameter and re-run the measurements on the current waveform.

Use the Clear button to clear all existing measurement results. Note that adding or deleting
a measurement, or changing a configuration parameter of an existing measurement, will also cause
measurements to be cleared. This is to prevent the accumulation of measurement statistics or sets of
statistics that are not coherent.

12 DDR Analysis
Operating Basics Application Directories

Application Directories
The installation directory for DDRA executable files is C:\Program Files\TekApplications\DDRA
and the installation directory for user files is C:\TekApplications\DDRA for oscilloscope running with
Windows-XP operating system and C:\Users\Public\Tektronix\TekApplications\DDRA for
oscilloscopes running with Windows7 operating system. During installation, the application sets up a limits
folder in the user directory. This folder contains limit files for various DDR standards and speed grades.
For 64-bit systems, the DDRA installer copies the symbol files into the following location:
C:\Users\Public\Tektronix\TekScope\BusDecodeTables\DDR. This is different from the default
TekScope location at C:\Users\[Username]\Tektronix\Tekscope\BusDecodeTables.

File Name Extensions

Table 4: File name extensions
File Extension Description
.csv An ascii file containing Comma Separated Values. This
file format may be read by any ascii text editor (such as
Notepad) or may be imported into spreadsheets such as
Excel.
.xml An ascii file containing measurement setup information,
limits or other data in Extensible Markup Language.
.set A binary file containing oscilloscope setup information in
a proprietary format.
.mht An HTML archive file, compatible with common Windows
applications; contains the full report, including text and
graphics.
.wfm A binary file containing an oscilloscope waveform record in
a recallable, proprietary format.
.tsf A symbol file containing various symbols for various logic
trigger patterns.
xxx

Returning to the Application

When you access oscilloscope functions, the DDRA control windows may be replaced by the oscilloscope
control windows or by the oscilloscope graticule. You can access oscilloscope functions in the following
ways:
From the menu bar on the oscilloscope, choose Analyze > DDR Analysis.
Alternatively, you can switch between recently used control panels using the forward or backward
arrows on the right corner of the control panel.

DDR Analysis 13
Operating Basics Control Panel

Control Panel
The Control Panel appears on the right of the application window. Using this panel, you can start or stop the
sequence of processes for the application and the oscilloscope to acquire information from the waveform.
The controls are Clear, Recalc, Single, and Run. The following table describes each of these controls:

Item Description
Clear Clears the current result display and resets any statistical
results and autoset ref levels. For any input sources that
have reference level autoset enabled, clears the current
ref levels so that they will be recalculated during the next
acquisition.
Recalc Runs the selected measurements on the currently displayed
waveform(s), without first performing a new acquisition.
Single Initiates a single new acquisition and runs the selected
measurements.
Run Initiates new acquisitions and runs the selected
measurements repeatedly until Stop is clicked. For any
non-live sources (Reference waveforms or Math waveforms
not dependent on a live channel), only a single processing
cycle will occur.
Show Plots Displays the plot summary window when clicked. This
button appears in the control panel only when one or more
plots have been defined.
Advanced Setup DPOJET Transitions to the Jitter and Eye Diagram Analysis
application when clicked, importing all currently defined
DDRA measurements. This button appears in the control
panel when you open the DDR analysis application. This
is useful if you wish to add additional measurements
not defined in DDRA, or wish to change measurement
configurations to intentionally deviate from those
recommended by DDRA.
xxx

14 DDR Analysis
Operating Basics Saving a Setup

Saving a Setup
The DDRA application state is automatically saved along with the oscilloscope state. To save the
oscilloscope settings and the application state, follow these steps:
1. Click File > Save As > Setup.
2. In the file browser, select the directory to save the setup file.
3. Select or enter a file name. The application appends *_DDRA.xml and *_DPOJET.xml to store the
DDR setup, and *.set to store the oscilloscope settings.
4. Click Save.

NOTE. After the oscilloscope application is started, DDRA needs to be launched at least once before
any saved DDRA configuration can be recalled.

Recalling a Saved Setup

To recall a previously saved set of application and oscilloscope settings, do the following steps:

NOTE. While recalling setup files with both DDRA and DPOJET saved settings, DDRA setup values get a
higher precedence over DPOJET setup values. For example: Select a DPOJET measurement and a DDRA
measurement, change the ref levels of DPOJET measurement and save the setup file. On recalling the setup
file, you will see that the DPOJET ref level settings are overwritten by the DDRA measurement ref levels.

1. Click File > Recall...

2. Click Setup in the left column if it is not already selected.
3. Select the directory in the file browser from which you wish to recall the setup file.
4. Select a .set file and click Recall.

NOTE. Only .set files can be selected for recall; any corresponding *_DDRA.xml and *_DPOJET.xml
file in the same directory will be recalled as well, if DDRA has been launched at least once since the
oscilloscope application was started. If DDRA has not been launched at least once, the oscilloscope
settings will be recalled but the DDRA configuration will be ignored.

DDR Analysis 15
Operating Basics Recalling the Default Setup

Recalling the Default Setup

To recall the default application and oscilloscope settings, click File > Recall Default Setup.

NOTE. Recalling default setup sets the DDRA application to DDR3 generation and data rate, None.

Limits
A limits file allows you to configure the limits used to determine Pass or Fail status for tests. Each limits
file includes a list of one or more measurements, and the ranges of acceptable values for any or all statistics
for each measurement that include combinations of all measurements and statistical characteristics, and an
appropriate range of values for each combination.
The application provides preconfigured limits files for many combinations of standards and speed grades.
You can create one by specifying limits for any of the result parameters such as Mean, Std Dev, Max, Min,
peak-to-peak, population, MaxPosDelta and MinPosDelta. For each of these result parameters, you can
specify the Upper Limit Equality (ULE), Lower Limit Equality (LLE), or Both. The measurement names
in the limits file must be entered as mentioned in About DDR Analysis.
To include Pass/Fail status in the result statistics, you can create a custom limits file in the following
format using an XML editor or any other editor. If the file is created in any other editor such as Notepad,
it should be saved in Unicode format.
The following is a sample of the limit file for DDR2 generation, the data rate being 667 MHz
<?xml version="1.0" encoding="utf-16" ?>
<Main>
<Measurement>
<NAME>DDR Hold–Diff</NAME>
<STATS>
<STATS_NAME>Min</STATS_NAME>
<LIMIT>BOTH</LIMIT>
<ULE>175e-12</ULE>
<LLE>0</LLE>
</STATS>
</Measurement>
<Measurement>
<NAME>tDH-Diff(base)</NAME>
<STATS>
<STATS_NAME>Min</STATS_NAME>
<LIMIT>BOTH</LIMIT>
<ULE>175e-12</ULE>
<LLE>0</LLE>
</STATS>
</Measurement>
</Main>

16 DDR Analysis
Operating Basics Search and Mark

You can find limit files for various data rates of different DDR standards and speed bins at
C:\TekApplications\DDRA\Limits.

NOTE. Base limit values change based on the selected AC configuration at Step 6 (see page 51). For
DDR3 1333 MT/s and 1600 MT/s, AC 150 ref level are applied independent of the specified AC config.

Search and Mark

The data rate, generation, and measurement type selected in DDRA are also set in Advanced Search and
Mark (ASM). Marks are available only for Read and Write bursts measurement type. You can configure
Search using Advance > Search > Configure. The identified bursts are shown as small inverted marks
( ) in the oscilloscope display area. Each pair of marks specifies the start and stop of a burst. You can
traverse from one mark to the other using the Mark Control window. For more details, refer to your
oscilloscope online help.

DDR Analysis 17
Operating Basics Dynamic Limits

Dynamic Limits
The application supports both static (predefined using limits file) and dynamic limits. Dynamic limits
are available only for DDRA clock measurements. They are calculated using the result of other
measurement(s).
The concept of dynamic limits is explained taking an example of a measurement, tCH(avg):
If the dynamic limits of a measurement depend on the result of other measurement(s) that has not
yet been calculated, the limit text field in the results panel shows “Derived...”. A tool tip displays the
message “This limit is calculated based on measurement tCK(avg)”.

On clicking Run/Single, the results are shown in the following figure:

If there is an error in calculating dynamic limits, the limit text field displays “Error...” as shown. A
tool tip displays the message “This limit is calculated based on measurement tCK(avg)”.

18 DDR Analysis
Operating Basics DDR Standards and their Measurements

References
Dynamic Limits for LPDDR Measurements (see page 108)
Dynamic Limits for LPDDR2 Measurements (see page 109)
Dynamic Limits for DDR Measurements (see page 111)
Dynamic Limits for DDR2 Measurements (see page 112)
Dynamic Limits for DDR3 Measurements (see page 113)

DDR Standards and their Measurements

The following table lists the measurements displayed for each DDR standard:

NOTE. For more details on the measurements, refer to the Algorithms section.

‡ †
‡

Measurements
Write Bursts
Data Eye Width
Data Eye Height
tWRSRE
tWRPDE
Differential DQS
Input Slew-Diff-Fall(DQS)
Input Slew-Diff-Rise(DQS)
tDH-Diff(base)
tDH-Diff(derated)
tDH-Diff(Vref-based)
tDQSH
tDQSL
tDS-Diff(base)
tDS-Diff(derated)
tDS-Diff(Vref-based)
tDSS-Diff
tDQSS-Diff
tDSH-Diff
TdIPW-High
TdIPW-Low

DDR Analysis 19
Operating Basics DDR Standards and their Measurements

‡ †
‡

Measurements
VIHL-AC
SRIN_dIVW_Rise
SRIN_dIVW_Fall
tDVAC(DQS)
Single Ended DQS
Slew Rate-Hold-SE-
Fall(DQS)
Slew Rate-Hold-SE-
Rise(DQS)
Slew Rate-Setup-SE-
Fall(DQS)
Slew Rate-Setup-SE-
Rise(DQS)
tDH-SE(base)
tDH-SE(derated)
tDIPW-SE
tDS-SE(base)
tDS-SE(derated)
tDIPW-SE
tDQSS-SE
tDSH-SE
tDSS-SE
Slew Rate DQ
Slew Rate-Hold-Fall(DQ)
Slew Rate-Hold-Rise(DQ)
Slew Rate-Setup-Fall(DQ)
Slew Rate-Setup-Rise(DQ)
tDQSS
RX Mask
tWPRE
tWPST
Read Bursts
Data Eye Width
Date Eye Height
tRDSRE
tRDPDE
Differential DQS

20 DDR Analysis
Operating Basics DDR Standards and their Measurements

‡ †
‡

Measurements
tAC-Diff
tDQSCK-Diff
tDQSQ-Diff
tDVAC(DQS)
tQH
tQSL
tLZ(DQS)
tHZ(DQS)
tQSH
SRQdiff-Rise(DQS)
SRQdiff-Fall(DQS)
Single Ended DQS
tDQSCK-SE
tDQSQ-SE
Vox(ac)DQS
Slew Rate (DQ)
SRQse-Fall(DQ)
SRQse-Rise(DQ)
tLZ(DQ)
tHZ(DQ)
tDQSCK
tRPRE
tRPST
Clock (Diff) ‡

tCH(abs)
tCH(avg)
tCK(abs)
tCK(avg)
tCL(abs)
tCL(avg)
tDVAC(CK)
tERR
(Includes measurements
from tERR2 to 49per)
tERR(11–50per)
tERR(2per)

DDR Analysis 21
Operating Basics DDR Standards and their Measurements

‡ †
‡

Measurements
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6–10per)
tJIT(cc)
tJIT(duty)
tJIT(per)
tHP
VID(ac)
Input Slew-Diff-Rise(CK)
Input Slew-Diff-Fall(CK)
tDVAC(CK)
tCK
tCH
tCL
SSC Downspread (CK)
SSC Mod Freq (CK)
Clock (Single Ended)
AC-Overshoot(CK#)
AC-Overshoot(CK)
ACOvershootArea(CK#)
ACOvershootArea(CK)
AC-Undershoot(CK#)
AC-Undershoot(CK)
AC-UndershootArea(CK#)
AC-UndershootArea(CK)
VIXCA
Vix(ac)CK
Vox(ac)CK
VSWING(MAX)CK
VSWING(MAX)CK#
VSEH(AC)CK
VSEH(AC)CK#
VSEH(CK#)
VSEH(CK)
VSEL(AC)CK

22 DDR Analysis
Operating Basics DDR Standards and their Measurements

‡ †
‡

Measurements
VSEL(AC)CK#
VSEL(CK#)
VSEL(CK)
VIN(CK)
VIN(CK#)
CKSlew-Rise(CK)
CKSlew-Rise(CK#)
CKSlew-Fall(CK)
CKSlew-Fall(CK#)
DQS (Single Ended)
AC-Overshoot(DQ)
AC-Undershoot(DQ)
AC-Overshoot(DQS#)
AC-Overshoot(DQS)
AC-OvershootArea(DQ)
AC-UndershootArea(DQ)
AC-OvershootArea(DQS#)
AC-OvershootArea(DQS)
AC-Undershoot(DQS#)
AC-Undershoot(DQS)
AC-UndershootArea(DQS)
AC-Under-
shootArea(DQS#)
Vix(ac)DQS
VIXDQ
VSWING(MAX)DQS
VSWING(MAX)DQS#
VSEH(AC)DQS
VSEH(AC)DQS#
VSEH(DQS#)
VSEH(DQS)
VSEL(AC)DQS
VSEL(AC)DQS#
VSEL(DQS#)
VSEL(DQS)
DQS (Single Ended, Read)

DDR Analysis 23
Operating Basics DDR Standards and their Measurements

‡ †
‡

Measurements
AC-OvershootArea(DQ)
AC-UndershootArea(DQ)
AC-Overshoot(DQ)
AC-Undershoot(DQ)
AC-OvershootArea(DQS)
AC-UndershootArea(DQS)
AC-Overshoot(DQS)
AC-Undershoot(DQS)
AC-OvershootArea(DQS#)
AC-Under-
shootArea(DQS#)
AC-Overshoot(DQS#)
AC-Undershoot(DQS#)
Vox(ac)DQS
Address/Command
AC-Overshoot
AC-OvershootArea
AC-Undershoot
AC-UndershootArea
InputSlew-Diff-Fall(CK)
InputSlew-Diff-Rise(CK)
Slew Rate-Hold-
Fall(Addr/Cmd)
Slew Rate-Hold-
Rise(Addr/Cmd)
Slew Rate-Setup-
Fall(Addr/Cmd)
Slew Rate-Setup-
Rise(Addr/Cmd)
tIH(base)
tIH(base)CA
tIH(base)CS
tIH(derated)CA
tIH(derated)CS
tIPW-High(CA)
tIPW-High(CS)
tIPW-Low(CA)

24 DDR Analysis
Operating Basics DDR Standards and their Measurements

‡ †
‡

Measurements
tIPW-Low(CS)
tIS(base)CA
tIS(base)CS
tIS(derated)CA
tIS(derated)CS
tIS(base)
tIS(derated)
tIH(derated)
tIPW-High
tIPW-Low
tDIPW
tCMDS
tCMDH
tCHDPW
tAS
tAH
tAPW
WCK (Differential)
tWCK-Rise-Slew
tWCK-Fall-Slew
tWCK-TJ
tWCK-DJ
tWCK-RJ
VWCK-Swing
tDVAC(WCK)
tWCK
tWCKH
tWCKL
tWCKHP
SSC Downspread (WCK)
SSC Mod Freq (WCK)
SSC Profile(WCK)
WCK (Single Ended)
VIN(WCK)
VIN(WCK#)
VIX(AC)WCK

DDR Analysis 25
Operating Basics DDR Standards and their Measurements

‡ †
‡

Measurements
VOL(WCK)
VOH(WCK)
VOL(WCK#)
VOH(WCK#)
WCKSlew-Rise(WCK)
WCKSlew-Rise(WCK#)
WCKSlew-Fall(WCK)
WCKSlew-Fall(WCK#)
Refresh
tCKSRE
tCKSRX
tRFC
tXSNRW
tREFTR(Write)
tREFTR(Read)
Power Down
tPD
Active
tRC
tRAS
tRCDRD
tRCDWR
Precharge
tPPD
tRP
tRP(ACT)
tRP(MRS)
tRP(REF)

26 DDR Analysis
Operating Basics Derating

‡ †
‡

Measurements
tRP(SRE)
tRTPL
xxx

‡ The clock measurements displayed for LPDDR and DDR standards are tCH, tCK, tHP, and tCL.
† The application displays a hint on selecting GDDR3 as the standard: “GDDR3 not completely supported. Some features may not function”.

Derating
Signal slew rate derating is required to verify the setup and hold timing requirements on address/command
and data signals. The base setup and hold limits are defined using input signals that have a 1.0 V/ns slew
rate. To determine final pass/fail status, the limits must be adjusted based on the actual slew rates of the
target signals, according to derating tables appearing in the DDR2 and DDR3 specifications.
DDR2 derated measurements for data signals are as follows:
tDS-SE(derated)
tDH-SE(derated)
tDS-Diff(derated)
tDH-Diff(derated)
DDR3 derated measurements are as follows:
tDS-Diff(derated)
tDH-Diff(derated)
The DDR2/DDR3 Address/Command derated measurements are as follows:
tIH(derated)
tIS(derated)
The derated value (Δ) is calculated as per the JEDEC standard using either the DDR Method or Nominal
Method, depending on the user configuration.
Derating is explained taking an example of Setup(tIS) measurement. The same concept is applicable for
other derated measurements.

When the nominal method is set, Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate
between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for

DDR Analysis 27
Operating Basics Derating

a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of
VIL(ac)max.

If the DDR Method is set, the application takes the maximum slope. This method is applicable if the actual
signal is earlier than the nominal slew rate line.

28 DDR Analysis
Operating Basics Derating

According to the specified reference levels, rise slew rate is always positive whereas fall slew rate is
negative. A single slew rate value is obtained by averaging the absolute values of rise and fall slew
rate. Using this value and a similarly-derived slew rate for the clock signal, the total setup time (tIS) is
calculated by adding ΔtIS to the tIS(base)limit from the following table:
Table 5: Address/Command Setup and Hold Values
Units(ps) DDR3–800 DDR3–1066 DDR3–1333 DDR3–1600 Units
tIS(base) AC 175 200 125 65 45 ps
tIS(base) AC150 350 275 190 170 ps
tIH(base) 275 200 140 120 ps
xxx

NOTE. For DDR3 speeds 1333 and 1600 MT/s, the AC 150 reference levels are applied, though the default
selection in the Step 6 (see page 51) is AC175.

ΔtIS is determined using the derating table (AC 175 (see page 53)), where the Y-axis represents
the Address/Command slew rate and the X-axis, the clock differential value. By indexing the
Address/Command value and Clock differential value, ΔtIS value is obtained from AC175 table.
The calculated slew rate is approximated to the derating table specified value (Example: 0.4 V/ns ≈
1.0V/ns). For values greater than 4.0 V/ns, the table returns the base limit value.
For example: For a Clock differential value= 1.0 V/ns, Address/Command Slew Rate =1.0 V/ns, and AC
175 Threshold selected in Step 6 (see page 51), the resulting derated values are:
tISderatedlimit= tIS(base)limit+ΔtIS.
tISderatedlimit= 200+ 40= 240

The result statistics of the both tIS(base) and tIS(derated) are the same as shown in the following figure. In
case of derating, the limit values get changed depending on the signal slew rate.

Reference
DDR3 Measurement Sources (see page 100)
DDR2 Measurement Sources (see page 89)

DDR Analysis 29
Operating Basics About DDR Analysis

About DDR Analysis

The DDR Analysis window allows you to select various standards, set up and run a pre-configured
measurement either through the DDRA or the DPOJET application.
Select Analyze > DDR Analysis to open the DDRA application.
The setup panel in the DDR Analysis application includes the following steps:
Generation, Rate and Levels (see page 31)
Interposer Filter (see page 34)
Measurements and Sources (see page 35)
Burst Detection Method (see page 40)
Burst Detection Settings (see page 40)
Thresholds and Scaling (see page 51)

NOTE. You can use the Next/Prev buttons or click directly on the step numbers to traverse through the

steps in the DDR Analysis. The steps for which configuration is complete are denoted .

The setup panel displays hints to help you understand the configuration options wherever applicable.
You can run a set of measurement in either of the two ways:
Click Run to start the acquisition sequence using the selected settings and to view the results in the
DDRA window. This is the normal way to generate results.

Click to move to the DPOJET application, where you can add or modify
measurements before sequencing. For more details, refer to the DPOJET Online Help. You need to

click in the DPOJET application to return to the DDRA window. Alternatively, you can
reselect Analyze >DDR Analysis from the menu bar.

30 DDR Analysis
Operating Basics Step1: Generation, Rate and Levels

Step1: Generation, Rate and Levels

Select the DDR generation, data rate and the voltage levels (if required). There are different speed bins for
each standard data rate for specific DDR generations.

1. Select the DDR Generation from the drop-down list.

2. Select the Data Rate from the drop-down list. On selecting Custom, an edit box allows you to enter the
value using the virtual keypad. Limit files are not defined for custom data rates for Pass/Fail status and
as a result the application displays a hint at the bottom of the screen “Please provide a limits file under
Jitter and Eye > Limits”. Note that selecting non-standard data rates in ASM (under Search > DDR
Read or DDR Write), changes the data rate to “None” in DDRA.
3. Set the voltage levels:
If you select JEDEC Defaults, the application uses the nominal voltage levels according to the
JEDEC specification.
If you select User Defined, enter the Vdd (see page 31) or Vref (see page 31) voltage values
using the virtual keypad.
4. (Optional) Click View to view the Vih (see page 34) and Vil (see page 34) values calculated
automatically based on the Vref value. To manually adjust the reference levels, go to Step6 (see
page 51) of DDRA or use the DPOJET source configuration panel.

Vdd
Is the supply voltage for each DDR standard. Vdd is based on DDR generation.

Vref
Is the reference voltage for each DDR standard. Vref is calculated using Vdd, which in turn is based
on DDR generation. In most cases, Vref=0.5Vdd.

DDR Analysis 31
Operating Basics Step1: Generation, Rate and Levels

The following table lists the minimum and maximum values of Vdd and Vref in the User Defined mode
for all DDR generations:
DDR
Generations Vdd Vref
Default Min Max Default Min Max
DDR ‡ 2.5 V –6 V 6V 1.25 V –6 V 6V
DDR2 1.8 V –6 V 6V 900 mV –6 V 6V
DDR3 1.5 V –6 V 6V 750 mV –6 V 6V
DDR3L 1.35 V –6 V 6V 675 mV –6 V 6V
DDR4 1.2 V –6 V 6V 600 mV –6 V 6V
LPDDR 1.8 V –6 V 6V 900 mV –6 V 6V
LPDDR2 1.2 V –6 V 6V 600 mV –6 V 6V
LPDDR3 1.2 V –6 V 6V 600 mV –6 V 6V
GDDR3 1.8 V –6 V 6V 900 mV –6 V 6V
GDDR5 1.5 V –6 V 6V 750 mV –6 V 6V
xxx

‡ DDR 400 MT/s has Vdd value set to 2.6 V and Vref Value set to 1.3 V.

NOTE. If you select Manual Threshold Settings in Step 6 and then subsequently choose user-defined
Vdd or Vref voltages in Step 1 , the following message is displayed “You have selected manual control
of measurement thresholds in Step 6. Please verify that they are appropriate for these settings”. This is
because the Vref voltage is normally used to determine the proper high, mid, and low thresholds. If these
thresholds are under manual control, there is no point in manually setting Vref.

32 DDR Analysis
Operating Basics Step1: Generation, Rate and Levels

Vdd and Vref

The configured values of Vdd and Vref are used to calculate VIH(ac)min, VIH(dc)min, VIL(dc)max and
VIL(ac)max, which are applied on the input signal. These levels are further used for calculating Setup
and Hold measurements.

For DDR2, the relationship between Vdd and Vref is as shown in the following tables:
Table 6: Input DC logic Level
Symbol Parameter Min Max Units
VIH(dc) DC input logic high Vref+0.125 – V
VIL(dc) DC input logic low –0.3 Vref–0.125 V
xxx

Table 7: Input AC logic Level

Symbol Parameter DDR2–400, DDR2–533 DDR2–667,DDR2–800 Units
Min Max Min Max
VIH(ac) AC input logic Vref+0.250 – Vref+0.200 – V
high
VIL(ac) AC input logic – Vref–0.250 – Vref+0.200 V
low
xxx

NOTE. Similar reference voltage levels are defined for DDR3 standard.

Speed Bins
For each DDR standard, the DDRA application automatically applies limits appropriate for the standard
data rates without speed bins. Limit values are different for different speed bins. If you want to test
according to a speed bin, you must manually configure the limit values from within DPOJET by manually
overriding the limit file before running the measurements.
For more details, refer to the topic “Limits” of the DPOJET help.

The following table lists the speed bins available for which pre-configured limit files are provided:
DDR Generation Speed bins
DDR-400 400A, 400B and 400C
DDR2
DDR2-667 800C and 800D
DDR2-800 800C, 800D and 800E
DDR3
DDR3-800 800D and 800E
DDR3-1066 1066E, 1066F and 1066G

DDR Analysis 33
Operating Basics Step2: Interposer Filter

DDR Generation Speed bins

DDR3-1333 1333F *, 1333G, 1333H and 1333J *
DDR3-1600 1600G †, 1600H, 1600J and 1600K †
xxx

* 1333F and 1333J are optional

† 1600G and 1600K are optional

NOTE. You can find limit files for various speed bins at C:\TekApplications\DDRA\Limits. You need
to manually select these limit files by clicking Analyze > Jitter and Eye Analysis > Preferences > Limits.

Vih
Is the input logic HIGH voltage.

Vil
Is the input logic LOW voltage.

Step2: Interposer Filter

Select interposer and its probing configuration for CLK and DQS signal. When interposer filters are
applied, MATH cannot be used as the measurement source in Step 3. The filter file will be applied when
the scope acquisition sample rate is supported in the filter file. You can also specify a user-defined filter
file by selecting the “User Defined” option from the drop-down list.

34 DDR Analysis
Operating Basics Step3: Measurements and Sources

Step3: Measurements and Sources

Select measurements and their corresponding sources (see page 39) in this step. Measurement availability
depends on the selected DDR standard. Select the Measurement Type (Read Bursts, Write Bursts,
Clock(Diff), Clock(Single Ended), Address/Command, Address/Command, DQS(Single Ended),
WCK(Single Ended), WCK(Diff), Refresh, Power Down, Active, or Precharge) from the drop-down list.
WCK(Single Ended), WCK(Diff), Refresh, Power Down, Active, or Precharge are only available for
GDDR5. Power Down, Active, and Precharge are only available 64-bit instruments. A message prompts
you to select one or more measurements before moving to the next step.

Measurement Type Reference Levels

The voltage reference levels for each measurement are automatically set to be consistent with JEDEC
guidelines unless they are manually overridden. In cases where none of the chosen measurements
have any applicable guidelines or manually set levels, DDRA will automatically choose reference
levels based on the signal's maximum and minimum levels. DDRA displays a hint if both Single Ended
DQS and Differential DQS measurements are selected at the same time, and measurements made with
this configuration may not be accurate due to conflicting ref level requirements. When two or more
measurements are selected in different sub-node categories under a Measurement Type the following
precedence is set for measurement ref levels:
Slew Rate ref levels
Single Ended specific ref levels
Differential specific ref levels
For Example: When Eye Width measurement is selected along with Differential DQS or Single Ended
DQS or Slew Rate measurements, Eye measurement may not produce the expected results. This is because
the actual mid level needed by Eye Width gets overwritten with SE levels and hence produces no results.

DDR Analysis 35
Operating Basics Step3: Measurements and Sources

Tree Structure Flow

The measurement tree structure is as follows:
The tree structure displays only those measurements appropriate for the selected measurement type.

All generations except GDDR3 display both parent and nested elements under measurement type
(such as tERR) as shown:

Click to expand and show the elements within the parent element.

Click to collapse and hide the elements within the parent element.

36 DDR Analysis
Operating Basics Step3: Measurements and Sources

Selecting the parent check box, selects all the children elements. Selecting all the children elements,
selects the parent element.

Clearing the parent check box clears all the children elements.
When the children include both checked and unchecked elements, the parent element becomes
highlighted as shown:

NOTE. If you move to the next step without selecting any measurements, the application displays the
message “Please select measurements in Step3”.

DDR Analysis 37
Operating Basics Step3: Measurements and Sources

Measurement Selection Based on Signal Type

The application adds the suffix SE (Single-ended) or Diff ( Differential) for relevant measurements
depending on the signal type.
If your signal type is differential, the measurements with suffix Diff should be selected and those with
SE should be deselected. The signal should be probed with a differential probe. If only one leg of
a differential signal is probed (using a single-ended probe), the automatically-configured reference
levels will not be correct. This can be resolved by using a Math waveform as the source, and
defining the Math so that the single-ended signal is centered around 0 V. This will not be a proper
JEDEC-compliant measurement but it will allow the measurements and/or eye diagram to function.
If your signal type is single-ended, the measurements with suffix SE should be selected and those with
Diff should be deselected. Some measurements on differential signals demand that the two legs of the
differential signal be separately probed with single-ended probes. These measurements are placed in
measurement types that segregate them from measurements made with a differential probe.

NOTE. The application displays a hint “Cannot select Diff and SE measurements at the same time” when
measurements with suffix SE and Diff are selected together under Write Bursts.

Timing error (tERR) measurements

Timing error measurements for the DDR3 generation such as tERR(2per), tERR(3per) until
tERR(50per) are grouped together and included as a nested element (tERR) under the parent element,
Clock(Diff)measurements. Selecting tERR selects all the timing error measurements.

38 DDR Analysis
Operating Basics Step3: Measurements and Sources

Sources
Select a measurement to view the sources available for the measurement. The sources are mutually
exclusive. For each required signal, select the appropriate source. A tool tip displays the required sources
for the selected measurement at the nodes of the measurement tree. A maximum of four analog sources
are available at a time.

NOTE. If the same channels are used for DQ/DQS/Clock sources (Example: DQ=Ch1, DQS=Ch1),
the application displays a hint “Cannot use the same waveform for different sources”. If Live and Ref
channels are used together (Example: Ch1 for DQS and Ref2 for DQ), the application displays a hint
“Cannot use Live and Ref waveforms together”.

Reference
Hints (see page 56)
LPDDR Measurement Sources (see page 75)
LPDDR2 Measurement Sources (see page 77)
DDR Measurement Sources (see page 86)
DDR2 Measurement Sources (see page 89)
DDR3 Measurement Sources (see page 100)
GDDR5 Measurement Sources (see page 104)

DDR Analysis 39
Operating Basics Step4: Burst Detection Method

Step4: Burst Detection Method

Burst Detection is based on the measurement type and generation, and is applicable only for Write Bursts,
Read Bursts, and DQS(Single Ended) measurement types.

The application supports the following burst detection methods for DPO/DSA/MSO oscilloscopes:
DQ/DQS Phase Alignment (see page 41)
Chip Select, Latency + DQ/DQS Phase Alignment (see page 43)
Logic State + Burst Latency (see page 44) (Available only for MSO series of oscilloscopes)
Visual Search (see page 47)

Reference
Hints (see page 56)

Step5: Burst Detection Settings

Displays the settings based on the burst detection method:
DQ/DQS Phase Alignment (see page 41)
Chip Select, Latency+ DQ/DQS Phase Alignment (see page 43)
Logic State + Burst Latency (see page 44) (Available only for MSO series of oscilloscopes)

40 DDR Analysis
Operating Basics DQ/DQS Phase Alignment

DQ/DQS Phase Alignment

Select the burst detection method as shown:

The DQ/DQS levels indicator shows "Auto" when both Strobe/Data and Edge detection hysteresis are
set to Auto. If one of the options is Manual, then the DQ/DQS levels shows as Manual. Click Settings
tab to set advanced burst detection parameters.

The burst detection settings panel controls how data bursts are identified within a waveform that includes
tri-state levels. For appropriately-probed signals with good signal fidelity, no adjustment to the default
values should be required. For signals with poor fidelity or unusual properties, burst detection can be
improved by switching to Manual control and adjusting the detection levels.

DDR Analysis 41
Operating Basics DQ/DQS Phase Alignment

NOTE. The High/Mid/Low levels used for burst detection have no relationship to the reference levels used
for measurement points. The measurement thresholds are defined in Step 6 (see page 51).

1. Select the type of burst detection level for the search.

If you select Auto, the application calculates these levels for you . It is recommended unless you
find that manual levels are necessary for reliable detection.
If you select Manual, enter both the Strobe and Data reference levels for the signal (High, Mid,
and Low). As you adjust the detection levels, observe the search-and-mark sprites that appear
above the waveform. These sprites are dynamically updated as you adjust the levels, helping you
to identify levels that properly delimit the selected burst type.
2. These settings need not be changed in most cases:
Edge Detection Hysteresis: This control configures the internal edge finder’s hysteresis band
which is used to detect read or write bursts. In the event of noisy inputs, it can be increased to
correct marks which may be larger than appropriate.
Termination Logic Margin: This control can be increased to help in terminating marks on
back-to-back writes in cases where otherwise a continuous strobe would cause a write-mark
to merge two back-to-back writes.

42 DDR Analysis
Operating Basics Chip Select, Latency + DQ/DQS Phase Alignment

Chip Select, Latency + DQ/DQS Phase Alignment

1. If you wish to filter the data bursts based on a CS Source signal, select the CS Source (see page 43)
using the CS Source drop-down. Select CS Active (see page 43) and CS Mode (see page 44) as shown
in the following figure. CS source is available only for Read and Write bursts measurements.

NOTE. If a CS source is selected, CS-DQS(Strobe) is used for signal separation otherwise

DQS(Strobe)-DQ(Data) is used. You must configure DQ source to enable Search and Mark.

CS Source
CS Source is used as a logic input to select read or write bursts corresponding to the chip select
signal. When a chip-select signal source other than none is specified, reads or writes will only be
shown when the chip-select source is active.

CS Active
Selects whether the chip-select source logic is considered active high or active low.

DDR Analysis 43
Operating Basics Logic State + Burst Latency

CS Mode
CS Mode consists of two modes – Auto and Manual. CS Auto mode calculates the level automatically
for you (as half the peak-to-peak voltage), while manual mode allows you to specify a CS level. In
cases where an entire acquisition could occur with no transitions on the chip-select line, you must
select the manual mode to set the correct logic level.

Logic State + Burst Latency

This burst detection method is available only on MSO series of oscilloscopes. You can configure the logic
state, burst latency, tolerance, burst length, and DQ/DQS levels.

The DDRA application provides a shortcut, Bus Setup, to configure the bus in the oscilloscope bus setup
window. Click Bus Setup in Step 5 to view the Bus setup screen as shown

NOTE. For more details, refer to “Bus Setup Control Window (Select Tab)” section in your oscilloscope
online help.

DDRA application lists the buses defined in the bus setup menu. For DDRA to use the logic bus for
read/write burst detection, it must have an associated symbol file (see page 46).

44 DDR Analysis
Operating Basics Logic State + Burst Latency

By default, the DDRA application displays the symbol file that corresponds to the selected DDR generation
in Step 1 (see page 31). Click Browse to select a symbol file of your choice. On selecting the symbol
file, the Logic trigger lists the available patterns as shown. The symbol files per generation are located at
C:\TekScope\busDecodeTables\DDR.

NOTE. For 64-bit systems, the DDRA installer copies the symbol files into the following location:
C:\Users\Public\Tektronix\TekScope\BusDecodeTables\DDR. This is different from the default TekScope
location at C:\Users\[Username]\Tektronix\Tekscope\BusDecodeTables.

Edit/customize the symbols based on your requirements and save it in *.tsf format. Place the created
symbol files for access at C:\TekScope\busDecodeTables\DDR. Use Bus setup config menu or browse
(Step 5) to access the created symbol file. A sample file for DDR3 is as shown:

Symbol Pattern
MOD_REG 0000
REFRESH 0001
PRECHARGE 0010
ACTIVATE 0011
WRITE 0100
READ 0101
NOP 0111
DESELECT 1XXX
xxx

The DDRA application displays a hint “There may be a possible mismatch in the selected logic trigger and
the measurement type. Please verify before continuing” when you select a logic state of READ and the
measurement type selected is WRITE or vice versa.

NOTE. Any change in the symbol file in the DDRA application, is reflected in the oscilloscope bus
configuration menu. The symbols of interest for DDRA are READ and WRITE patterns.

DDR Analysis 45
Operating Basics Logic State + Burst Latency

Symbol File
Symbol files are files of alphanumeric symbol names and associated data values, and are used to map
a group value to a text string. The oscilloscope displays the symbol in place of the numeric value. For
more details on symbol file format, refer to your oscilloscope online help .

Specify the Burst Latency, Tolerance (see page 46), and burst length (see page 47) values.

CAS Min and Max

For READ commands, Read Latency (RL) is defined as the delay, in clock cycles, between the rising
CLK edge that latches the READ command and the rising DQS edge signifying availability of the first
data bit. The Read Latency is equal to the additive Latency and the CAS Latency (RL = AL + CL).
CAS Min specifies the minimum time delay between the start of READ bus state and the initial rising
DQS edge, for the first bit to be recognized. CAS Max specifies the maximum time delay between the
end of the READ bus state and the initial rising DQS edge, for the first bit to be recognized. In the
following figure, the actual READ latency is 2 and the CAS Min and CAS Max are set to 2. The
green zone indicates where the initial rising DQS edge must be for burst recognition to occur.
For WRITE commands, Write Latency (WL) is defined as the delay, in clock cycles, between the
rising CLK edge that latches the WRITE command and the rising DQS edge in the center of the first
data bit. The Write Latency is equal to the Additive Latency and the CAS Write Latency (WL = AL +
CWL). As with the READ case, the CAS Max and CAS Min parameters define a window following
the WRITE bus state where the initial rising DQS edge must be for burst recognition to occur.

46 DDR Analysis
Operating Basics Visual Search

Burst Length
READ and WRITE operations are burst oriented, they start at a selected location, and continue for a
burst length. Burst length, specified in cycles, determines where a read/write mark ends after the start
of a read/write mark has been identified. Any change in DDR generation resets the burst length to 8.0.

Reference
Salient Features of MSO-DDR Integration (see page 60)
Using Digital Channels (see page 118)

Visual Search
Capturing and analyzing the right part of the waveform can require hours of collecting and sorting through
the many acquisitions. The Visual Trigger feature in the oscilloscope makes the identification of the
desired waveform events quick and easy by scanning through acquired analog waveforms and graphically
comparing them to geometric shapes on the display. By discarding acquired waveforms which do not
meet the graphical definition, Visual Triggering extends the trigger capabilities of the oscilloscope beyond
the traditional hardware trigger system.
In DDR, Visual Trigger can be used to separate Read bursts from Write Bursts and mark them. By
selecting the Visual Search option in Step4: Burst Detection Method, these marked bursts can be used for
further debugging and analysis.

Marking Read/Write bursts using visual trigger

Visual Trigger can also be used to mark all bursts which have a specific property (for example, marking a
Read burst that has a spike just before it comes out of tri-state or marking a Write burst with a known data
pattern). The figure below shows Visual Trigger that was used to mark (green marks) Write bursts with
a known data pattern.
Along with the Visual search mark, Advanced search and mark (another feature in Tektronix oscilloscopes)
has also been used to mark all the Write bursts (pink marks). Visual trigger has been used to isolate a burst
with a specific data pattern, which allows the marked burst to be used for further debugging and analysis.

DDR Analysis 47
Operating Basics Visual Search

Isolating Read and Write bursts on the DDR3 bus using Visual trigger
DDR3 SDRAM is a high speed, dynamic random access memory internally configured as an eight bank
DRAM. It can Read (fetch) and Write data as a burst operation. The burst length can be 4 clock cycles,
8 clock cycles, and can go up to 32 clock cycles so that it can fetch the data byte 1 to 8 bytes in a burst.
DDR3 defines the polarity of the Preamble different for Read and Write. For a Read burst, the Preamble
would be negative polarity. For a Write burst, the Preamble would be positive polarity. For DDR3, the
Read and Write Preamble widths are defined by parameters tRPRE and tWPRE in the JEDEC specification,
and whose minimum value has been defined as 0.9 times that of the clock period.
Additionally, the phase between the Strobe signal (DQS) and Data Signals (DQ) are different for Read and
Write. DQS and DQ are aligned for Read bursts and shifted by 90 degrees for Write bursts.

48 DDR Analysis
Operating Basics Visual Search

Isolating based on Preamble polarity and phase between DQS and DQ using Visual trigger
Figure 1 shows a screen capture of using Visual Trigger to isolate Read signals based on Preamble polarity
and phase difference between the DQS and DQ signals. Channel 1 of the oscillocope is DQS and Channel
2 is DQ. Areas A1 and A2 are set so that when a signal is captured, there is no DQS signal in these regions.
This ensures that the captured signal is coming out of tri-state. Area A3 is set to select the negative
polarity of the Preamble. Areas A4 and A5 are set so that the DQ signal does not enter these regions,
making sure that the DQS and DQ are aligned.

Read burst

DDR Analysis 49
Operating Basics Visual Search

Write burst

50 DDR Analysis
Operating Basics Step6: Thresholds and Scaling

Step6: Thresholds and Scaling

The left half of this panel controls selection of critical voltage thresholds used by the measurement
algorithms. The right half determines whether scaling is automatically adjusted each time you sequence.

Measurement Thresholds
Select either Auto or Manual as the Measurement Threshold type.
If you select Auto, the application calculates these levels for you based on the DDR generation and
speed grade. It is recommended that you use this option.
If you select Manual, set the measurements levels by clicking the Setup button.
For more details, refer to the topic “Ref Levels” of the DPOJET help.

NOTE. For every measurement selected in DDRA, appropriate reference levels are set in the DPOJET
application. You can change these levels, if needed, from the DPOJET application.

DDR Analysis 51
Operating Basics Step6: Thresholds and Scaling

Vertical Scaling
Selecting Auto performs autoset on the oscilloscope vertical settings only.
For more details, refer to the topic “Source Autoset” of the DPOJET help.

Horizontal Scaling
Selecting Auto performs autoset on the oscilloscope horizontal settings only.
For more details, refer to the topic “Source Autoset” of the DPOJET help.

NOTE. If both Vertical and Horizontal are checked, the application performs autoset on both vertical and
horizontal oscilloscope settings when Single/Run is selected.

Alternate Thresholds
Alternate Thresholds only apply to the DDR3 Address and Command measurement type. It allows you
to select derating values(Δ) from the derating tables– AC 175 (see page 53) and AC 150. The default
is AC 175.

52 DDR Analysis
Operating Basics Step6: Thresholds and Scaling

AC 175 . The AC 175 Threshold derating table is as follows:

Table 8: Derating Values for DDR3 800/1066/1333/1600 MT/s tIS/tIH
ΔtIS, ΔtIH derating in ps AC/DC based
AC 175 Threshold(VIH(ac))= VREF(dc)+175 mV, VIL(ac)=VREF(dc)–175 mV
CK , CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ- Δ-
t- t- t- t- t- t- t- t- t- t- t- t- t- t- t- t-
I- I- I- I- I- I- I- I- I- I- I- I- I- I- I- I-
S H S H S H S H S H S H S H S H
CMD/ 2 8 5 8 5 8 5 9 5 1 6 1 7 1 8 1 1
ADDR . 8 0 8 0 8 0 6 8 0 6 1 4 2 4 2 0
Slew 0 4 2 0 8 0
rate 1 5 3 5 3 5 3 6 4 7 5 8 5 9 6 9 8
(v/ns) . 9 4 9 4 9 4 7 2 5 0 3 8 1 8 9 4
5
1 0 0 0 0 0 0 8 8 1 1 2 2 3 3 4 5
. 6 6 4 4 2 4 0 0
0
0 – – – – – – 6 4 1 1 2 2 3 3 3 4
. 2 4 2 4 2 4 4 2 2 0 0 0 8 6
9
0 – – – – – – 2 – 1 6 1 1 2 2 3 4
. 6 1 6 1 6 1 2 0 8 4 6 4 4 0
8 0 0 0
0 – – – – – – – – 5 0 1 8 2 1 2 3
. 1 1 1 1 1 1 3 8 3 1 8 9 4
7 1 6 1 6 1 6
0 – – – – – – – – – – 7 – 1 8 2 2
. 1 2 1 2 1 2 9 1 1 1 2 5 3 4
6 7 6 7 6 7 6 8 0
0 – – – – – – – – – – – – – – 5 1
. 3 4 3 4 3 4 2 3 1 2 1 1 2 6 0
5 5 0 5 0 5 0 7 2 9 4 1 6
0 – – – – – – – – – – – – – – – –
. 6 6 6 6 6 6 5 5 4 4 3 3 3 2 2 1
4 2 0 2 0 2 0 4 2 6 4 8 6 0 6 2 0
xxx

DDR Analysis 53
Operating Basics Step6: Thresholds and Scaling

AC 150 .

The AC 150 Threshold derating table is as follows:

Table 9: Derating Values for DDR3 800/1066/1333/1600 MT/s tIS/tIH
ΔtIS, ΔtIH derating in ps AC/DC based
AC 150 Threshold(VIH(ac))= VREF(dc)+150 mV, VIL(ac)=VREF(dc)–150 mV
CK , CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ- Δ- Δ- Δ- Δ- Δ-
Δ- t- Δ- Δ- t- Δ- Δ- t- Δ- t- Δ- Δ- t- Δ- t- Δ-
tI- I- tI- tI- I- tI- tI- I- tI- I- tI- tI- I- tI- I- tI-
S H S H S H S H S H S H S H S H
CM- 2 7 5 7 5 7 5 8 5 9 6 9 7 1 8 1 1
D/A- . 5 0 5 0 5 0 3 8 1 6 9 4 0 4 1 0
DD- 0 7 5 0
R S- 1 5 3 5 3 5 3 5 4 6 5 7 5 8 6 9 8
lew . 0 4 0 4 0 4 8 2 6 0 4 8 2 8 0 4
rate 5
(v/
ns) 1 0 0 0 0 0 0 8 8 1 1 2 2 3 3 4 5
. 6 6 4 4 2 4 0 0
0
0 0 – 0 – 0 – 8 4 1 1 2 2 3 3 4 4
. 4 4 4 6 2 4 0 2 0 0 6
9
0 0 – 0 – 0 – 8 – 1 6 2 1 3 2 4 4
. 1 1 1 2 6 4 4 2 4 0 0
8 0 0 0
0 0 – 0 – 0 – 8 – 1 0 2 8 3 1 4 3
. 1 1 1 8 6 4 2 8 0 4
7 6 6 6
0 – – – – – – 7 – 1 – 2 – 3 8 3 2
. 1 2 1 2 1 2 1 5 1 3 2 1 9 4
6 6 6 6 8 0
0 – – – – – – – – 6 – 1 – 2 – 3 1
. 1 4 1 4 1 4 2 3 2 4 1 2 6 0 0
5 0 0 0 0 0 0 2 4 6
0 – – – – – – – – – – – – 7 – 1 –
. 2 6 2 6 2 6 1 5 9 4 1 3 2 5 1
4 5 0 5 0 5 0 7 2 4 6 6 0
xxx

For DDR3 1866 and 2133 speeds, AC175 or AC150 default to AC135 settings.

Reference
Hints (see page 56)

54 DDR Analysis
Operating Basics Measurement Levels

Measurement Levels
By definition, edges occur when a waveform crosses specified reference voltage levels. Reference voltage
levels must be set so that the application can identify state transitions on a waveform. By default, the
application automatically chooses reference voltage levels when necessary.

The DDRA application uses three basic reference levels: High, Mid and Low. In addition, a hysteresis
value defines a voltage band that prevents a noisy waveform from producing spurious edges. The reference
levels and hysteresis are independently set for each source waveform, and are specified separately for
rising versus falling transitions.
Item Description
Measurement Reference Levels Setup (one level per source)
Rise High Sets the high threshold level for the rising edge of the source.
Rise Mid Sets the middle threshold level for the rising edge of the source.
Rise Low Sets the low threshold level for the rising edge of the source.
Fall High Sets the high threshold level for the falling edge of the source.
Fall Mid Sets the middle threshold level for the falling edge of the source.
Fall Low Sets the low threshold level for the falling edge of the source.
Hysteresis Sets the threshold margin to the reference level which the voltage must cross to
be recognized as changing; the margin is the relative reference level plus or
minus half the hysteresis; use to filter out spurious events.
xxx

DDR Analysis 55
Operating Basics Hints

Hints
The DDRA application displays the following hints at different steps:

Hint Step Description

Select a standard data rate in DDRA 1 Displayed when data rate is None. When you select a
non standard data rate in ASM, the data rate is set to
None in DDRA.
GDDR3 not completely supported. 1 Displayed on selecting GDDR3 standard, which does
Some features may not function. not have standard data rates. Only Data Eye Width
measurement is available for both Read and Write bursts.
Please provide a Limits file under 1 Displayed for custom data rates for which limits are not
Jitter and Eye > Limits defined. You need to manually configure the limits.
Cannot use Live and Ref waveforms 3 Displayed on selecting both Live and Ref waveforms
together. as source for DQ and DQS. Example: Data Eye Width
measurement with sources as Ch1 for DQ and Ref1 for
DQS.
Cannot use the same waveform for 3 Displayed on selecting the same source for DQ and DQS.
different sources. Example: Data Eye Width using Ch3 for both DQ and
DQS.
Cannot select Diff and SE 3 Displayed on selecting measurements with suffix SE and
measurements at the same time. Diff. Example: DDR2, Write bursts, tDH-Diff and tDH-SE
measurements.
Use unique sources that are either 3 Displayed on selecting measurements which require DQ,
Live or Ref. DQS and Clock sources. Example: DDR3, 800MT/s,
select all Read burst measurements.
xxx

56 DDR Analysis
Operating Basics Results as Statistics

Results as Statistics
Result statistics for most of the measurements show Population in terms of UI or transitions. According to
the JEDEC specification, the analysis for most of the clock measurements is done for a 200-cycle moving
window. However, for clock measurements such as tCL(avg) and tCH(avg), the population is shown as
tCK(avg) units. For some measurements such as Data Eye Width, exactly one measurement occurs per
acquisition. For such measurements, the population increases by one for each acquisition independent
of the number of UI in the acquisition.

For more details, refer to the topic “Viewing Statistical Results” of the DPOJET help.

Reference
Dynamic Limits (see page 18)

DDR Analysis 57
Operating Basics Plots

Plots
The only measurement for which a plot is automatically configured is Data Eye Width, which is available
for both Read and Write bursts. However, plots may be added for other measurements through the plot
panel. The plot selection and configuration methods are identical to those used for DPOJET. For more
details, refer to the DPOJET help.

For acquisitions containing more than one read or write burst, time trend plots connect together all
measurements within each burst with a continuous line, but do not draw lines between bursts. If a vertical
cursor is placed where it does not intersect a line, the cursor annotation will read "NaN" (Not a Number).

For more details, refer to the topic “About Configuring Plots” of the DPOJET help.

Reports

For more details, refer to the topic “About Reports” of the DPOJET help.

58 DDR Analysis
Operating Basics Switching between the DDRA and DPOJET Applications

Switching between the DDRA and DPOJET Applications

For advanced analysis, click to switch to the DPOJET application. Likewise, click

in the DPOJET application to revert to the DDRA application.

The transition behaves as follows:
The application name in the title bar switches between DDR Analysis and Jitter and Eye Diagram
Analysis Tool.
Measurement name remains unchanged while traversing from DDRA to DPOJET.
Within DPOJET, more measurements may be added to those automatically configured in DDRA.
These measurements must be configured manually.
Once in DPOJET, measurements automatically configured by DDRA may be reconfigured. (The
measurements will generally no longer be JEDEC-compliant in this case.)
Upon returning to DDRA, new or non-standard measurements will be retained.
Measurement sequencing, results analysis and report generation can be done from either application.
Any change in generation and measurement type in the DDRA deselects all the currently selected
measurements.
Switching back from DPOJET to DDRA, always resets focus to the Setup panel.
DPOJET or DDRA application is always accessible from the oscilloscope menu bar, as an alternative
to the quick navigation buttons.
If DPOJET application is opened from the oscilloscope menu (Analyze > Jitter and Eye Diagram
Analysis), the shortcut button to DDR Analysis is not shown. This shortcut only appears if DPOJET
is entered from the DDRA interface.
Any change in the reference voltage levels in DPOJET is reflected in DDRA Step 1, Vih and Vil (see
page 115). Vih and Vil specify the static voltage reference levels of the measurements. You can modify
these levels either in Step 6 (see page 51) of DDRA or in the DPOJET source configuration screen.

DDR Analysis 59
Operating Basics Salient Features of MSO-DDRA Integration

Salient Features of MSO-DDRA Integration

The following are the salient features of MSO-DDR integration:
Use the DDRA user interface for the required settings without exiting from the DDRA setup panel for
digital configuration.
Logic State burst detection method is more reliable than the conventional DQ/DQS Phase alignment.
Digital configurations are available at Step 4 and Step 5 of the DDRA application. The Logic pattern
or Logic state triggering is used on the digital control signals such as RAS, CAS, CS and WE, which
identify the desired burst type.
Symbol files per DDR generation are available.
Identify marks using the specified digital control signals and Burst Latency and Tolerance values. The
Burst Latency and Tolerance values are important to precisely mark the bursts.
Change in DDR generation resets the burst length to 8.0.

60 DDR Analysis
Tutorial Introduction to the Tutorial

Introduction to the Tutorial

This tutorial teaches how to set up the application, take measurements, and view results as plots or statistics.
Before you begin the tutorial, perform the following tasks:
Set up the oscilloscope.
Start the application.
Recall the tutorial waveform.

Setting Up the Oscilloscope

The steps to set up the oscilloscope are:
Click File > Recall Default Setup in the oscilloscope menu bar to recall the default settings.
Press the individual CH1, CH2, CH3, and CH4 buttons as needed to add or remove active waveforms
from the display.

Starting the Application

Click Analyze > DDR Analysis to open the application.

Waveform Files
The DDRA application provides the following waveforms at C:\TekApplications\DDRA\Waveforms
for oscilloscopes running the Windows-XP operating system and C:\Users\Public\Tek-
tronix\TekApplications\DDRA\Waveforms for oscilloscopes running the Windows7 operating
system:
DDR2_800_DQS_Write.wfm
DDR2_800_DQ_Write.wfm
DDR2_800_CLK.wfm

NOTE. These waveforms have to be used only for Write bursts and CLK.

DDR Analysis 61
Tutorial Recalling a Waveform File

Recalling a Waveform File

To recall a waveform file, follow these steps:
1. Click File > Recall in the oscilloscope menu bar to display the Recall dialog box.
2. Click Waveform icon in the left of the Recall dialog box.
3. Select Ref1, Ref2, Ref3, or Ref4 as the Destination option.
4. Browse to select the waveform. Use the keypad to edit the waveform file name.
5. Click Recall. The oscilloscope recalls and activates the Reference Waveform control window.
6. Click On to display the waveform.

7. Click to return to the application. Alternatively, DDRA can also be accessed from Analyze >
DDR Analysis.

Taking a Measurement
This tutorial uses the following example
DDR2 800MT/s, Write bursts - Differential measurements
Waveforms Used: DDR2_800_DQS_Write.wfm and DDR2_800_DQ_Write.wfm
1. To set the application to default values, click File > Recall Default Setup. This is not necessary if
you have just started the application.
2. To view the DDRA application, select Analyze > DDR Analysis.
3. At Step 1, select the DDR2 standard and the data rate as 800 MT/s. The default voltage settings
are retained as shown:

62 DDR Analysis
Tutorial Taking a Measurement

4. At Step 2, select the filter and the probing type.

5. At Step 3, select the measurements and the associated sources.

6. At Step 4, select the burst detection method.

The selected data rate, generation, and measurement type are reflected in ASM on selection in
DDRA. Marks are available only for Read and Write bursts measurement type. Configure Search
using Advance > Search > Configure. The identified bursts are shown as small inverted marks
( ) in the oscilloscope display area. Each pair of marks specifies the start and stop of a burst. You
can traverse from one mark to the other using the Mark Control window. For more details, refer to
your oscilloscope online help.

DDR Analysis 63
Tutorial Taking a Measurement

NOTE. Logic state+ DQ/DQS Phase Alignment is available only for MSO series of oscilloscopes.

7. At Step 5, select the burst detection settings based on the selected burst detection method as shown:

64 DDR Analysis
Tutorial Taking a Measurement

8. At Step 6, retain the settings as shown:

9. Click Single to run the application. When complete, the result statistics with limits are shown in the
results tab.

The eye diagram plot is displayed as shown:

DDR Analysis 65
Tutorial Taking a Measurement

66 DDR Analysis
Parameters About Parameters

About Parameters
This section describes the DDRA application parameters and includes the menu default settings. Refer to
the user manual of your oscilloscope for operating details of other controls, such as front-panel buttons.
The parameter tables list the selections or range of values available for each option, the incremental unit of
numeric values, and the default selection or value.

DDR Analysis 67
Parameters Step1: Generation, Rate and Levels Parameters

Step1: Generation, Rate and Levels Parameters

Step1 includes the following parameters:

Table 10: Generation, rate and levels parameters

Option Parameters Default setting
DDR Generation DDR, DDR2, DDR3, DDR3L, DDR4, DDR3
LPDDR, LPDDR2, LPDDR3, GDDR3,
and GDDR5
Data Rate † DDR: 200 MT/s, 266 MT/s, 333 MT/s, 200 MT/s for DDR
400 MT/s, Custom and None
DDR2: 400 MT/s, 533 MT/s, 400 MT/s for DDR2
667 MT/s, 800 MT/s, 1066 MT/s,
Custom and None
DDR3: 800 MT/s, 1066 MT/s, None for DDR3
1333 MT/s, 1866 MT/s, 2133 MT/s,
Custom and None
DDR3L: 800 MT/s, 1066 MT/s, 800 MT/s for DDR3L
1333 MT/s, 1600 MT/s, Custom and
None
DDR4: 1600 MT/s, 1866 MT/s, 1600 MT/s for DDR4
2133 MT/s, 2400 MT/s, 2466 MT/s,
3200 MT/s, Custom and None
LPDDR: 200 MT/s, 266 MT/s, Custom 200 MT/s for LPDDR
and None
LPDDR2:333 MT/s, 400 MT/s, 533 333 MT/s for LPDDR2
MT/s, 667 MT/s, 933 MT/s, 1066
MT/s, Custom and None
LPDDR3:333 MT/s, 800 MT/s, 1066 333 MT/s for LPDDR3
MT/s, 1200 MT/s, 1333 MT/s, 1466
MT/s, 1600 MT/s, Custom and None
GDDR3: 500 MT/s, 600 MT/s, 500 MT/s for GDDR3
700 MT/s, 800 MT/s, 900 MT/s,
1000 MT/s, Custom and None
GDDR5: 4000 MT/s, 4800 MT/s, 4000 MT/s for GDDR5
5000 MT/s, 5500 MT/s, Custom, and
None
Custom 800 MT/s
Vdd JEDEC Default, User Defined JEDEC Default
Vref JEDEC Default, User Defined JEDEC Default
DDR4Vref JEDEC Default, User Defined User Defined
xxx

† Data rate varies for different DDR standards.

68 DDR Analysis
Parameters Step2: Interposer Filter Parameters

Step2: Interposer Filter Parameters

Step2 includes the following parameters under Filter Type:
None
User Defined
Direct Attached
Socketed
Step2 includes the following parameters under Probing Type for CLK, WCK, and DQS signal types:
Single Ended
Differential

DDR Analysis 69
Parameters Step3: Measurement and Sources Parameters

Step3: Measurement and Sources Parameters

Step3 includes the following parameters under Measurement Type:
Read Bursts
Write Bursts
WCK(Single Ended) †
WCK(Diff) †
Clock(Diff)
Clock(Single Ended)
Address/Command
Refresh †
Power Down †
Active †
Precharge †
DQS(Single Ended)
DQS(Single Ended, Read)
The sources parameters are as shown in the following table:

Table 11: Sources parameters

Option Parameters Default setting
DQS(Strobe) Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch1
DQS#(Strobe) Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch3
DQ(Data) Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch2
Addr/Cmd Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch4
Clock Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch3
Clock# Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch4
WCK † Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch1
WCK# † Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch4
WE, CS, CAS, RAS, CKE † D0-D15 None
xxx

† These measurement types and parameters are available for GDDR5 generation.

70 DDR Analysis
Parameters Step4: Burst Detection Method Parameters

Step4: Burst Detection Method Parameters

Step4 has the following parameters:
DQ/DQS Phase Alignment (see page 41)
Chip Select, Latency + DQ/DQS Phase Alignment (see page 43)
Logic State + Burst Latency (see page 44)
Visual Search (see page 47)

Step5: Burst Detection Settings Parameters

Step5 has the following parameters:

NOTE. The DQ/DQS Phase Alignment settings are same for Chip Select and Logic State Burst Detection
methods.

Table 12: Burst detection parameters

Option Parameters Default setting
Chip Select, Latency + DQ/DQS Phase Alignment
CS Source None, Ch1-Ch4, Ref1-Ref4, None
Math1-Math4
CS Mode † Auto, Manual Auto
CAS Min(ui) † 0–1k 2.0
CS Active † High, Low Low
CS Level † Left, Right 0.0 V
CAS Max(ui) † 0–1k 3.0
DQ/DQS Levels ‡ Auto, Manual Auto

DDR Analysis 71
Parameters Step5: Burst Detection Settings Parameters

Table 12: Burst detection parameters (cont.)

Option Parameters Default setting
DQ/DQS Phase Alignment
Strobe
High Auto, Manual Auto
Mid Auto, Manual Auto
Low Auto, Manual Auto
Data
High Auto, Manual Auto
Mid Auto, Manual Auto
Low Auto, Manual Auto
Edge Detection Hysteresis Auto, Manual Auto
Termination Logic Margin Auto, Manual Auto
LogicState + Burst Latency DQ/DQS Phase Alignment *
Bus B1–B16 None
Tolerance ‡ 0–50 G 1Cyc
Burst Latency ‡ 0–50 G 2.5Cyc
Burst Length 0–50 G(ui) 0.0
DQ/DQS Levels ‡ Auto, Manual Auto
Logic Trigger ‡ MODE_REG, REFRESH, MODE_REG
PRECHARGE, ACTIVATE, WRITE,
READ, SRX, DESELECT, SRE, PDE
xxx

† Available only when you select CS source.

* Available only for the MSO series of oscilloscopes.
‡ These measurement types and parameters are available for GDDR5 generation.

72 DDR Analysis
Parameters Step6: Thresholds and Scaling Parameters

Step6: Thresholds and Scaling Parameters

Step6 has the following parameters:

Table 13: Thresholds and scaling parameters

Option Parameters Default setting
Measurement Thresholds Auto, Manual Auto
Vertical Scaling Set, Clear Clear
Horizontal Scaling Set, Clear Clear
Alternate Thresholds * AC 175, AC 150 AC175
Measurement Levels
Rise High –20 V to 20 V 1V
Rise Mid –20 V to 20 V 0V
Rise Low –20 V to 20 V –1 V
Fall High –20 V to 20 V 1V
Fall Mid –20 V to 20 V 0V
Fall Low –20 V to 20 V –1 V
Hysteresis 0 to 10 V 30 mV
xxx

* Available only for Address and Command Measurement type.

DDR Analysis 73
Parameters Step6: Thresholds and Scaling Parameters

74 DDR Analysis
References LPDDR Measurement Sources

LPDDR Measurement Sources

The sources required for analysis may include DQS (Strobe), DQS# (Strobe), DQ (Data) , Clock, Clock #,
and Addr/Cmd. DQ and DQS can be either Single-Ended (SE) or Differential (Diff). Read and Write
bursts have CS as an optional source.

The following table lists the sources required for each LPDDR measurement:
Table 14: LPDDR measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
tDQSS Bus (B1) and DQS DQ
Differential DQS
tDH-Diff(base) DDR Hold–Diff DQS and DQ None
tDQSH Pos Width DQS and DQ None
tDQSL Neg Width DQS and DQ None
tDS-Diff(base) DDR Setup–Diff DQS and DQ None
tDSH-Diff Hold DQS and Clock DQ †
tDSS-Diff Setup DQS and Clock DQ †
Single Ended DQS
tDH-SE DDR Hold-SE DQ and DQS None
tDIPW-SE Period DQ DQS †
tDSH-SE Hold DQS and Clock DQ †
tDSS-SE Setup DQS and Clock DQ †
tDS-SE DDR Setup–SE DQS and DQ None
tWPRE DDR tRPRE DQS DQ †
tWPST DDR tPST DQS DQ †
Read Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
Differential DQS
tAC-Diff DDR Setup-Diff DQ and Clock DQS †
tDQSCK-Diff Skew DQS and Clock DQ †
tQH Hold DQS and DQ None
Single Ended DQS
tDQSQ-SE Setup DQS and DQ None
tRPRE DDR tRPRE DQS DQ †

DDR Analysis 75
References LPDDR Measurement Sources

Table 14: LPDDR measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tRPST DDR tRPST DQS DQ †
Clock (Diff)
tCH Pos Width Clock None
tCK Period Clock None
tCL Neg Width Clock None
tHP Period Clock None
VID(ac) DDR VID(ac) Clock None
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# None
AC-Overshoot(CK) Overshoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock# None
AC-OvershootAreat(CK) DDR Over Area Clock None
AC-Undershoot(CK#) Undershoot Clock# None
AC-Undershoot(CK) Undershoot Clock None
AC-UndershootArea(CK#) DDR Under Area Clock# None
AC-Undershoot Area(CK) DDR Under Area Clock None
Vix(ac)CK V-Diff-Xovr Clock and Clock# None
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS) Overshoot DQS DQ †
AC-OvershootArea(DQS) DDR Over Area DQS DQ †
AC-Undershoot(DQS) Undershoot DQS DQ †
AC-UndershootArea(DQS) DDR Under Area DQS DQ †
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
Address/Command
AC-Overshoot Overshoot Addr/Cmd None

76 DDR Analysis
References LPDDR2 Measurement Sources

Table 14: LPDDR measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-Overshoot DDR Over Area Addr/Cmd None
AC-Undershoot Undershoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
tIH(base) DDR Hold–Diff Clock and Addr/Cmd None
tIPW-High High Time Clock and Addr/Cmd None
tIPW-Low Low Time Clock and Addr/Cmd None
tIS(base) DDR Setup–Diff Clock and Addr/Cmd None
xxx

† Required so that the Search-and-Mark feature can properly identify bursts

LPDDR2 Measurement Sources

The sources required for analysis may include DQS (Strobe), DQS# (Strobe), DQ (Data), Clock, Clock #,
and Addr/Cmd. DQS and Clock can be either Single-Ended (SE) or Differential (Diff). Read and Write
bursts have CS as an optional source.

The following table lists the sources required for each LPDDR2 measurement:
Table 15: LPDDR2 measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
tDQSS DQS and Bus (B1) DQ
Single Ended DQS
tDIPW-SE Period DQ DQS
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS and DQ None
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQ and DQS None
tDH-Diff(base) DDR Hold-Diff DQ DQS ‡
tDH-Diff(derated) DDR Hold-Diff DQS and DQ None
tDH-Diff(Vref-based) Hold DQS and DQ None
tDQSH Positive Width DQS DQ ‡
tDQSL Negative Width DQS DQ ‡
tDS-Diff(base) DDR Setup-Diff DQS and DQ None
tDS-Diff(derated) DDR Setup-Diff DQS and Clock DQ ‡
tDS-Diff(Vref-based) Setup DQS DQ ‡

DDR Analysis 77
References LPDDR2 Measurement Sources

Table 15: LPDDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tDSH-Diff Hold DQS and Clock DQ ‡
tDSS-Diff Setup DQS and Clock DQ ‡
tDVAC(DQS) Time Outside Level DQS DQ
Slew Rate DQ
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS ‡
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS ‡
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS ‡
Slew Rate-Setup- Rise Slew Rate DQ DQS ‡
Rise(DQ)
tWPRE DDR tRPRE DQS DQ ‡
tWPST DDRtPST DQS DQ ‡
Read Bursts
Differential DQS
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ ‡
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDQSQ-Diff Setup DQS and DQ None
tDVAC(DQS) Time Outside Level DQS DQ
tQH Hold DQS and DQ None
Slew Rate DQ
SRQse-Fall(DQ) Fall Slew Rate DQ DQS ‡
SRQse-Rise(DQ) Rise Slew Rate DQ DQS ‡
tRPRE DDR tRPRE DQS DQ ‡
tRPST DDR tPST DQS DQ ‡
Clock (Diff)
tCH(abs) Pos Width Clock None
tCH(avg) DDR tCH(avg) Clock None
tCK(abs) Period Clock None
tCK(avg) DDR tCK(avg) Clock None
tCL(abs) Neg Width Clock None
tCL(avg) DDR tCL(avg) Clock None
tDVAC(CK) Time Outside Level CK None
tERR DDR tERR Clock None
tJIT(cc) CC–Period Clock None
tJIT(duty) DDR tJIT(duty) Clock None
tJIT(per) DDR tJIT(per) Clock None
tHP Period Clock None
Clock (Single Ended)

78 DDR Analysis
References LPDDR2 Measurement Sources

Table 15: LPDDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-OverShoot(CK#) OverShoot Clock# None
AC-OverShoot(CK) OverShoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock# None
AC-OvershootArea(CK) DDR Over Area Clock None
AC-UnderShoot(CK#) UnderShoot Clock# None
AC-UnderShoot(CK) UnderShoot Clock None
AC-UndershootArea(CK#) DDR Under Area Clock# None
AC-UndershootArea(CK) DDR Under Area Clock None
VIXCA DDR3 Vix(ac) CK, CK# None
VSEH(AC)CK Cycle Max Clock None
VSEH(AC)CK# Cycle Max Clock# None
VSEL(AC)CK Cycle Min Clock None
VSEL(AC)CK# Cycle Min Clock# None
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-OverShoot(DQ) OverShoot DQ DQS
AC-UnderShoot(DQ) UnderShoot DQ DQS
AC-OverShoot(DQS#) OverShoot DQS# DQ, DQS
AC-OverShoot(DQS) OverShoot DQS DQ ‡
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ ‡
AC-UnderShoot(DQS#) UnderShoot DQS# DQ, DQS
AC-UnderShoot(DQS) UnderShoot DQS DQ ‡
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-UndershootArea(DQS) DDR Under Area DQS DQ ‡
VIXDQ DDR3 Vix(ac) DQS, DQS# DQ
VSEH(AC)DQS Cycle Max DQS DQ ‡
VSEH(AC)DQS# Cycle Max DQS# DQ ‡
VSEL(AC)DQS Cycle Min DQS DQ ‡
VSEL(AC)DQS# Cycle Min DQS# DQ ‡
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS

DDR Analysis 79
References LPDDR2 Measurement Sources

Table 15: LPDDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
Precharge
tRTP tCMD-CMD Bus, CK None
tRP tCMD-CMD Bus, CK None
Active
tRAS tCMD-CMD Bus, CK None
tRC tCMD-CMD Bus, CK None
tRCDRD tCMD-CMD Bus, CK None
tRCDWR tCMD-CMD Bus, CK None
Address/Command
AC-OverShoot OverShoot Addr/Cmd None
AC-OvershootArea DDR Over Area Addr/Cmd None
AC-UnderShoot UnderShoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
InputSlew-Diff-Fall(CK) Fall Slew Rate Clock None
InputSlew-Diff-Rise(CK) Rise Slew Rate Clock None
Slew Rate-Hold- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Hold- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
Slew Rate-Setup- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Setup- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
tIH(base) DDR Hold-Diff Clock and Addr/Cmd None
tIH(derated) DDR Hold-Diff Clock and Addr/Cmd None
tIPW-High High Time Clock and Addr/Cmd None
tIPW-Low Low Time Clock and Addr/Cmd None

80 DDR Analysis
References LPDDR2 Measurement Sources

Table 15: LPDDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tIS(base) DDR Setup-Diff Clock and Addr/Cmd None
tIS(derated) DDR Setup-Diff Clock and Addr/Cmd None
xxx

‡ Required so that the Search-and-Mark feature can properly identify bursts

DDR Analysis 81
References LPDDR3 Measurement Sources

LPDDR3 Measurement Sources

The sources required for analysis may include DQS (Strobe), DQS# (Strobe), DQ (Data) , Clock, Clock
#, and Addr/Cmd. DQ and DQS can be either Single-Ended (SE) or Differential (Diff). Read and Write
bursts have CS as an optional source.

The following table lists the sources required for each LPDDR3 measurement:
Table 16: LPDDR3 measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
tDQSS DDR tDQSS DQS and Bus (B1) DQ
tWPRE DDR tRPRE DQS DQ ‡
tWPST DDR tPST DQS DQ ‡
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS DQ ‡
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDH-Diff(base) DDR Hold-Diff DQS and DQ None
tDH-Diff(derated) DDR Hold-Diff DQS and DQ None
tDH-Diff(Vref-based) Hold DQS and DQ None
tDQSH Positive Width DQS and DQ None
tDQSL Negative Width DQS and DQ None
tDS-Diff(base) DDR Setup-Diff DQS and DQ None
tDS-Diff(derated) DDR Setup-Diff DQS and DQ None
tDS-Diff(Vref-based) Setup DQS and DQ None
tDSH-Diff Hold DQS and Clock DQ ‡
tDSS-Diff Setup DQS and Clock DQ ‡
tDVAC(DQS) Time Outside Level DQS DQ ‡
TdIPW-High Positive Width DQ DQS ‡
TdIPW-Low Negative Width DQ DQS ‡
Slew Rate DQS
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS ‡
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS ‡
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS ‡
Slew Rate-Setup- Rise Slew Rate DQ DQS ‡
Rise(DQ)

82 DDR Analysis
References LPDDR3 Measurement Sources

Table 16: LPDDR3 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
Read Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
tRPRE DDR tRPRE DQS DQ ‡
tRPST DDR tRPST DQS DQ ‡
tDQSCK DDR2tDQSCK DQS and Clock DQ ‡
Differential DQS
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ ‡
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDQSQ-Diff Setup DQS and DQ None
tDVAC(DQS) Time Outside Level DQS DQ ‡
tAC-Diff DDR Setup-Diff DQ and Clock DQS ‡
tDQSCK-Diff Skew DQS and Clock DQ ‡
tQH Hold DQS and DQ None
tQSH Positive Width DQS DQ ‡
tQSL Negative Width DQS DQ ‡
Slew Rate DQ
SRQse-Fall(DQ) Fall Slew Rate DQ DQS ‡
SRQse-Rise(DQ) Rise Slew Rate DQ DQS ‡
Clock (Diff)
tCH(abs) Positive Width Clock None
tCH(avg) DDR tCH(avg) Clock None
tCK(abs) Period Clock None
tCK(avg) DDR tCK(avg) Clock None
tCL(abs) Negative Width Clock None
tCL(avg) DDR tCL(avg) Clock None
tDVAC(CK) Time Outside Level CK None
tERR DDR tERR Clock None
tJIT(cc) CC–Period Clock None
tJIT(duty) DDR tJIT(duty) Clock None
tJIT(per) DDR tJIT(per) Clock None
InputSlew-Diff-Fall(CK) Fall Slew Rate Clock None
InputSlew-Diff-Rise(CK) Rise Slew Rate Clock None

DDR Analysis 83
References LPDDR3 Measurement Sources

Table 16: LPDDR3 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
Clock (Single Ended)
AC-OverShoot(CK#) OverShoot Clock# None
AC-OverShoot(CK) OverShoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock# None
AC-OvershootArea(CK) DDR Over Area Clock None
AC-UnderShoot(CK#) UnderShoot Clock# None
AC-UnderShoot(CK) UnderShoot Clock None
AC-UndershootArea(CK#) DDR Under Area Clock# None
AC-UndershootArea(CK) DDR Under Area Clock None
Vix(ac)CK V-Diff-Xovr Clock and Clock# None
VSEH(AC)CK# Cycle Max Clock# None
VSEH(AC)CK Cycle Max Clock None
VSEL(AC)CK# Cycle Min Clock# None
VSEL(AC)CK Cycle Min Clock None
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-OverShoot(DQ) OverShoot DQ DQS
AC-UnderShoot(DQ) UnderShoot DQ DQS
AC-OverShoot(DQS#) OverShoot DQS# DQ, DQS
AC-OverShoot(DQS) OverShoot DQS DQ ‡
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ ‡
AC-UnderShoot(DQS#) UnderShoot DQS# DQ, DQS
AC-UnderShoot(DQS) UnderShoot DQS DQ ‡
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-UndershootArea(DQS) DDR Under Area DQS DQ ‡
Vix(ac)DQS DDR3 Vix(ac) DQS DQ ‡
VSEH(AC)DQS# Cycle Max DQS# DQ ‡
VSEH(AC)DQS Cycle Max DQS DQ ‡
VSEL(AC)DQS# Cycle Min DQS# DQ ‡
VSEL(AC)DQS Cycle Min DQS DQ ‡

84 DDR Analysis
References LPDDR3 Measurement Sources

Table 16: LPDDR3 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
Address/Command
AC-OverShoot OverShoot Addr/Cmd None
AC-OvershootArea DDR Over Area Addr/Cmd None
AC-UnderShoot UnderShoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
Slew Rate-Hold- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Hold- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
Slew Rate-Setup- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Setup- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
tIH(base) DDR Hold-Diff Clock and Addr/Cmd None
tIH(base)CA DDR Hold-Diff Clock and Addr/Cmd None
tIH(base)CS DDR Hold-Diff Clock and Addr/Cmd None
tIH(derated) DDR Hold-Diff Clock and Addr/Cmd None
tIH(derated)CA DDR Hold-Diff Clock and Addr/Cmd None
tIH(derated)CS DDR Hold-Diff Clock and Addr/Cmd None
tIPW-High High Time Clock and Addr/Cmd None
tIPW-High(CA) High Time Addr/Cmd None
tIPW-High(CS) High Time Addr/Cmd None
tIPW-Low Low Time Clock and Addr/Cmd None
tIPW-Low(CA) Low Time Addr/Cmd None

DDR Analysis 85
References DDR Measurement Sources

Table 16: LPDDR3 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tIPW-Low(CS) Low Time Addr/Cmd None
tIS(base)CA DDR Setup-Diff Clock and Addr/Cmd None
tIS(base)CS DDR Setup-Diff Clock and Addr/Cmd None
tIH(derated)CA DDR Setup-Diff Clock and Addr/Cmd None
tIH(derated)CS DDR Setup-Diff Clock and Addr/Cmd None
xxx

‡ Required so that the Search-and-Mark feature can properly identify bursts

DDR Measurement Sources

The sources required for analysis may include DQS(Strobe), DQ(Data), DQS# (Strobe), Clock, Clock#,
and Addr/Cmd. DQ and DQS can be either Single-Ended (SE) or Differential (Diff). CS Source is
available, as appropriate, as an optional qualifier.

The following table lists the sources required for each DDR measurement:
Table 17: DDR measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
Differential DQS
tDSH-Diff Hold DQS and Clock DQ †
tDSS-Diff Setup DQS and Clock DQ †
Single Ended DQS
tDH-SE DDR Hold-SE DQS and DQ None
tDIPW-SE Period DQ DQS †
tDSH-SE Hold DQS and Clock DQ †
tDS-SE DDR Setup–SE DQS and DQ None
tDSS-SE Setup DQS and Clock DQ †
tWPRE DDR tRPRE DQS DQ †
tWPST DDR tPST DQS DQ †
Read Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
Differential DQS
tAC-Diff DDR Setup-Diff DQ and Clock DQS †

86 DDR Analysis
References DDR Measurement Sources

Table 17: DDR measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tDQSCK-Diff Skew DQS and Clock DQ †
tQH Hold DQS and DQ None
Single Ended DQS
tDQSQ-SE Setup DQS and DQ None
tRPRE DDR tRPRE DQS DQ †
tRPST DDR tRPST DQS DQ †
Clock (Diff)
tCH Pos Width Clock None
tCK Period Clock None
tCL Neg Width Clock None
tHP Period Clock None
VID(ac) DDR VID(ac) Clock None
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# None
AC-Overshoot(CK) Overshoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock# None
AC-OvershootArea(CK) DDR Over Area Clock None
AC-Undershoot(CK#) Undershoot Clock# None
AC-Undershoot(CK) Undershoot Clock None
AC-UndershootArea(CK#) DDR Under Area Clock# None
AC-UndershootArea(CK) DDR Under Area Clock None
Vix(ac)CK V–Diff–Xovr Clock and Clock# None
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ †
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ †
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ †
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-UndershootArea(DQS) DDR Under Area DQS DQ †
Vix(ac)DQS V–Diff–Xovr DQS and DQS# DQ †

DDR Analysis 87
References DDR Measurement Sources

Table 17: DDR measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
Address/Command
AC-Overshoot Overshoot Addr/Cmd None
AC-OvershootArea DDR Over Area Addr/Cmd None
AC-Undershoot Undershoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
tIH(base) DDR Hold–Diff Clock and Addr/Cmd None
tIPW-High High Time Clock and Addr/Cmd None
tIPW-Low Low Time Clock and Addr/Cmd None
tIS(base) DDR Setup–Diff Clock and Addr/Cmd None
xxx

† Required so that the Search-and-Mark feature can properly identify bursts

88 DDR Analysis
References DDR2 Measurement Sources

DDR2 Measurement Sources

The sources required for analysis may include DQS(Strobe), DQ(Data), DQS# (Strobe), Clock, Clock#,
CS Source, and Addr/Cmd. DQ and DQS can be either Single-Ended (SE) or Differential (Diff). Read
and Write bursts have CS as an optional source.

The following table lists the sources required for each DDR2 measurement:
Table 18: DDR2 measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS DQ †
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQS DQ †
tDH-Diff(base) DDR Hold–Diff DQS and DQ None
tDH-Diff(derated) DDR Hold–Diff DQS None
tDQSH Pos Width DQS DQ †
tDQSL Neg Width DQS and DQ DQ †
tDQSS-Diff Skew DQS and Clock DQ †
tDS-Diff(base) DDR Setup–Diff DQS and DQ None
tDS-Diff(derated) DDR Setup–Diff DQS and DQ None
tDSH-Diff Hold DQS and Clock DQ †
tDSS-Diff Setup DQS and Clock DQ †
tDVAC(DQS) Time Outside Level DQS DQ
Single Ended DQS
Slew Rate-Setup-SE- Fall Slew Rate DQS DQ †
Fall(DQS)
Slew Rate-Setup-SE- Rise Slew Rate DQS DQ †
Rise(DQS)
Slew Rate-Hold-SE- Fall Slew Rate DQS DQ †
Fall(DQS)
Slew Rate-Hold-SE- Rise Slew Rate DQS DQ †
Rise(DQS)
tDH-SE(base) DDR Hold–SE DQS and DQ None
tDH-SE(derated) DDR Hold–SE DQS and DQ None
tDIPW-SE Period DQ DQS
tDQSS-SE Skew DQS and Clock DQ †
tDSH-SE Hold DQS and Clock DQ †

DDR Analysis 89
References DDR2 Measurement Sources

Table 18: DDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tDS-SE(base) DDR Setup–SE DQS and DQ None
tDS-SE(derated) DDR Setup–SE DQS and DQ None
tDSS-SE Setup DQS and Clock DQ †
Slew Rate DQ
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS †
Slew Rate-Setup-Rise(DQ) Rise Slew Rate DQ DQS †
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS †
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS †
tWPRE DDR tRPRE DQS DQ †
tWPST DDR tPST DQS DQ †
Read Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
Differential DQS
tAC-Diff DDR Setup-Diff DQ and Clock DQS †
tDQSQ-Diff Setup DQS and DQ None
tQH Hold DQS and DQ None
tDVAC(DQS) Time Outside Level DQS DQ
Single Ended DQS
tDQSCK-SE Skew DQS and Clock None
tDQSQ-SE Setup DQ and DQS None
tRPRE DDR tRPRE DQS DQ †
tWPRE DDR tPST DQS DQ †
Vox(ac)DQS V-Diff-Xovr DQS, DQS# DQ
Clock (Diff)
tCH(abs) Pos Width Clock None
tCH(avg) DDR tCH(avg) Clock None
tCK(abs) Period Clock None
tCK(avg) DDR tCK(avg) Clock None
tCL(abs) Neg Width Clock None
tCL(avg) DDR tCL(avg) Clock None
tDVAC(CK) Time Outside Level CK None
tERR(11–50per) DDR tERR(m–n) Clock None
tERR(2per) DDR tERR(n) Clock None
tERR(3per) DDR tERR(n) Clock None
tERR(4per) DDR tERR(n) Clock None
tERR(5per) DDR tERR(n) Clock None

90 DDR Analysis
References DDR2 Measurement Sources

Table 18: DDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tERR(6–10per) DDR tERR(m–n) Clock None
tHP Period Clock None
tJIT(cc) CC–Period Clock None
tJIT(duty) DDR tJIT(duty) Clock None
tJIT(per) DDR tJIT(per) Clock None
VID(ac) DDR VID(ac) Clock None
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# None
AC-Overshoot(CK) Overshoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock None
AC-OvershootArea(CK) DDR Over Area Clock None
AC-Undershoot(CK#) Undershoot Clock# None
AC-Undershoot(CK) Undershoot Clock None
AC-UndershootArea(CK#) DDR Under Area Clock None
AC-UndershootArea(CK) DDR Under Area Clock None
Vix(ac)CK V–Diff–Xovr Clock and Clock# None
Vox(ac)CK V–Diff–Xovr Clock and Clock# None
VSWING(MAX)CK Cycle Pk-Pk Clock None
VSWING(MAX)CK# Cycle Pk-Pk Clock None
DQS (Single Ended)
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
Vix(ac)DQS V–Diff–Xovr DQS DQ †
VSWING(MAX)DQS Cycle Pk-Pk DQS DQ †
VSWING(MAX)DQS# Cycle Pk-Pk DQS# DQ †
DQS (Single Ended, Read)

DDR Analysis 91
References DDR2 Measurement Sources

Table 18: DDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ †
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ †
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ †
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-UndershootArea(DQS) DDR Under Area DQS DQ †
Vox(ac)DQS V-Diff-Xovr DQS, DQS# DQ
Precharge
tRP(MRS) tCMD-CMD Bus, CK None
tRP(REF) tCMD-CMD Bus, CK None
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd None
AC-OvershootArea DDR Over Area Addr/Cmd None
AC-Undershoot Undershoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
InputSlew-Diff-Fall(CK) Fall Slew Rate Clock None
InputSlew-Diff-Rise(CK) Rise Slew Rate Clock None
Slew Rate-Hold- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Hold- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
Slew Rate-Setup- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Setup- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
tIH(base) DDR Hold–Diff Clock and Addr/Cmd None
tIH(derated) DDR Hold–Diff Clock and Addr/Cmd None
tIPW-High High Time Clock and Addr/Cmd None
tIPW-Low Low Time Clock and Addr/Cmd None

92 DDR Analysis
References DDR3 Measurement Sources

Table 18: DDR2 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tIS(base) DDR Setup–Diff Clock and Addr/Cmd None
tIS(derated) DDR Setup–Diff Clock and Addr/Cmd None
xxx

† Required so that the Search-and-Mark feature can properly identify bursts

DDR3 Measurement Sources

The sources required for analysis may include DQS(Strobe), DQ(Data), DQS# (Strobe), Clock, Clock#,
and Addr/Cmd. DQ and DQS can be either Single-Ended (SE) or Differential (Diff). CS Source is
available, as appropriate, as an optional qualifier.

The following table lists the sources required for each DDR3 measurement:
Table 19: DDR3 measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS DQ ‡
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDH-Diff(base) DDR Hold-Diff DQS and DQ None
tDH-Diff(derated) DDR Hold-Diff DQS and DQ None
tDQSH Pos Width DQS DQ ‡
tDQSL Neg Width DQS DQ ‡
tDQSS-Diff Skew DQS and Clock DQ ‡
tDS-Diff(base) DDR Setup–Diff DQS and DQ None
tDS-Diff(derated) DDR Setup–Diff DQ and DQS None
tDSH-Diff Hold DQS and Clock DQ ‡
tDSS-Diff Setup DQS and Clock DQ ‡
tDVAC(DQS) Time Outside Level DQS DQ
Single Ended DQS
tDIPW-SE Period DQ DQS ‡
tDQSS-SE Skew DQS and Clock DQ ‡
tDSH-SE Hold DQS and Clock DQ ‡
tDSS-SE Setup DQS and Clock DQ ‡
Slew Rate DQ

DDR Analysis 93
References DDR3 Measurement Sources

Table 19: DDR3 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS ‡
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS ‡
Slew Rate-Setup-Rise(DQ) Rise Slew Rate DQ DQS ‡
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS ‡
tWPRE DDR tWPRE DQS DQ ‡
tWPST DDR tPST DQS DQ ‡
Read Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
Differential DQS
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ ‡
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDQSCK-Diff Skew DQS and Clock DQ ‡
tDQSQ-Diff Setup DQS and DQ None
tQH Hold DQ and DQS None
tDVAC(DQS) Time Outside Level DQS DQ
tRPRE DDR tRPRE DQS DQ ‡
tPST DDR tPST DQS DQ ‡
Clock (Diff)
tCH(abs) Pos Width Clock None
tCH(avg) DDR tCH(avg) Clock None
tCK(abs) Period Clock None
tCK(avg) DDR tCK(avg) Clock None
tCL(abs) Neg Width Clock None
tCL(avg) DDR tCL(avg) Clock None
tDVAC(CK) Time Outside Level CK None
tERR DDR tERR Clock None
tJIT(cc) CC–Period Clock None
tJIT(duty) DDR tJIT(duty) Clock None
tJIT(per) DDR tJIT(per) Clock None
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# None
AC-Overshoot(CK) Overshoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock# None
AC-OvershootArea(CK) DDR Over Area Clock None
AC-Undershoot(CK#) Undershoot Clock# None
AC-Undershoot(CK) Undershoot Clock None

94 DDR Analysis
References DDR3 Measurement Sources

Table 19: DDR3 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-UndershootArea(CK#) DDR Under Area Clock# None
AC-UndershootArea(CK) DDR Under Area Clock None
Vix(ac)CK DDR3 Vix(ac)CK Clock None
VSEH(AC)CK# Cycle Max Clock# None
VSEH(AC)CK Cycle Max Clock None
VSEH(CK#) Cycle Max Clock# None
VSEH(CK) Cycle Max Clock None
VSEL(AC)CK# Cycle Min Clock# None
VSEL(AC)CK Cycle Min Clock None
VSEL(CK#) Cycle Min Clock# None
VSEL(CK) Cycle Min Clock None
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ ‡
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ ‡
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ ‡
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-UndershootArea(DQS) DDR Under Area DQS DQ ‡
Vix(ac)DQS DDR3 Vix(ac) DQS DQ ‡
VSEH(AC)DQS# Cycle Max DQS# DQ ‡
VSEH(AC)DQS Cycle Max DQS DQ ‡
VSEH(DQS#) Cycle Max DQS# DQ ‡
VSEH(DQS) Cycle Max DQS DQ ‡
VSEL(AC)DQS# Cycle Min DQS# DQ ‡
VSEL(AC)DQS Cycle Min DQS DQ ‡
VSEL(DQS#) Cycle Min DQS# DQ ‡
VSEL(DQS) Cycle Min DQS DQ ‡
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS

DDR Analysis 95
References DDR3 Measurement Sources

Table 19: DDR3 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
Precharge
tRP(ACT) tCMD-CMD Bus, CK None
tRP(MRS) tCMD-CMD Bus, CK None
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd None
AC-OvershootArea DDR Over Area Addr/Cmd None
AC-Undershoot Undershoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
InputSlew-Diff-Fall(CK) Fall Slew Rate Clock None
InputSlew-Diff-Rise(CK) Rise Slew Rate Clock None
Slew Rate-Hold- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Hold- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
Slew Rate-Setup- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Setup- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
tIH(base) DDR Hold–Diff Clock and Addr/Cmd None
tIH(derated) DDR Hold–Diff Clock and Addr/Cmd None
tIPW-High High Time Addr/Cmd None
tIPW-Low Low Time Addr/Cmd None
tIS(base) DDR Setup–Diff Clock and Addr/Cmd None
tIS(derated) DDR Setup–Diff Clock and Addr/Cmd None
xxx

‡ Required so that the Search-and-Mark feature can properly identify bursts

96 DDR Analysis
References DDR3L Measurement Sources

DDR3L Measurement Sources

The sources required for analysis may include DQS (Strobe), DQS# (Strobe), DQ (Data), Clock, Clock #,
and Addr/Cmd. DQ and DQS can be either Single-Ended (SE) or Differential (Diff). Read and Write
bursts have CS as an optional source.

The following table lists the sources required for each DDR3L measurement:
Table 20: DDR3L measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
tWPRE DDR tRPRE DQS DQ ‡
tWPST DDR tPST DQS DQ ‡
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS DQ ‡
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDH-Diff(base) DDR Hold-Diff DQS and DQ None
tDH-Diff(derated) DDR Hold-Diff DQS and DQ None
tDQSH Positive Width DQS and DQ None
tDQSL Negative Width DQS and DQ None
tDQSS-Diff Skew DQS and Clock DQ ‡
tDS-Diff(base) DDR Setup–Diff DQS and DQ None
tDS-Diff(derated) DDR Setup–Diff DQS and DQ None
tDSH-Diff Hold DQS and Clock DQ ‡
tDSS-Diff Setup DQS and Clock DQ ‡
tDVAC(DQS) Time Outside Level DQS DQ ‡
Single Ended DQS
tDIPW-SE Period DQ DQS ‡
tDQSS-SE Skew DQS and Clock DQ ‡
tDSH-SE Hold DQS and Clock DQ ‡
tDSS-SE Setup DQS and Clock DQ ‡
Slew Rate DQ
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS ‡
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS ‡
Slew Rate-Setup-Rise(DQ) Rise Slew Rate DQ DQS ‡
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS ‡
Read Bursts

DDR Analysis 97
References DDR3L Measurement Sources

Table 20: DDR3L measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
tRPRE DDR tRPRE DQS DQS ‡
tRPST DDR tRPST DQS DQS ‡
Differential DQS
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ ‡
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDQSCK-Diff Skew DQS and Clock DQ ‡
tDQSQ-Diff Setup DQS and DQ None
tQH Hold DQS and DQ None
tDVAC(DQS) Time Outside Level DQS DQ ‡
tAC-Diff DDR Setup-Diff DQ and Clock DQS ‡
Slew Rate DQ
SRQse-Fall(DQ) Fall Slew Rate DQ DQS ‡
SRQse-Rise(DQ) Rise Slew Rate DQ DQS ‡
Clock (Diff)
tCH(abs) Positive Width Clock None
tCH(avg) DDR tCH(avg) Clock None
tCK(abs) Period Clock None
tCK(avg) DDR tCK(avg) Clock None
tCL(abs) Negative Width Clock None
tCL(avg) DDR tCL(avg) Clock None
tDVAC(CK) Time Outside Level CK None
tERR DDR tERR Clock None
tJIT(cc) CC–Period Clock None
tJIT(duty) DDR tJIT(duty) Clock None
tJIT(per) DDR tJIT(per) Clock None
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# None
AC-Overshoot(CK) Overshoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock# None
AC-OvershootArea(CK) DDR Over Area Clock None
AC-Undershoot(CK#) Undershoot Clock# None
AC-Undershoot(CK) Undershoot Clock None
AC-UndershootArea(CK#) DDR Under Area Clock# None
AC-UndershootArea(CK) DDR Under Area Clock None
Vix(ac)CK V-Diff-Xovr Clock and Clock# None

98 DDR Analysis
References DDR3L Measurement Sources

Table 20: DDR3L measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
VSEH(AC)CK# Cycle Max Clock# None
VSEH(AC)CK Cycle Max Clock None
VSEH(CK#) Cycle Max Clock# None
VSEH(CK) Cycle Max Clock None
VSEL(AC)CK# Cycle Min Clock# None
VSEL(AC)CK Cycle Min Clock None
VSEL(CK#) Cycle Min Clock# None
VSEL(CK) Cycle Min Clock None
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ ‡
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ ‡
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ ‡
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-UndershootArea(DQS) DDR Under Area DQS DQ ‡
Vix(ac)DQS DDR3 Vix(ac) DQS DQ ‡
VSEH(AC)DQS# Cycle Max DQS# DQ ‡
VSEH(AC)DQS Cycle Max DQS DQ ‡
VSEH(DQS#) Cycle Max DQS# DQ, DQS
VSEH(DQS) Cycle Max DQS DQ ‡
VSEL(AC)DQS# Cycle Min DQS# DQ ‡
VSEL(AC)DQS Cycle Min DQS DQ ‡
VSEL(DQS#) Cycle Min DQS# DQ, DQS
VSEL(DQS) Cycle Min DQS DQ ‡
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ

DDR Analysis 99
References DDR4 Measurement Sources

Table 20: DDR3L measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd None
AC-OvershootArea DDR Over Area Addr/Cmd None
AC-Undershoot Undershoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
Slew Rate-Hold- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Hold- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
Slew Rate-Setup- Fall Slew Rate Addr/Cmd None
Fall(Addr/Cmd)
Slew Rate-Setup- Rise Slew Rate Addr/Cmd None
Rise(Addr/Cmd)
tIH(base) DDR Hold–Diff Clock and Addr/Cmd None
tIH(derated) DDR Hold–Diff Clock and Addr/Cmd None
tIPW-High High Time Clock and Addr/Cmd None
tIPW-Low Low Time Clock and Addr/Cmd None
tIS(base) DDR Setup–Diff Clock and Addr/Cmd None
tIS(derated) DDR Setup–Diff Clock and Addr/Cmd None
xxx

‡ Required so that the Search-and-Mark feature can properly identify bursts

DDR4 Measurement Sources

The sources required for analysis may include DQS (Strobe), DQS# (Strobe), DQ (Data) , Clock, Clock #,
and Addr/Cmd. DQ and DQS can be either Single-Ended (SE) or Differential (Diff). Read and Write
bursts have CS as an optional source.

100 DDR Analysis

References DDR4 Measurement Sources

The following table lists the sources required for each DDR4 measurement:
Table 21: DDR4 measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
RX Mask Mask Hits DQS and DQ None
tWPRE DDR tRPRE DQS DQ ‡
tWPST DDR tPST DQS DQ ‡
Differential DQS
tDVAC(DQS) DDR Hold–Diff DQS and DQ None
tDQSH Positive Width DQS and DQ None
tDQSL Negative Width DQS and DQ None
tDQSS-Diff Time Outside Level DQS DQ ‡
tDS-Diff(base) DDR Setup–Diff DQS and DQ None
tDSH-Diff Hold DQS and Clock DQ ‡
tDSS-Diff Setup DQS and Clock DQ ‡
SRIN_dIVW_Fall Fall Slew Rate DQ DQS ‡
SRIN_dIVW_Rise Rise Slew Rate DQ DQS ‡
TdIPW-High Positive Width DQ DQS ‡
TdIPW-Low Negative Width DQ DQS ‡
VIHL_AC Cycle Pk-Pk DQ DQS ‡
Read Bursts
Data Eye Width Eye Width DQS and DQ None
Data Eye Height Eye Height DQS and DQ None
tRPRE DDR tRPRE DQS DQ ‡
tRPST DDR tRPST DQS DQ ‡
Differential DQS
tDQSCK-Diff Skew DQS and Clock DQ ‡
tQH Hold DQS and DQ None
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ ‡
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ ‡
tDQSQ-Diff Setup DQS and DQ None
tDVAC(DQS) Time Outside Level DQS DQ ‡
tHZ(DQ) DDR tHZDQ Clock and DQ DQS ‡
tLZ(DQ) DDR tLZDQ Clock and DQ DQS ‡
tQSH Positive Width DQS DQ ‡
tQSL Negative Width DQS DQ ‡

DDR Analysis 101

References DDR4 Measurement Sources

Table 21: DDR4 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
Single Ended DQS
tHZ(DQS) DDR tHZDQ Clock and DQS DQ ‡
tLZ(DQS) DDR tLZDQ Clock and DQS DQ ‡
Slew Rate DQ
SRQse-Fall(DQ) Fall Slew Rate DQ DQS ‡
SRQse-Rise(DQ) Rise Slew Rate DQ DQS ‡
Clock (Diff)
tCH(abs) Positive Width Clock None
tCH(avg) DDR tCH(avg) Clock None
tCK(abs) Period Clock None
tCK(avg) DDR tCK(avg) Clock None
tCL(abs) Negative Width Clock None
tCL(avg) DDR tCL(avg) Clock None
tDVAC(CK) Time Outside Level CK None
tERR DDR tERR Clock None
tJIT(cc) CC–Period Clock None
tJIT(duty) DDR tJIT(duty) Clock None
tJIT(per) DDR tJIT(per) Clock None
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# None
AC-Overshoot(CK) Overshoot Clock None
AC-OvershootArea(CK#) DDR Over Area Clock# None
AC-OvershootArea(CK) DDR Over Area Clock None
AC-Undershoot(CK#) Undershoot Clock# None
AC-Undershoot(CK) Undershoot Clock None
AC-UndershootArea(CK#) DDR Under Area Clock# None
AC-UndershootArea(CK) DDR Under Area Clock None
Vix(ac)CK V-Diff-Xovr Clock and Clock# None
VSEH(CK#) Cycle Max CK# None
VSEH(CK) Cycle Max CK None
VSEL(CK#) Cycle Min CK# None
VSEL(CK) Cycle Min CK None
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS

102 DDR Analysis

References DDR4 Measurement Sources

Table 21: DDR4 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ ‡
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ ‡
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ ‡
AC-Under- DDR Under Area DQS# DQ, DQS
shootArea(DQS#)
AC-UndershootArea(DQS) DDR Under Area DQS DQ ‡
VSEH(DQS#) Cycle Max DQS# DQ, DQS
VSEH(DQS) Cycle Max DQS DQ ‡
VSEL(DQS#) Cycle Min DQS# DQ, DQS
VSEL(DQS) Cycle Min DQS DQ ‡
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd None
AC-OvershootArea DDR Over Area Addr/Cmd None
AC-Undershoot Undershoot Addr/Cmd None
AC-UndershootArea DDR Under Area Addr/Cmd None
tIPW-High High Time Clock and Addr/Cmd None
tIPW-Low Low Time Clock and Addr/Cmd None
xxx

‡ Required so that the Search-and-Mark feature can properly identify bursts

DDR Analysis 103

References GDDR5 Measurement Sources

GDDR5 Measurement Sources

The sources required for analysis may include DQ, WCK, WCK#, CK, CK#,WE, CS, CAS, RAS, CKE,
and Addr/Cmd.

The following table lists the sources required for each GDDR5 measurement:
Table 22: GDDR5 measurement sources
DPOJET base Additional required
DDR measurements measurement Performed on sources
Write Bursts
Data Eye Width Eye Width DQ and WCK None
Data Eye Height Eye Height DQ and WCK None
tWRPDE tBurstToCMD CK WE, CS, CAS, RAS, CKE
tWRSRE tBurstToCMD CK WE, CS, CAS, RAS, CKE
Read Bursts
Data Eye Height Eye Height DQ and WCK None
Data Eye Width Eye Width DQ and WCK None
tRDPDE tBurstToCMD CK WE, CS, CAS, RAS, CKE
tRDSRE tBurstToCMD CK WE, CS, CAS, RAS, CKE
WCK (Single Ended)
Vin(WCK#) High-Low WCK# None
VIN(WCK) High-Low WCK None
Vix(ac)WCK V-Diff-Xovr WCK, WCK# None
VOH(WCK#) High WCK# None
VOH(WCK) High WCK None
VOL(WCK#) Low WCK# None
VOL(WCK) Low WCK None
WCK Slew-Fall(WCK#) Fall Slew Rate WCK# None
WCK Slew-Fall(WCK) Fall Slew Rate WCK None
WCK Slew-Rise(WCK#) Rise Slew Rate WCK# None
WCK Slew-Rise(WCK) Rise Slew Rate WCK None
WCK (Diff)
SSC Downspread(WCK) SSC-Freq-DEV WCK None
SSC Mod Freq(WCK) SSC-MOD-FREQ WCK None
SSC Profile(WCK) SSC-PROFILE WCK None
tDVAC(WCK) Time Outside Level WCK None
tJIT(cc) CC-Period WCK None
tJIT(per) DDR tJIT(per) WCK None
tWCK Period WCK None

104 DDR Analysis

References GDDR5 Measurement Sources

Table 22: GDDR5 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
tWCK-DJ TJ@BER WCK None
tWCK-Fall-Slew Fall Slew Rate WCK None
tWCKH Positive and Negative WCK None
Width
tWCKHP Period WCK None
tWCKL Positive and Negative WCK None
Width
tWCK-Rise-Slew Rise Slew Rate WCK None
tWCK-RJ RJ WCK None
tWCK-TJ TJ@BER WCK None
VWCK-SWING High-Low WCK None
Clock(Diff)
SSC Downspread(CK) SSC-FREQ-DEV CK None
SSC Mod Freq(CK) SSC-MOD-FREQ CK None
SSC Profile(CK) SSC-PROFILE CK None
tCH Pos Width CK None
tCK Period CK None
tCL Neg Width CK None
tDVAC(CK) Time Outside Level CK None
tHP Period CK None
tJIT(cc) CC-Period CK None
tJIT(per) DDR tJIT(per) CK None
Clock(Single Ended)
CKslew-Fall(CK#) Fall Slew Rate CK# None
CKslew-Fall(CK) Fall Slew Rate CK None
CKslew-Rise(CK#) Rise Slew Rate CK# None
CKslew-Rise(CK) Rise Slew Rate CK None
VIN(CK#) High-Low CK# None
VIN(CK) High-Low CK None
Vix(ac)CK V-Diff-Xovr CK and CK# None
Address/Command Measurements
tAH Hold CK, Addr./Cmd None
tAPW Period Addr/Cmd None
tAS Setup CK, Addr./Cmd None
tCMDH Hole CK, Addr./Cmd None
tCMDPW Period CK, Addr./Cmd None
tCMDS Setup CK, Addr./Cmd None

DDR Analysis 105

References GDDR5 Measurement Sources

Table 22: GDDR5 measurement sources (cont.)

DPOJET base Additional required
DDR measurements measurement Performed on sources
Refresh
tCKSRE tCKSRE CK WE, CS, CAS, RAS, CKE
tCKSRX tCKSRX CK WE, CS, CAS, RAS, CKE
tREFTR(Read) tCMD-CMD CK WE, CS, CAS, RAS, CKE
tREFTR(Write) tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRFC tCMD-CMD CK WE, CS, CAS, RAS, CKE
tXSNRW tCMD-CMD CK WE, CS, CAS, RAS, CKE
Power Down
tPD tCMD-CMD CK WE, CS, CAS, RAS, CKE
Active
tRAS tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRC tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRCDRD tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRCDWR tCMD-CMD CK WE, CS, CAS, RAS, CKE
Precharge
tPPD tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRP(ACT) tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRP(MRS) tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRP(REP) tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRP(SRE) tCMD-CMD CK WE, CS, CAS, RAS, CKE
tRTPL tCMD-CMD CK WE, CS, CAS, RAS, CKE
xxx

106 DDR Analysis

References Measurement Range Limits

Measurement Range Limits

The following tables lists the measurement range limits of DDR measurements for different data rates:

NOTE. Measurement Range Limits are provided for each measurement under the General configure
tab of the DPOJET application. These range limits are always ON (OFF is disabled) for two source
measurements such as Skew, Setup, Hold and others. The range limits are used by the algorithms to
associate valid edge of first source to the valid edge of the second source.

Data Rate 1 UI 2 UI
200 MT/s 5 ns 10 ns
266 MT/s 3.7594 ns 7.5188 ns
333 MT/s 3.003 ns 6.006 ns
370 MT/s 2.702 ns 5.404 ns
400 MT/s 2.5 ns 5 ns
533 MT/s 1.875 ns 3.75 ns
667 MT/s 1.4995 ns 2.999 ns
800 MT/s 1.25 ns 2.5 ns
1333 MT/s 0.75 ns 1.5 ns
1600 MT/s 0.625 ns 1.25 ns
1866 MT/s 0.535 ns 1.071 ns
2133 MT/s 0.468 ns 0.937 ns
xxx

The following measurements have different range limits as shown:

Table 23: Measurement range limits
Measurement Maximum Minimum
tDQSCK-Diff UI –UI
tDQSQ-Diff UI / 2 –UI / 2
tAC-Diff UI / 2 –UI / 2
tDQSCK-SE UI –UI
tDQSQ-SE UI / 2 –UI / 2
tDH-Diff(base) UI 0
tDH-Diff(derated) UI 0
tDQSS-Diff UI –UI
tDS-Diff(base) UI 0
tDS-Diff(derated) UI 0
tDSH-Diff 2 UI 0

DDR Analysis 107

References Dynamic Limits for LPDDR Measurements

Table 23: Measurement range limits (cont.)

Measurement Maximum Minimum
tDSS-Diff 2 UI 0
tDQSS-SE UI – UI
tDSH-SE 2 UI 0
tDSS-SE 2 UI 0
tDH-SE(base) UI 0
tDH-SE(derated) UI 0
tDS-SE(base) UI 0
tDS-SE(derated) UI 0
tIH(base) 2 UI 0
tIH(derated) 2 UI 0
tIS(base) 2 UI 0
tIS(derated) 2 UI 0
tQH 1.5 UI UI / 2
xxx

Dynamic Limits for LPDDR Measurements

The following table lists the dynamic limits for LPDDR measurements, which are common for all
LPPDR data rates. For more details, refer to the LPDDR JEDEC standard specification mentioned in the
application readme.txt.

NOTE. Dynamic limits are the same for all LPDDR data rates.

Table 24: Dynamic limits for LPDDR

Dynamic limits
Measurement Min Max Units
tCH 0.45 0.55 tCK
tCL 0.45 0.55 tCK
Vix(ac)CK 0.4 * Vdd 0.6 * Vdd –
Vix(ac)DQS 0.4 * Vdd 0.6 * Vdd –
Vid(ac) 0.6 * Vdd *Vdd+0.6 –
xxx

108 DDR Analysis

References Dynamic Limits for LPDDR2 Measurements

Dynamic Limits for LPDDR2 Measurements

The following table lists the dynamic limits for LPDDR2 measurements. For more details, refer to the
LPDDR2 JEDEC standard specification mentioned in the application readme.txt.

NOTE. Refer to the standard specific JEDEC document for derated measurements such as tIS(derated),
tIH(derated), tDS-Diff(derated), and tDH-Diff(derated) for calculating dynamic limits.

Table 25: Dynamic limits for LPDDR2

Dynamic limits
Measurement Data rate (MT/s) Min Max Units
tCH(avg) 0.45 0.55 tCK(avg)
tCL(avg) 0.45 0.55 tCK(avg)
tCH(abs) 0.43 0.57 tCK(avg)
tCL(abs) 0.43 0.57 tCK(avg)
tERR(13–50) ‡ (1 + 0.68ln(n)) * (1 + 0.68ln(n)) * ps
tJIT(per)min tJIT(per)max
VSEH(AC)DQS 1066 to 466 MT/s (VDDQ / 2) + 0.220 – V
400 to 200 MT/s (VDDQ / 2) + 0.300 – V
VSEH(AC)DQS# 1066 to 466 MT/s (VDDQ / 2) + 0.220 – V
400 to 200 MT/s (VDDQ / 2) + 0.300 – V
VSEH(AC)CK 1066 to 466 MT/s (VDDQ / 2) + 0.220 – V
400 to 200 MT/s (VDDQ / 2) + 0.300 – V
VSEH(AC)CK# 1066 to 466 MT/s (VDDQ / 2) + 0.220 – V
400 to 200 MT/s (VDDQ / 2) + 0.300 – V
VSEL(AC)DQS 1066 to 466 MT/s – (VDDQ / 2) – 0.220 V
400 to 200 MT/s – (VDDQ / 2) – 0.300 V
VSEL(AC)DQS# 1066 to 466 MT/s – (VDDQ / 2) – 0.220 V
400 to 200 MT/s – (VDDQ / 2) – 0.300 V
VSEL(AC)CK 1066 to 466 MT/s – (VDDQ / 2) – 0.220 V
400 to 200 MT/s – (VDDQ / 2) – 0.300 V
VSEL(AC)CK# 1066 to 466 MT/s – (VDDQ / 2) – 0.220 V
400 to 200 MT/s – (VDDQ / 2) – 0.300 V
xxx

‡ Includes measurements from tERR13per to tERR50per

DDR Analysis 109

References Dynamic Limits for LPDDR3 Measurments

Dynamic Limits for LPDDR3 Measurments

The following table lists the dynamic limits for LPDDR3 measurements. For more details, refer to the
LPDDR3 JEDEC standard specification mentioned in the application readme.txt.

NOTE. Refer to the standard specific JEDEC document for derated measurements such as tIS(derated),
tIH(derated), tDS-Diff(derated), and tDH-Diff(derated) for calculating dynamic limits.

Table 26: Dynamic limits for LPDDR3

Dynamic limits
Measurement Data rate (MT/s) Min Max Units
tCH(avg) 0.45 0.55 tCK(avg)
tCL(avg) 0.45 0.55 tCK(avg)
tCH(abs) 0.43 0.57 tCK(avg)
tCL(abs) 0.43 0.57 tCK(avg)
tERR(13–50) ‡ (1 + 0.68ln(n)) * (1 + 0.68ln(n)) * ps
tJIT(per)min tJIT(per)max
VSEH(DQS) (VDDQ / 2) + 0.150 – V
VSEH (DQS#) (VDDQ / 2) + 0.150 – V
VSEH(CK) (VDDQ / 2) + 0.150 – V
VSEH(CK#) (VDDQ / 2) + 0.150 – V
VSEL(DQS) – (VDDQ / 2) + 0.150 V
VSEL(DQS#) – (VDDQ / 2) + 0.150 V
VSEL(CK) – (VDDQ / 2) + 0.150 V
VSEL(CK#) – (VDDQ / 2) + 0.150 V
VSEH(AC)DQS (VDDQ / 2) + 0.150 – V
VSEH(AC)DQS# (VDDQ / 2) + 0.150 – V
VSEH(AC)CK (VDDQ / 2) + 0.150 – V
VSEH(AC)CK# (VDDQ / 2) + 0.150 – V
VSEL(AC)DQS – (VDDQ / 2) – 0.150 V
VSEL(AC)DQS# – (VDDQ / 2) – 0.150 V
VSEL(AC)CK – (VDDQ / 2) – 0.150 V
VSEL(AC)CK# – (VDDQ / 2) – 0.150 V
xxx

‡ Includes measurements from tERR13per to tERR50per

110 DDR Analysis

References Dynamic Limits for DDR Measurements

Dynamic Limits for DDR Measurements

The following table lists the dynamic limits for DDR measurements, which are common for all DDR data
rates. For more details, refer to the DDR JEDEC standard specification mentioned in the application
readme.txt.

NOTE. Dynamic limits are the same for all DDR data rates.

Table 27: Dynamic limits for DDR

Dynamic limits
Measurement Min Max Units
tCH 0.45 0.55 tCK
tCL 0.45 0.55 tCK
Vix(ac)CK 0.5*Vdd–0.2 0.5*Vdd+0.2 –
Vix(ac)DQS 0.5*Vdd–0.2 0.5*Vdd+0.2 –
Vid(ac) 0.7 Vdd+0.6 –
xxx

DDR Analysis 111

References Dynamic Limits for DDR2 Measurements

Dynamic Limits for DDR2 Measurements

The following table lists the dynamic limits for DDR2 measurements. For more details, refer to the DDR2
JEDEC standard specification mentioned in the application readme.txt.

NOTE. Dynamic limits are the same for all DDR2 data rates except for those data rates specifically
mentioned in the table.

Table 28: Dynamic limits for DDR2

Dynamic limits
Measurement Data rate (MT/s) Min Max Units
tCH(avg) 667, 800 0.48 0.52 tCK(avg)
tCL(avg) 667, 800 0.48 0.52 tCK(avg)
tCH(abs) 0.45 0.55 –
tCL(abs) 0.45 0.55 –
tIPW 0.6 NA –
Vix(ac)CK 0.5*Vdd–0.175 0.5*Vdd+0.175 –
Vix(ac)DQS 0.5*Vdd–0.175 0.5*Vdd+0.175 –
Vox(ac)CK 0.5 * Vdd–0.125 0.5 x Vdd+0.125 –
Vox(ac)DQS 0.5 x Vdd–0.125 0.5 x Vdd+ 0.125 –
Vid(ac) 0.5 Vdd –
xxx

112 DDR Analysis

References Dynamic Limits for DDR3 Measurements

Dynamic Limits for DDR3 Measurements

The following table lists the dynamic limits for DDR3 measurements. For more details, refer to the DDR3
JEDEC standard specification mentioned in the application readme.txt.

NOTE. Dynamic limits are the same for all DDR3 data rates.

Table 29: Dynamic limits for DDR3

Dynamic limits
Measurement Min Max Units
tCH(avg) 0.47 * tCK(avg) 0.53 * tCK(avg) tCK(avg)
tCL(avg) 0.47 * tCK(avg) 0.53 * tCK(avg) tCK(avg)
tCH(abs) 0.43 * tCK(avg) NA tCK(avg)
tCL(abs) 0.43 * tCK(avg) NA tCK(avg)
VSEH(DQS) (VDDQ / 2) + 0.175 – V
VSEH (DQS#) (VDDQ / 2) + 0.175 – V
VSEH(CK) (VDDQ / 2) + 0.175 – V
VSEH(CK#) (VDDQ / 2) + 0.175 – V
VSEL(DQS) – (VDDQ / 2) – 0.175 V
VSEL(DQS#) – (VDDQ / 2) – 0.175 V
VSEL(CK) – (VDDQ / 2) – 0.175 V
VSEL(CK#) – (VDDQ / 2) – 0.175 V
VSEH(AC)DQS (VDDQ / 2) + 0.175 – V
VSEH(AC)DQS# (VDDQ / 2) + 0.175 – V
VSEH(AC)CK (VDDQ / 2) + 0.175 – V
VSEH(AC)CK# (VDDQ / 2) + 0.175 – V
VSEL(AC)DQS – (VDDQ / 2) – 0.175 V
VSEL(AC)DQS# – (VDDQ / 2) – 0.175 V
VSEL(AC)CK – (VDDQ / 2) – 0.175 V
VSEL(AC)CK# – (VDDQ / 2) – 0.175 V
xxx

† Includes measurements from tERR13per to tERR50per

DDR Analysis 113

References Dynamic Limits for DDR3L Measurements

Dynamic Limits for DDR3L Measurements

The following table lists the dynamic limits for DDR3L measurements.

NOTE. Dynamic limits are the same for all DDR3L data rates.

Table 30: Dynamic limits for DDR3L

Dynamic limits
Measurement Min Max Units
tCH(avg) † 0.47 * tCK(avg) 0.53 * tCK(avg) tCK(avg)
tCL(avg) † 0.47 * tCK(avg) 0.53 * tCK(avg) tCK(avg)
tCH(abs) † 0.43 * tCK(avg) NA tCK(avg)
tCL(abs) † 0.43 * tCK(avg) NA tCK(avg)
VSEH(DQS) † (VDDQ / 2) + 0.175 – V
VSEH (DQS#) † (VDDQ / 2) + 0.175 – V
VSEH(CK) † (VDDQ / 2) + 0.175 – V
VSEH(CK#) † (VDDQ / 2) + 0.175 – V
VSEL(DQS) † – (VDDQ / 2) – 0.175 V
VSEL(DQS#) † – (VDDQ / 2) – 0.175 V
VSEL(CK) † – (VDDQ / 2) – 0.175 V
VSEL(CK#) † – (VDDQ / 2) – 0.175 V
VSEH(AC)DQS † (VDDQ / 2) + 0.175 – V
VSEH(AC)DQS# † (VDDQ / 2) + 0.175 – V
VSEH(AC)CK † (VDDQ / 2) + 0.175 – V
VSEH(AC)CK# (VDDQ / 2) + 0.175 – V
VSEL(AC)DQS – (VDDQ / 2) – 0.175 V
VSEL(AC)DQS# – (VDDQ / 2) – 0.175 V
VSEL(AC)CK – (VDDQ / 2) – 0.175 V
VSEL(AC)CK# – (VDDQ / 2) – 0.175 V
xxx

† Supported in DDRA application but not called out JEDEC.

114 DDR Analysis

References Dynamic Limits for DDR4 Measurements

Dynamic Limits for DDR4 Measurements

The following table lists the dynamic limits for DDR4 measurements. For more details, refer to the DDR4
JEDEC standard specification mentioned in the application readme.txt.

NOTE. Dynamic limits are the same for all DDR4 data rates.

Table 31: Dynamic limits for DDR4

Dynamic limits
Measurement Min Max Units
tCH(avg) 0.48 * tCK(avg) 0.52 * tCK(avg) tCK(avg)
tCL(avg) 0.48 * tCK(avg) 0.52 * tCK(avg) tCK(avg)
tCH(abs) 0.45 * tCK(avg) NA tCK(avg)
tCL(abs) 0.45 * tCK(avg) NA tCK(avg)
VSEH(DQS) (VDDQ / 2) + 0.175 – V
VSEH (DQS#) (VDDQ / 2) + 0.175 – V
VSEH(CK) (VDDQ / 2) + 0.175 – V
VSEH(CK#) (VDDQ / 2) + 0.175 – V
VSEL(DQS) – (VDDQ / 2) – 0.175 V
VSEL(DQS#) – (VDDQ / 2) – 0.175 V
VSEL(CK) – (VDDQ / 2) – 0.175 V
VSEL(CK#) – (VDDQ / 2) – 0.175 V
xxx

Vih/Vil Reference Levels

On clicking the View button, the VIH(ac)min, VIH(dc)min, VIL(ac)max, VIL(dc)max and VREF(dc)
values are as shown based on the Vref voltage.

DDR Analysis 115

References Vih/Vil Reference Levels

The following table lists the Vih and Vil values for all the DDR generations except GDDR3 and data rate:
Table 32: VIH and VIL values for DDR generations
Genera-
tion Data rate VIH(ac)min VIH(dc)min VREF(dc) VIL(dc) max VIL(ac)max
DDR 200 MT/s 1.56 V 1.4 V 1.25 V 1.1 V 940 mV
266 MT/s 1.56 V 1.4 V 1.25 V 1.1 V 940 mV
333 MT/s 1.56 V 1.4 V 1.25 V 1.1 V 940 mV
400 MT/s 1.61 V 1.45 V 1.3 V 1.15 V 990 mV
DDR2 400 MT/s 1.15 V 1.025 V 900 mV 775 mV 650 mV
533 MT/s 1.15 V 1.025 V 900 mV 775 mV 650 mV
667 MT/s 1.1 V 1.025 V 900 mV 775 mV 700 mV
800 MT/s 1.1 V 1.025 V 900 mV 775 mV 700 mV
DDR3 800 MT/s 925 mV 850 mV 750 mV 650 mV 575 mV
1066 MT/s 925 mV 850 mV 750 mV 650 mV 575 mV
1333 MT/s 925 mV 850 mV 750 mV 650 mV 575 mV
1600 MT/s 925 mV 850 mV 750 mV 650 mV 575 mV
1866 MT/s 885 mV 850 mV 750 mV 650 mV 615 mV
2133 MT/s 885 mV 850 mV 750 mV 650 mV 615 mV

116 DDR Analysis

References Vih/Vil Reference Levels

Table 32: VIH and VIL values for DDR generations (cont.)
Genera-
tion Data rate VIH(ac)min VIH(dc)min VREF(dc) VIL(dc) max VIL(ac)max
DDR3L 800 MT/s 835 mV 765 mV 675 mV 585 mV 515 mV
1066 MT/s 835 mV 765 mV 675 mV 585 mV 515 mV
1333 MT/s 835 mV 765 mV 675 mV 585 mV 515 mV
1600 MT/s 835 mV 765 mV 675 mV 585 mV 515 mV
DDR4 1600 MT/s 735 mV 700 mV 600 mV 500 mV 465 mV
1866 MT/s 735 mV 700 mV 600 mV 500 mV 465 mV
2133 MT/s 735 mV 700 mV 600 mV 500 mV 465 mV
2400 MT/s 735 mV 700 mV 600 mV 500 mV 465 mV
2666 MT/s 735 mV 700 mV 600 mV 500 mV 465 mV
3200 MT/s 735 mV 700 mV 600 mV 500 mV 465 mV
GDDR5 4000 MT/s 900 mV 850 mV 750 mV 650 mV 600 mV
4800 MT/s 900 mV 850 mV 750 mV 650 mV 600 mV
5000 MT/s 900 mV 850 mV 750 mV 650 mV 600 mV
5500 MT/s 900 mV 850 mV 750 mV 650 mV 600 mV
LPDDR 200 MT/s 1.44 V 1.26 V 900 mV 540 mv 360 mV
266 MT/s 1.44 V 1.26 V 900 mV 540 mv 360 mV
333 MT/s 1.44 V 1.26 V 900 mV 540 mv 360 mV
370 MT/s 1.44 V 1.26 V 900 mV 540 mv 360 mV
400 MT/s 1.44 V 1.26 V 900 mV 540 mv 360 mV
LPDDR2 333 MT/s 900 mV 800 mV 600 mV 400 mV 300 mV
400 MT/s 900 mV 800 mV 600 mV 400 mV 300 mV
533 MT/s 820 mV 730 mV 600 mV 470 mV 380 mV
667 MT/s 820 mV 730 mV 600 mV 470 mV 380 mV
800 MT/s 820 mV 730 mV 600 mV 470 mV 380 mV
933 MT/s 900 mV 800 mV 600 mV 400 mV 300 mV
1066 MT/s 820 mV 730 mV 600 mV 470 mV 380 mV
LPDDR3 333 MT/s 750 mV 700 mV 600 mV 500 mV 450 mV
800 MT/s 750 mV 700 mV 600 mV 500 mV 450 mV
1066 MT/s 750 mV 700 mV 600 mV 500 mV 450 mV
1200 MT/s 750 mV 700 mV 600 mV 500 mV 450 mV
1333 MT/s 750 mV 700 mV 600 mV 500 mV 450 mV
1466 MT/s 750 mV 700 mV 600 mV 500 mV 450 mV
1600 MT/s 750 mV 700 mV 600 mV 500 mV 450 mV
xxx

DDR Analysis 117

References Using Digital Channels

Using Digital Channels

You must do the following steps when you select “Logic State+DQ/DQS Phase Alignment” burst detection
method in an MSO oscilloscope. The DDR3 signal is an example here, but a few settings must be changed
for other DDR standards. Using appropriate label names for digital signals (such as RS, CAS, CS and WE)
helps in defining the sources in a bus.

NOTE. Refer “Setting Up Digital Channels” in your oscilloscope user manual for more details on how to
set up digital channels.

Calculating Digital Channel Threshold

Follow the steps to calculate the digital channel threshold:
1. View the analog equivalent of the input digital signal (refer” Viewing Analog Characteristics of Digital
Waveforms” in the MSO oscilloscope user manual).

118 DDR Analysis

References Using Digital Channels

2. Measure the thresholds for the CS signal as shown in an example:

Measure the Min, and Pk-Pk on the analog waveform and calculate the threshold value
approximately as follows:
Threshold Value = Min + 50% of Pk-Pk.
For example: If the measured Min value is 450 mV and Pk-Pk is 666 mV, using the above formula,
the threshold value is set to 750 mV.
3. Enter the calculated threshold value in the Digital setup dialog box under Threshold.

DDR Analysis 119

References Using Digital Channels

NOTE. Thresholds are DUT specific. Carry out the same procedure for every DUT under test.

Configuring Sources for a Bus

The steps to configure source for a bus are:
1. Set up the bus (refer to “Set Up a Parallel Bus” in your MSO oscilloscope user manual)
2. Add sources to the bus. Ensure that the order of sources (MSB to LSB) is in sync with the sources
mentioned in the corresponding symbol file.
For example: DDR3 symbol file specifies the following:

SYMBOL MSB -> LSB

READ 0101
WRITE 0100
xxx

120 DDR Analysis

References Using Digital Channels

Set up the sources for these symbols as shown in the following figure:

Configuring Burst Latency and Tolerance

The following example shows how Burst Latency and Tolerance values are calculated using DDR3
1066 READ burst signal:

NOTE. Burst Latency and Tolerance values are specific to a DUT and should be computed for each
DUT under test.

1. Set up digital channels (see page 118) and configure the bus (see page 120). Connect DQ/DQS to
Ch1/Ch2 sources. Press Single on the oscilloscope front panel for signal acquisition.
2. Locate the READ burst and place the cursor in the centre of the burst. Place the second cursor on the
first rising edge of the DQS signal as shown in the following figure:

DDR Analysis 121

References Using Digital Channels

3. Note the time difference between the two cursors. In this example, it is 10.24 ns (called t1) as shown
in the following figure.
4. Place the cursors on two consecutive rising/falling edges of the DQS signal as shown:

122 DDR Analysis

References Using Digital Channels

5. Note the time difference between the two cursors. It is 1.92 ns (called t2) as shown in the above figure.
6. Calculate CAS Min using the equation:
CAS Min = t1/t2 – 0.5
In the above example, CAS Min= (10.24/1.92) – 0.5 ~ 5 (approximately)
7. Calculate CAS Max using the equation:
CAS Min = t1/t2 + 0.5
In the above example, CAS Min= (10.24/1.92) + 0.5 ~ 6 (approximately)
8. Configure CAS Min and Max values in DDRA as shown:

DDR Analysis 123

References Using Digital Channels

Providing inaccurate CAS Min and MAX values can result in an offset in Mark start/end calculations
which in turn provides inaccurate measurement results. An example of incorrect CAS Min\Max values. is
as follows:

124 DDR Analysis

References Error Codes and Warnings

NOTE. You can perform the above steps once and then save the setup. Setup files help to recall the settings
corresponding to a particular DUT.

Error Codes and Warnings

Code Description
E102 File does not exist.
E103 DPOJET is not able to open the help file. In order to use the help file, please reinstall
DPOJET.
E104 Mask Hits measurement requires an Eye diagram plot but no more plots can be
assigned. Please remove a plot before adding a Mask Hits measurement.
E105 The maximum number of plots you can select is 4.
E106 No Spectrum plot data is available.
E202 The upper range must be greater than the lower range.
E400 A measurement failed to complete successfully.
W410 Number of edges are not sufficient for a measurement.

DDR Analysis 125

References Error Codes and Warnings

Code Description
E411 In at least one zone, there are too few edges to complete a measurement.
E424 No edges or UI of the required type were found in the waveform. If this is not a clock
signal, check the Vref threshold and record length.
E425 No transitions of the selected Bit Type were found in the waveform.
E500 The record lengths of the source waveforms differ. Please configure for sources with
equivalent record lengths.
E1001 Vertical Autoset Failed: Signal on Source x has extreme offset.
E1002 Vertical Autoset Failed: Amplitude of Source x is too small.
E1003 Vertical Autoset Failed: Amplitude or DC offset of Source x is too high.
E1004 Vertical Autoset Failed: No signal on Source x.
E1005 Vertical Autoset Failed: Signal on Source x exceeds top of scale.
E1006 Vertical Autoset Failed: Signal on Source x exceeds bottom of scale.
E1007 Vertical Autoset Failed: Signal on Source x is clipped on top.
E1008 Vertical Autoset Failed: Signal on Source x is clipped on bottom.
E1009 Vertical Autoset Failed: Measurement error ( ISDB error code = 6 ) on Source x.
E1010 Vertical Autoset Failed: Measurement error ( ISDB error code = 7 ) on Source x.
W1011 A change to Source x vertical settings caused overload disconnect. Original settings
are restored and Source x is reconnected. Ignore oscilloscope message.
E1012 Vertical Autoset Failed: None of the selected measurements use live sources
(Ch1-Ch4). Horizontal autoset works for live sources only.
E1013 Vertical Autoset Failed: Invalid signal on Source x.
E1020 Horizontal Autoset Failed: None of the selected measurements use live sources
(Ch1-Ch4). Horizontal autoset works for live sources only.
E1021 Horizontal Autoset Failed: On Source x, cannot determine resolution of rising/falling
edges.
E1022 Horizontal Autoset Failed: Horizontal resolution is at the maximum.
E1026 Horizontal Autoset Failed: Source amplitude to too low.
E1027 Horizontal Autoset Failed: Signal is clipped at the top - positive clipping.
E1028 Horizontal Autoset Failed: Signal is clipped at the bottom - negative clipping.
E1029 Horizontal Autoset Failed: Signal frequency is extremely low.
E1035 Oscilloscope has gone into invalid state. Please restart the system.
E1040 Autoset Failed: None of the live sources (Ch1-Ch4) selected.
W1051 Ref Level Autoset: Waveform for the source x is clipped.
W1053 Ref Level Autoset: Source amplitude is extremely low.
E1054 Ref Level Autoset: Error in setting reference levels.
E1055 Ref Level Autoset Failed: No waveform to measure.
E1056 Ref Level Autoset: Unstable Histogram for waveform on source x.
E1057 Ref Level Autoset: No selected source.
E1058 Ref Level Autoset Failed: Invalid signal on source x.
E1059 Ref Level Autoset Error: Source x is not defined.

126 DDR Analysis

References Error Codes and Warnings

Code Description
E1061 Since Digital Filters (DSP) are enabled, maximum sampling rate has been retained.
To enable adaptive use of lower sampling rate, please choose Analog Only under
Vertical . Bandwidth Enhanced.
E1062 The maximum Record Length (RL) in autoset is restriced to 25M, set the RL manually
for >25M.
E1063 The minimum Record Length (RL) in autoset is restricted to 500K, set the RL manually
for <500K.
E2001 The maximum number of measurements has been reached.
E2002 All the refs are used as sources by the measurements. Export to Ref is not possible.
E2003 Ref ‘x’ is already used as a measurement source.
E2004 Ref ‘x’ is already used as a destination for other measurement.
E2005 No measurement(s) are selected. Export to Ref is not possible.
E2006 No results available to export to ref.
E2007 There are no time trend results for the selected measurement(s).
E2008 No ref destination is selected. Results will not be exported to ref.
E3001 Could not open or create a log file. Please ensure that you have read/write permission
to access log folders and files.
E3002 The specified path is invalid (for example: The specified path is not mapped to a drive).
E3003 The specified path, file name or both exceed the system defined length. For Example:
On Windows-based platforms, the path name must be less than 248 characters and file
names less than 260 characters.
E3004 The specified path directory is read-only or is not empty.
E3005 Please ensure that the file is currently not in use by other process and/or has not
exceeded the file size limit.
E3006 Invalid filename: Check whether the file name contains a colon (:) in the middle of
the string.
E3007 Select at least one measurement from the table before you save.
E3008 There are currently no results to save. Please run a measurement.
E3009 Current statistics is successfully saved at C:\TekApplications\DPOJET\Log\Statistics.
E3010 Access to file/directory denied. Please ensure that the file/directory has read/write
permissions.
E3011 Mask Hits Measurements will not be selected as this feature is not available for Mask
Hits measurement.
E3012 Folder does not exist.
E4000 Not enough data points. Unable to render plot(s).
E4001 Internal measurement error. Please remove a measurement and try again.
E4002 Not enough data points for spectrum computation.
E4003 Due to high memory usage, only a portion of the waveform could be processed. Please
reduce your record length or the number of measurements.
E4004 An error occurred in the edge extraction process.
E4005 Qualifier: The record length and sample interval must match across the waveforms.

DDR Analysis 127

References Error Codes and Warnings

Code Description
E4006 A maximum of 4096 qualifier zones is supported. The entire waveform will not be
processed and hence partial measurement results are available.
E4007 Logic Qualifier enabled and no qualifier zones found.
W4008 The configured Ref voltage for Overshoot must be greater than or equal to the mid
autoset ref levels.
W4009 The configured Ref voltage for Undershoot must be lesser than or equal to the mid
autoset ref levels.
E4013 The configured Ref voltage must be greater than or equal to the mid autoset ref levels.
E4014 The configured Ref voltage must be lesser than or equal to the mid autoset ref levels.
E4015 ‡OMING One or more qualifier zones had too few edges for measurement calculation.
E4016 Not enough edges in the waveform for measurement calculation.
E4017 Qualifier not enabled and hence no qualifier zones found. Please enable the qualifier.
E4018 The preamble is incomplete in all the qualifier zones.
E4019 ‡ The preamble is incomplete in one or more qualifier zones.
E4020 The postamble is incomplete in all the qualifier zones.
E4021 The postamble is incomplete in one or more qualifier zones. Displays the zone number
(x) for which the preamble/postamble fails.
E4022 ‡ Not enough samples present in the qualifier zones. Please increase the sampling
rate and reacquire the waveform.
E4023 The configured ref levels are not correct. The high ref level should be >= Mid and Mid
should be >= Low for both Rise and Fall slopes. Reconfigure the ref levels and run
the measurement.
E4024 Could not compute proper High and Low values.
W4025 The signal does not cross the configured Ref Voltage and hence the result shows zero
population. Please adjust the Ref voltage value.
E4027 From Symbol not found in the acquisition.
E4028 To Symbol not found in the acquisition.
E4029 The configured High Ref voltage must be ≥ to the mid autoset ref levels.
E4030 The configured Low Ref voltage must be ≤ to the mid autoset ref levels.
E4031 The configured High Ref voltage must be ≥ to the mid autoset ref levels and the
configured Low Ref voltage must be ≤ to the mid autoset ref levels.
E5005 1 Occurs while running setup. Please make sure you have finished any previous setup
and closed other applications
W5005 The path or file name exceeds the system limit of 260 characters.
E9004 Derating will not be applied to the limits as Slew Rate measurements failed.
W9005 Derating value calculated using single Slew Rate measurement value.
W9006 Derating value cannot be computed since the calculated Slew Rate is not present in
the derating table †.
E9007 Derating Error *.
xxx

* Slew Rate measurements used to calculate the derated value failed to Run as there are no sufficient edges on the Rise and Fall slopes of
the waveform.

128 DDR Analysis

References Error Codes and Warnings

Base measurement limits are not defined as per the specification.

† Signal Slew Rate value is outside the derating table (Ex: If DDR2-800 MT/s tDS derating with a differential probe has a DQS differential slew rate of
0.65 V/ns, this warning message is displayed as the derating table definition starts from 0.8 V/ns).
Derating value is "not supported" (TBD) in the specification (Ex: If the DQS differential slew rate is 2.0 V/ns and the DQ slew rate is 0.7 V/ns, then
the value is "-"(TBD).
Derating will not be applied for the above cases and the base limit will be displayed in the results table.
‡ Displays the zone number (x) for which the preamble/postamble fails.
1 This error occurs during DPOJET installation on a DPO/MSO series of oscilloscopes. Delete the Installshield folder under C:\Program files\Common
Files and delete all files and folders under C:\Windows\Temp folder. Restart the installation again.

DDR Analysis 129

References Error Codes and Warnings

130 DDR Analysis

Algorithms About Algorithms

About Algorithms
The DDRA application can take measurements by selecting either Clock, Strobe, Data or CS Source as
sources. The number of waveforms used by the application depends on the type of measurement being
taken.

Oscilloscope Setup Guidelines

For all measurements, use the following guidelines to set up the oscilloscope:
The signal is any channel, reference, or math waveform.
The vertical scale for the waveform must be set so that the waveform does not exceed the vertical
range of the oscilloscope.
The sample rate must be set to capture sufficient waveform detail and avoid aliasing.
Longer record lengths increase measurement accuracy but the oscilloscope takes longer to measure
each waveform.

Search and Mark Algorithms

DDR search algorithms look for patterns in data (DQ) to determine start and end of bursts. All searches use
histogram analysis around edges found in the waveform, where edges are determined using the supplied
min/max/mid levels. These levels and the speed grade are configurable in the DDRA application's first and
fifth steps.
DDR search operates by scanning through both DQ and DQS and measuring peak to peak voltage and
mid-levels. The mid-level detected on DQS is then used with a 10% hysteresis band to extract the edges
from the DQS signal. These edges are stored and are then used for bit rate estimation.
All DDR searches use waveform shape expectations to determine start or stop of a Read and Write burst.
The application will scan for first the start of any burst, followed by that burst’s termination condition. Once
a start condition has been found, only the termination condition will be searched for until the end-of-record.

tDQSS
tDQSS is different from the tDQSS-Diff supported for other generations like DDR2, DDR3. tDQSS
measures the time taken from the WRITE event in the DDR bus to the first DQS latching transition.
This measurement has two sources. One bus source (B1) and a DQS source (analog). Additionally we
need a DQ source for DDR Write burst detection.
Measurement internally sets up a Bus search to look for WRITE events. For every WRITE event in the bus
search output, the algorithm finds and associates the first rising edge of DQS within the DDR Write burst.
This measurement is available only on 64-bit MSO instruments. Measurement gets selected only if
there is a bus source configured.

DDR Analysis 131

Algorithms Data Eye Width

Data Eye Width

Data Eye Width is common for both Read and Write bursts. The type of burst is determined by the ASM
settings. If a waveform contains multiple bursts of the same kind, the Data Eye Width is calculated and
respective Eye Diagram rendered for all bursts within one acquisition. It uses the DPOJET measurement,
Eye width with eye diagram plot enabled. Set DQ to Data signal and DQS to explicit clock edge.
By default, the DQS eye will be rendered under the DQ eye in an orange monochrome color. The DQS
eye can be turned off from the Eye diagram plot configuration panel. For Write bursts, the DQS eye is
offset from the Data eye (crossing in the center), whereas eye diagrams overlap for Read bursts. The
relative positions of the eye diagrams can be controlled using the Ref Clock alignment property on the Eye
diagram plot configuration panel. The left and center options indicate where the DQS crossing shall be
located so that Data Eye will maintain its normal position. Left is suitable for Read bursts and center for
Write bursts. Use Auto to automatically determine the offset property.
For more details, refer to the topic “Eye Width” of the DPOJET help.

132 DDR Analysis

Algorithms Data Eye Height

Data Eye Height

Data Eye Height is common for both Read and Write bursts. The type of burst is determined by the ASM
settings. If a waveform contains multiple bursts of the same kind, the Data Eye Height is calculated
and the Eye Diagram rendered for all bursts within one acquisition. Set DQ to Data signal and DQS
to explicit clock edge.
By default, the DQS eye will be rendered under the DQ eye in orange monochrome color. The DQS eye
can be turned off from the Eye diagram plot configuration panel. For Write bursts, the DQS eye is offset
from the Data eye (crossing in the center), whereas eye diagrams overlap for Read bursts. The relative
positions of the eye diagrams might be controlled using the Ref Clock alignment property on the Eye
diagram plot configuration panel. The left and center options indicate where the DQS crossing shall be
located so that Data Eye will maintain its normal position. Left is suitable for Read bursts and center for
Write bursts. Use Auto to automatically determine the offset property.

NOTE. When you select “Vertical Scale to Data” in the eye diagram plot configuration, it is possible
that the DQS signal can be clipped both at the top and bottom of the eye diagram. The Eye diagram is
enabled only when you select the Eye Width measurement along with Eye Height. The Eye diagram
plot is disabled when you select only Eye Height.

For more details, refer to the topic “Eye Height” of the DPOJET help.

DDR Analysis 133

Algorithms Input Slew-Diff-Rise(DQS)

Input Slew-Diff-Rise(DQS)
Input Slew-Diff-Rise(DQS) measures slew rate on differential DQS signals between the rising edges
from low to high.
Input Slew-Diff-Rise(DQS) uses the DPOJET measurement, Rise Slew Rate.

NOTE. The above figure is applicable for all DDR2 Slew Rate(Diff) measurements.

For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

Input Slew-Diff-Fall(DQS)
Input Slew-Diff-Fall(DQS) measures slew rate on differential DQS signals between the falling edges
from high to low.
Input Slew-Diff-Fall(DQS) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

134 DDR Analysis

Algorithms tDH-Diff(base)

tDH-Diff(base)
tDH-Diff(base) is defined as the input hold time between Data (DQ) and Differential Strobe (DQS) signal.
It is the elapsed time taken from the mid-level of the DQS signal to the specific level (VIH(dc) and
VIL(dc), where VIH(dc) is on a falling slope of DQ signal and VIL(ac) is on a rising slope of the DQ
signal). This measurement requires you to set up correct reference levels for DQS and DQ signals for
different speeds. The DDRA application will set up these levels automatically when “JEDEC Default”
mode is selected. When “User Defined” mode is selected, then these reference levels are calculated
based on your input for Vref and Vdd.
tDH-Diff(base) uses the DPOJET measurement, DDR-Hold-Diff.
For more details, refer to the topic “DDR-Hold-Diff” of the DPOJET help.

tDH-Diff(derated)
Derating limits are calculated by adding the tDH(base) limit and ΔtDH(derating) value. ΔtDH for a
rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of
VREF(dc), and for a falling signal is defined as the slew rate between the last crossing of VIH(dc) min and
the first crossing of VREF(dc).
tDH-Diff(derated) uses the DPOJET measurement, DDR-Hold-Diff, to calculate the base value.
For more details, refer to the topic “DDR-Hold-Diff” of the DPOJET help.

tDH-Diff(Vref-based)
tDH-Diff(Vref-based) is defined as the elapsed time from Vref of the DQS signal to the Vref of the DQ
signal. This is the only tDH measurement that does not use the Vih and Vil thresholds.
tDH-Diff(derated) uses the DPOJET measurement, Hold.
For more details, refer to the topic “Hold” of the DPOJET help.

tDS-Diff(base)
tDS-Diff(base) is defined as the input setup time between DQ and differential DQS signal. It is the elapsed
time taken from the mid-level of the DQS signal to the specific level (VIH(ac) and VIL(ac), where VIH(ac)
is on a falling slope of DQ signal and VIL(ac) is on a rising slope of the DQ signal).
tDS-Diff(base) uses the DPOJET measurement, DDR Setup-Diff.

DDR Analysis 135

Algorithms tDS-Diff(base)

For more details, refer to the topic “DDR-Setup-Diff” of the DPOJET help.

The configured values of Vdd and Vref are used to calculate VIH(ac)min VIH(dc)min, VIL(dc)max and VIL(ac)max,
which are applied on the input signal. These levels are further used for calculating Setup and Hold
measurements.

The relationship between Vdd and Vref for DDR2 standard is as shown in the following tables. For other
DDR standards, please refer to their JEDEC specifications.
Table 33: Input DC logic Level
Symbol Parameter Min Max Units
VIH(dc) DC input logic high Vref+0.125 – V
VIL(dc) DC input logic low –0.3 Vref–0.125 V
xxx

136 DDR Analysis

Algorithms tDS-Diff(derated)

Table 34: Input AC logic Level

DDR2–400, DDR2–533 DDR2–667,DDR2–800 Units
Symbol Parameter Min Max Min Max
VIH(ac) AC input Vref+0.250 x Vref+0.200 – V
logic high
VIL(ac) AC input – Vref–0.250 – Vref+0.200 V
logic low
xxx

tDS-Diff(derated)
Derating limits are calculated by adding the tDS(base) limit and ΔtDS(derating) value.. ΔtDS for a rising
signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min, and
for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of VIL(ac)max and the first crossing of VIL(ac)max.
tDS-Diff(derated) uses the DPOJET measurement, DDR-Setup-Diff, to calculate the base value.
For more details, refer to the topic “DDR-Setup-Diff” of the DPOJET help.

tDS-Diff(Vref-based)
tDS-Diff(Vref-based) is defined as the elapsed time from Vref of the DQ signal to the Vref of the DQS
signal. This is the only tDS measurement that does not use Vih and Vil thresholds.
tDS-Diff(Vref-based) uses the DPOJET measurement, Setup.
For more details, refer to the topic “Setup” of the DPOJET help.

DDR Analysis 137

Algorithms tDQSH

tDQSH
tDQSH is the high pulse width on the DQS(Strobe) input. Amount of time the waveform remains above
the mid reference voltage level.
tDQSH uses the DPOJET measurement, Pos Width.

For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

tDQSL
tDQSL is the low pulse width on the DQS(Strobe) input. Amount of time the waveform remains below the
mid reference voltage level.
tDQSL uses the DPOJET measurement, Neg Width.

For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

tDSS-Diff
tDSS-Diff is defined as the elapsed setup time from the DQS falling edge to the clock rising edge.
tDSS-Diff uses the DPOJET measurement, Setup.
For more details, refer to the topic “Setup” of the DPOJET help.

138 DDR Analysis

Algorithms tDSH-Diff

tDSH-Diff
tDSH-Diff is defined as the elapsed time from the clock rising edge to the DQS falling edge.
tDSH-Diff uses the DPOJET measurement, Hold.
For more details, refer to the topic “Hold” of the DPOJET help.

tDQSS-Diff
tDQSS-Diff is defined as the elapsed time from the DQS rising edge to the clock rising edge.
tDQSS-Diff uses the DPOJET measurement, Skew.
For more details, refer to the topic “Skew” of the DPOJET help.

Slew Rate-Hold-SE-Fall(DQS)
Slew Rate-Hold-SE-Fall(DQS) measures the slew rate on the DQS-SE signal between the falling edge
from VREF to VIL(ac)max.
Slew Rate-Hold-SE-Fall(DQS) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

Slew Rate-Hold-SE-Rise(DQS)
Slew Rate-Hold-SE-Rise(DQS) measures the slew rate on the DQS-SE signal between the rising edge
from VREF to VIH(ac)min.
Slew Rate-Hold-SE-Rise(DQS) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

Slew Rate-Setup-SE-Fall(DQS)
Slew Rate-Setup-SE-Fall(DQS) measures the slew rate on the DQS-SE signal between the falling edge
from VREF to VIL(ac)max.
Slew Rate-Setup-SE-Fall(DQS) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

DDR Analysis 139

Algorithms Slew Rate-Setup-SE-Rise(DQS)

Slew Rate-Setup-SE-Rise(DQS)
Slew Rate-Setup-SE-Rise(DQS) measures the slew rate on the DQS-SE signal between the rising edge
from VREF to VIH(ac)min.
Slew Rate-Setup-SE-Rise(DQS) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

tDS-SE(base)
tDS-SE(base) is the input setup time between DQ and single-ended DQS signal. It is the elapsed time
between VIH(dc)min of DQS and VIL(ac) max of DQ.
tDS-SE(base) uses the DPOJET measurement, DDR-Setup-SE.
For more details, refer to the topic “DDR-Setup-SE” of the DPOJET help.

tDIPW-SE
tDIPW-SE is defined as the input pulse width on the DQ or DBI# signal.
tDIPW-SE uses the DPOJET measurement, High Time.
For more details, refer to the topic “High Time” of the DPOJET help.

tDSS-SE
tDSS-SE is defined as the elapsed setup time from the DQS falling edge to the clock rising edge.
tDSS-SE uses the DPOJET measurement, Setup.
For more details, refer to the topic “Setup” of the DPOJET help.

tDSH-SE
tDSH-SE is defined as the elapsed time from the clock rising edge to the DQS falling edge.
tDSH-SE uses the DPOJET measurement, Hold.
For more details, refer to the topic “Hold” of the DPOJET help.

140 DDR Analysis

Algorithms tDQSS-SE

tDQSS-SE
tDQSS-SE is defined as the elapsed time from the DQS rising edge to the clock rising edge.
tDQSS-SE uses the DPOJET measurement, Skew.
For more details, refer to the topic “Skew” of the DPOJET help.

tDH-SE(base)
tDH-SE(base) is defined as the input hold time between DQ and single-ended DQS signal.
tDH-SE(base) uses the DPOJET measurement, DDR-Hold-SE.
For more details, refer to the topic “DDR-Hold-SE” of the DPOJET help.

tDVAC(CK)
tDVAC(CK) is defined as the allowed time before ring back of CK below VIDCK/WCK (AC) reference
levels.
tDVAC(CK) uses the DPOJET measurement, Time Outside Level. tDVAC(CK) is used for GDDR5
generation.
For more details, refer to the topic “Time Outside Level” of the DPOJET help.

DDR Analysis 141

Algorithms tWPRE

tWPRE
tWPRE is defined as the elapsed time on a DQS signal between tWPRE_begin and tWPRE_end. This
measurement is common for all DDR generation except DDR3.

tWPRE uses the DPOJET measurement, DDR tRPRE for DDR, DDR2, LPDDR and LPDDR2 generations.
For more details, refer to the topic “DDR tRPRE” of the DPOJET help.
For DDR3 generation, tWPRE is based on the DPOJET measurement, DDR tWPRE.
For more details, refer to the topic “DDR tWPRE” of the DPOJET help.

142 DDR Analysis

Algorithms tWPST

tWPST
tWPST is defined as the elapsed time between tWPST_begin and tWPST_end.

tWPST uses the DPOJET measurement, DDR tPST.

The application calculates this measurement using the following equation:
tWPST= t2(n)– t1(n)
For more details, refer to the topic “DDR tPST” of the DPOJET help.

tWRPDE
tWRPDE measures the elapsed time between the WRITE and POWERDOWN ENTRY commands.
This measurement is available for GDDR5 generation.
tWRPDE uses the DPOJET measurement, tBurstToCMD. This measurement will appear under WRITE
measurement type.
For more details, refer to the topic “tBurstToCMD” of the DPOJET help.

tWRSRE
tWRSRE measures the elapsed time between the WRITE and SELF REFRESH commands.. This
measurement is available for both DDR2 and DDR3 generation.
tWRSRE uses the DPOJET measurement, tBurstToCMD. This measurement will appear under WRITE
measurement type.
For more details, refer to the topic “tBurstToCMD” of the DPOJET help.

DDR Analysis 143

Algorithms tDQSCK-Diff

tDQSCK-Diff
tDQSCK-Diff is the DQS output access time from CK or CK#.
tDQSCK-Diff uses the DPOJET measurement, Skew.

The application calculates this measurement using the following equation:

for mid level

Where:
Tn specifies the clock edges.
TDQS(n) specifies the DQS edges.
The edge locations are determined by the mid-reference voltage levels. This is a skew measurement
between the rising edge of DQS and the rising edge of clock.
For more details, refer to the topic “Skew” of the DPOJET help.

NOTE. The JEDEC standard specifies that tDQSCK is the actual position of a rising strobe edge relative
to CK, CK#. Hence, DQS should be in phase with CK. When DQS and CK are not in phase, there could
be possibility of probe polarity interchange. You can overcome this by changing the edge direction to
“Opposite as From” under edges configure tab for Skew measurements.
For more details, refer to the topic “Configuring Edges for Skew Measurement” of the DPOJET help.

tDQSQ-Diff
tDQSQ-Diff is the DQS-DQ skew for DQS and associated DQ signals. Set JEDEC standard reference
levels for DQ.

144 DDR Analysis

Algorithms tAC-Diff

tDQSQ-Diff uses the DPOJET measurement, Setup.

For more details, refer to the topic “Setup” of the DPOJET help.

tAC-Diff
tAC-Diff is the DQ output access time from CK or CK#. Set DQ as the clock source and DQS as the
differential source. Set appropriate reference levels for DQ.
tAC-Diff uses the DPOJET measurement, DDR-Setup-Diff.
For more details, refer to the topic “DDR-Setup-Diff” of the DPOJET help.

tQH
tQH is the elapsed time between when the clock waveform crosses its own voltage reference level and the
designated edge of a data waveform.
tQH uses the DPOJET measurement, Hold.
For more details, refer to the topic “Hold” of the DPOJET help.

DDR Analysis 145

Algorithms SRQdiff-Rise(DQS)

SRQdiff-Rise(DQS)
SRQdiff-Rise(DQS) measures slew rate on differential DQS signals between the rising edges from low to
high.

SRQdiff-Rise(DQS) uses the DPOJET measurement, Rise Slew Rate.

NOTE. The above figure is applicable for all DDR3 Slew Rate(Diff) measurements.

For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

SRQdiff-Fall(DQS)
SRQdiff-Fall(DQS) measures slew rate on differential DQS signals between the falling edges from high
to low.
SRQdiff-Fall(DQS) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

146 DDR Analysis

Algorithms tDQSQ-SE

tDQSQ-SE
vtDQSQ-SE is the skew measured between DQS and DQ single-ended signals.
tDQSQ-SE uses the DPOJET measurement, Setup.
For more details, refer to the topic “Setup” of the DPOJET help.

tDQSCK-SE
tDQSCK-SE is the DQS output access time from CK or CK#. DQS is a single-ended source and special
reference levels (see page 115) are available. Clock is a differential source.
tDQSCK-SE uses the DPOJET measurement, Skew.

The application calculates this measurement using the following equation:

for mid level

Where:
Tn specifies the clock edges.
TDQS(n) specifies the DQS edges.
The edge locations are determined by the mid-reference voltage levels. This is a skew measurement
between the rising edge of DQS and the rising edge of clock.
For more details, refer to the topic “Skew” of the DPOJET help.

DDR Analysis 147

Algorithms DDR2-tDQSCK

DDR2-tDQSCK
tDQSCK is measured between the rising edge of clock before or after DQS Preamble time.
For more details, refer to the topic DDR2-tDQSCK of the DPOJET help.
In the following screen capture, only DQS edge is considered after preamble region for all the respective
( READ or WRITE ) bursts in the acquisitions.

SRQse-Fall(DQ)
SRQse-Fall(DQ) is defined as the single-ended output slew rate for falling edge and is measured between
VOL(AC) to VOH(AC).

The application calculates this measurement using the following equation:

148 DDR Analysis

Algorithms SRQse-Rise(DQ)

Where:
VOH(AC) is the AC output high measurement level for output slew rate.
VOL(AC) is the AC output low measurement level for output slew rate.

SRQse-Rise(DQ)
SRQse-Rise(DQ) is defined as the single-ended output slew rate for rising edge and is measured between
VOH(AC) to VOL(AC).

Where:
VOH(AC) is the AC output high measurement level for output slew rate.
VOL(AC) is the AC output low measurement level for output slew rate.
tRDPDE
tRDPDE measures the elapsed time between the READ and POWERDOWN ENTRY commands.
tRDPDE uses the DPOJET measurement, tBurstToCMD. This measurement will appear under READ
measurement type and available for GDDR5 generation only.
For more details, refer to the topic “tBurstToCMD” of the DPOJET help.

tRDSRE
tRDSRE measures the elapsed time between the READ and SELF REFERSH commands.
tRDSRE uses the DPOJET measurement, tBurstToCMD. This measurement will be available for GDDR5
generation only.
For more details, refer to the topic “tBurstToCMD” of the DPOJET help.

DDR Analysis 149

Algorithms tRPRE

tRPRE
DDR tRPRE is defined as the differential pulse width(DQS) for READ preamble.
tRPRE uses the DPOJET measurement, DDR tRPRE.
For more details, refer to the topic “DDR tRPRE” of the DPOJET help.

tRPST
tRPST is defined as the differential pulse width for READ preamble.
tRPST uses the DPOJET measurement, DDR tRPST.
For more details, refer to the topic “DDR tRPST” of the DPOJET help.

Slew Rate-Hold-Fall(DQ)
Slew Rate-Hold-Fall(DQ) measures the slew rate on the DQ signal between the falling edge from VREF to
VIL(ac)max. This measurement is available for both DDR2 and DDR3 generation.
Slew Rate-Hold-Fall(DQ) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

Slew Rate-Hold-Rise(DQ)
Slew Rate-Hold-Rise(DQ) measures the slew rate on the DQ signal between the rising edge from VREF to
VIH(ac)min. This measurement is available for both DDR2 and DDR3 generation.
Slew Rate-Hold-Rise(DQ) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

Slew Rate-Setup-Fall(DQ)
Slew Rate-Setup-Fall(DQ) measures the slew rate on the DQ signal between the falling edge from VREF to
VIL(ac)max. This measurement is available for both DDR2 and DDR3 generation.
Slew Rate-Setup-Fall(DQ) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

150 DDR Analysis

Algorithms Slew Rate-Setup-Rise(DQ)

Slew Rate-Setup-Rise(DQ)
Slew Rate-Setup-Rise(DQ) measures the slew rate on the DQ signal between the rising edge from VREF to
VIH(ac)min. This measurement is available for both DDR2 and DDR3 generation.
Slew Rate-Setup-Rise(DQ) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

SSC Downspread(CK)
SSC Downspread(CK) measures the SSC downspread for the clock.
SSC Downspread(CK) uses the DPOJET measurement, SSC-FREQ-DEV.
For more details, refer to the topic “SSC-FREQ-DEV” of the DPOJET help.

SSC Mod Freq(CK)

SSC Mod Freq(CK) measures the SSC modulation frequency for the clock.
SSC Mod Freq(CK) uses the DPOJET measurement, SSC-MOD-FREQ.
For more details, refer to the topic “SSC-MOD-FREQ” of the DPOJET help.

SSC Profile(CK)
SSC Profile(CK) measures the SSC profile.
SSC Profile(CK) uses the DPOJET measurement, SSC-PROFILE.
For more details, refer to the topic “SSC-PROFILE” of the DPOJET help.

tCH
tCH is the high pulse width on the clock signal. It is the amount of time the waveform remains above the
mid reference voltage level.
tCH uses the DPOJET measurement, Pos Width.
For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

DDR Analysis 151

Algorithms tCK

tCK
tCK is the absolute clock period. It is the elapsed time between consecutive rising crossings of the mid
reference CK voltage level.
tCK uses the DPOJET measurement, Period.
For more details, refer to the topic “Period” of the DPOJET help.

tCL
tCL is the low pulse width on the clock signal. It is the amount of time the waveform remains below the
mid reference voltage level.
tCL uses the DPOJET measurement, Neg Width.
For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

tCH(abs)
tCH(abs) is the high pulse width on the clock signal. It is the amount of time the waveform remains
above the mid reference voltage level.
tCH(abs) uses the DPOJET measurement, Pos Width.
For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

152 DDR Analysis

Algorithms tCH(avg)

tCH(avg)
tCH(avg) is the average width of the high-half cycle calculated across a sliding 200-cycle window
of clock cycles.
tCH(avg) uses the DPOJET measurement, DDR tCH(avg).

The application calculates this measurement using the following equation:

Where:
N=200, which is configurable.

tCK(abs)
tCK(abs)is the absolute clock period. It is the elapsed time between consecutive rising crossings of the mid
reference CK voltage level.
tCK(abs) uses the DPOJET measurement, Period.
For more details, refer to the topic “Period” of the DPOJET help.

tCK(avg)
tCK(avg) is calculated as the average clock period across a sliding 200-cycle window of low pulses.
tCK(avg) uses the DPOJET measurement, DDR tCK(avg).

The application calculates this measurement using the following equation:

Where:
N=200, which is configurable.
Range: 200≤N≤1M

DDR Analysis 153

Algorithms tCL(abs)

tCL(abs)
tCL(abs) is the low pulse width on the clock signal. It is the amount of time the waveform remains
below the mid reference voltage level.
tCL(abs) uses the DPOJET measurement, Neg Width.
For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

tCL(avg)
tCL(avg) is defined as the average low pulse width calculated across 200-cycle window of consecutive
low pulses.
tCL(avg) uses the DPOJET measurement, DDR tCL(avg).

The application calculates this measurement using the following equation:

Where:
N=200, which is configurable.
Range: 200≤N≤1M

tHP
tHP is the minimum of the absolute half period of the actual input clock. It is similar to DPOJET's Period
measurement where the edge type is clock with edges selection set to both. Only the minimum result
statistics will be compared with the limit values for PASS/FAIL status.

The application calculates this measurement using the following equation:

Where:
tCH(abs) is the minimum of the actual instantaneous clock high time.
tCL(abs) is the minimum of the actual instantaneous clock low time.

154 DDR Analysis

Algorithms tERR

tERR
tERR (Timing error) is the time difference between the sum of tCK transitions for a 200-cycle window to
n times tCK(avg). The calculated value represents the accumulated error across many cycles (n). The
number of cycles to be used is defined by n, which is configurable.

The application calculates this measurement using the following equation:

Where:
For tERR(nper):
n=2 for tERR(2 per)
n=3 for tERR(3 per)
n=4 for tERR(4 per)
n=5 for tERR(5 per)
n=6 for tERR(6 per)
.
.
.
.
n=49 for tERR(49 per)
For tERR(m-nper):
6 ≤ n ≤ 10 for tERR(6–10 per)
11 ≤ n ≤ 50 for tERR(11–50 per)
13 ≤ n ≤ 50 for tERR(13–50 per)

DDR Analysis 155

Algorithms tJIT(cc)

tJIT(cc)
tJIT(cc) is the difference in period measurements from one cycle to the next; that is, the first difference
of the Period measurement.
tJIT(cc) uses the DPOJET measurement, CC–Period.

The application calculates this measurement using the following equation:

tJIT(duty)
tJIT(duty) is the largest elapsed time between the tCH from tCH(avg) or tCL from tCL(avg) for a 200-cycle
window. This value represents the maximum of the accumulated value across a 200-cycle moving window.
tJIT(duty) uses the DPOJET measurement, DDR tJIT(duty).

The application calculates this measurement using the following equation:

Where:
tJIT(CH) = {tCHi- tCH(avg)}
tJIT(CL) = {tCLi- tCL(avg)}
Where:
i=1 to 200

156 DDR Analysis

Algorithms tJIT(per)

tJIT(per)
tJIT(per) is the largest elapsed time between the tCK from tCK(avg) for a 200-cycle window. This value
represents the maximum of the accumulated value across a 200-cycle moving window.
tJIT(per) uses the DPOJET measurement, DDR tJIT(per).

The application calculates this measurement using the following equation:

Where:
i=1 to 200

VID(ac)
VID(ac) is defined as the magnitude of the difference between the input voltage on CK and the input
voltage on CK#.
VID(ac) uses the DPOJET measurement, DDR VID(ac).
For more details, refer to the topic “DDR VID(ac)” of the DPOJET help.

Input Slew-Diff-Rise(CK)
Input Slew-Diff-Rise(CK) measures slew rate on differential CK signals between the rising edges from
low to high. The clock differential voltage varies from 500 mV to –250 mV.
Input Slew-Diff-Rise(CK) uses the DPOJET measurement, Rise Slew Rate.

NOTE. This measurements is common for both Clock(Diff) and Address/Command measurement types.

For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

DDR Analysis 157

Algorithms Input Slew-Diff-Fall(CK)

Input Slew-Diff-Fall(CK)
Input Slew-Diff-Fall(CK) measures slew rate on differential CK signals between falling edges from clock
high to low. The clock differential voltage varies from +500 mV to –250 mV.
Input Slew-Diff-Fall(CK) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

AC-Overshoot(CK#)
AC-Overshoot(CK#) is the positive-going amplitude, for each waveform event that exceeds the Vdd
reference level on the CK# signal.
AC-Overshoot(CK#) uses the DPOJET measurement, Overshoot.

NOTE. If the input waveform never exceeds Vdd, the measurement will return a population of 0 events.

For more details, refer to the topic “Overshoot” of the DPOJET help.

AC-Overshoot(CK)
AC-Overshoot(CK) is the positive-going amplitude, for each waveform event that exceeds the Vdd
reference level on the CK signal.
AC-Overshoot(CK) uses the DPOJET measurement, Overshoot.

NOTE. If the input waveform never exceeds Vdd, the measurement will return a population of 0 events.

For more details, refer to the topic “Overshoot” of the DPOJET help.

158 DDR Analysis

Algorithms AC-OvershootArea(CK#)

AC-OvershootArea(CK#)
AC-OvershootArea(CK#) is defined as the triangular area obtained by considering the voltage value
closest to the maximum peak point on the CK# signal. The triangular area is obtained using the Overshoot
width and the amplitude. The units for OvershootArea is V-ns.

AC-OvershootArea(CK#) uses the DPOJET measurement, DDR Over Area.

OvershootArea=0.5*Base*Height
Where:
Base is the overshoot width.
Height is the overshoot amplitude.
For more details, refer to the topic “DDR Over Area” of the DPOJET help.

DDR Analysis 159

Algorithms AC-OvershootArea(CK)

AC-OvershootArea(CK)
AC-OvershootArea(CK) is defined as the triangular area obtained by considering the voltage value closest
to the maximum peak point on the CK signal. The triangular area is obtained using the Overshoot width
and the amplitude. The units for OvershootArea is V-ns.

AC-OvershootArea(CK) uses the DPOJET measurement, DDR Over Area.

OvershootArea=0.5*Base*Height
Where:
Base is the overshoot width.
Height is the overshoot amplitude.
AC-Overshoot(CK) uses the DPOJET measurement, DDR Over Area.
For more details, refer to the topic “DDR Over Area” of the DPOJET help.

AC-Undershoot(CK#)
AC-Undershoot(CK#) is the negative-going amplitude (expressed as a positive number), for each
waveform event that goes below the Vss reference level on the CK# signal.
AC-Undershoot(CK#) uses the DPOJET measurement, Undershoot.

NOTE. If the input waveform never goes below Vss, the measurement will return a population of 0 events.

For more details, refer to the topic “Undershoot” of the DPOJET help.

160 DDR Analysis

Algorithms AC-Undershoot(CK)

AC-Undershoot(CK)
AC-Undershoot(CK) is the negative-going amplitude (expressed as a positive number), for each waveform
event that goes below the Vss reference level on the CK signal.
AC-Undershoot(CK) uses the DPOJET measurement, Undershoot.

NOTE. If the input waveform never goes below Vss, the measurement will return a population of 0 events.

For more details, refer to the topic “Undershoot” of the DPOJET help.

AC-UndershootArea(CK#)
AC-UndershootArea(CK#) is defined as the inverted triangular area obtained by considering the voltage
value closest to the maximum peak point on the CK# signal. The triangular area is obtained using the
undershoot width and the amplitude. The units for UndershootArea is V-ns.

AC-UndershootArea(CK#) uses the DPOJET measurement, DDR Under Area.

UndershootArea=0.5*Base*Height
Where:
Base is the undershoot width.
Height is the undershoot amplitude.
For more details, refer to the topic “DDR Under Area” of the DPOJET help.

DDR Analysis 161

Algorithms AC-UndershootArea(CK)

AC-UndershootArea(CK)
AC-UndershootArea(CK) is defined as the inverted triangular area obtained by considering the voltage
value closest to the maximum peak point on the CK signal. The triangular area is obtained using the
undershoot width and the amplitude. The units for UndershootArea is V-ns.

AC-UndershootArea(CK) uses the DPOJET measurement, DDR Under Area.

UndershootArea=0.5*Base*Height
Where:
Base is the undershoot width.
Height is the undershoot amplitude.
For more details, refer to the topic “DDR Under Area” of the DPOJET help.

CKslew-Fall(CK)
CKslew-Fall(CK) measures the single ended CD fall slew rate.
CKslew-Fall(CK) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

CKslew-Fall(CK#)
CKslew-Fall(CK#) measures the single ended CD fall slew rate.
CKslew-Fall(CK#) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

162 DDR Analysis

Algorithms CKslew-Rise(CK)

CKslew-Rise(CK)
CKslew-Rise(CK) measures the single ended CK rise slew rate.
CKslew-Rise(CK) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

CKslew-Rise(CK#)
CKslew-Rise(CK#) measures the single ended CK# rise slew rate.
CKslew-Rise(CK#) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

VIN(CK)
VIN(CK) measures the single ended CK clock input voltage level.
VIN(CK) uses the DPOJET measurement, High-Low.
For more details, refer to the topic “High-Low” of the DPOJET help.

VIN(CK#)
VIN(CK#) measures the single ended CK# clock input voltage level.
VIN(CK#) uses the DPOJET measurement, High-Low.
For more details, refer to the topic “High-Low” of the DPOJET help.

DDR Analysis 163

Algorithms Vix(ac)CK

Vix(ac)CK
Vix(ac)CK is defined as the cross-point voltage for differential input signals measured across the clock
signal.
Vix(ac)CK uses the DPOJET measurement, V–Diff–Xovr.
For more details, refer to the topic “V–Diff–Xovr” of the DPOJET help.
For DDR3 generation, the measurement uses DPOJET measurement, DDR3 Vix(ac).
For more details, refer to the topic “DDR3 Vix(ac)” of the DPOJET help.

Vox(ac)CK
Vox(ac)CK is defined as the cross-point voltage for differential input signals measured across the clock
signal.
Vox(ac)CK uses the DPOJET measurement, V–Diff–Xovr.
For more details, refer to the topic “V–Diff–Xovr” of the DPOJET help.

VSWING(MAX)CK#
VSWING(MAX)CK# is defined as the maximum input voltage on the clock signal (CK#). Available only
for DDR2 generation.

VSWING(MAX)CK# uses the DPOJET measurement, Cycle Pk-Pk.

For more details, refer to the topic “Cycle Pk-Pk” of the DPOJET help.

164 DDR Analysis

Algorithms VSWING(MAX)CK

VSWING(MAX)CK
VSWING(MAX)CK is defined as the maximum input voltage on the clock signal (CK). Available only
for DDR2 generation.
VSWING(MAX)CK uses the DPOJET measurement, Cycle Pk-Pk.
For more details, refer to the topic “Cycle Pk-Pk” of the DPOJET help.

VSEH(AC)CK
VSEH(AC)CK is defined as the single-ended high level voltage for the CK signal. Available only
for LPDDR2 and DDR3 generation.

NOTE. The same illustration is applicable for other measurements such as VSEH(AC)CK#,
VSEH(CK#),VSEH(CK),VSEL(AC)CK#, VSEL(AC)CK#, VSEL(AC)CK, VSEL(CK#), and VSEL(CK).

VSEH(AC)CK uses the DPOJET measurement, Cycle Max.

For more details, refer to the topic “Cycle Max” of the DPOJET help.

DDR Analysis 165

Algorithms VSEH(AC)CK#

VSEH(AC)CK#
VSEH(AC)CK# is defined as the single-ended high level voltage for the CK# signal. Available only
for LPDDR2 and DDR3 generation.
VSEH(AC)CK# uses the DPOJET measurement, Cycle Max.
For more details, refer to the topic “Cycle Max” of the DPOJET help.

VSEH(CK#)
VSEH(CK#) is defined as the single-ended high level voltage for the CK# signal. Available only for
DDR3 generation.
VSEH(CK#) uses the DPOJET measurement, Cycle Max.
For more details, refer to the topic “Cycle Max” of the DPOJET help.

VSEH(CK)
VSEH(CK) is defined as the single-ended high level voltage for the CK signal. Available only for DDR3
generation.
VSEH(CK) uses the DPOJET measurement, Cycle Max.
For more details, refer to the topic “Cycle Max” of the DPOJET help.

VSEL(AC)CK#
VSEL(AC)CK is defined as the single-ended low level voltage for the CK# signal. Available only for
LPDDR2 and DDR3 generation.
VSEL(AC)CK# uses the DPOJET measurement, Cycle Min.
For more details, refer to the topic “Cycle Min” of the DPOJET help.

166 DDR Analysis

Algorithms VSEL(AC)CK

VSEL(AC)CK
VSEL(AC)CK is defined as the single-ended low level voltage for the CK signal. Available only for
LPDDR2 and DDR3 generation.
VSEL(AC)CK uses the DPOJET measurement, Cycle Min.
For more details, refer to the topic “Cycle Min” of the DPOJET help.

VSEL(CK#)
VSEL(CK#) is defined as the single-ended low level voltage for the CK# signal. Available only for
DDR3 generation.
VSEH(CK) uses the DPOJET measurement, Cycle Min.
For more details, refer to the topic “Cycle Min” of the DPOJET help.

VSEL(CK)
VSEL(CK) is defined as the single-ended low level voltage for the CK signal. Available only for DDR3
generation.
VSEH(CK) uses the DPOJET measurement, Cycle Min.
For more details, refer to the topic “Cycle Min” of the DPOJET help.

DDR Analysis 167

Algorithms Vix(ac)DQS

Vix(ac)DQS
Vix(ac)DQS is defined as the cross-point voltage for differential input signals measured across the DQS
signal.
Vix(ac)DQS uses the DPOJET measurement, V–Diff–Xovr.
For more details, refer to the topic “V–Diff–Xovr” of the DPOJET help.
For DDR3 generation, the measurement uses DPOJET measurement, DDR3 Vix(ac).
For more details, refer to the topic “DDR3 Vix(ac)” of the DPOJET help.

Vox(ac)DQS
Vox(ac)DQS is defined as the cross-point voltage for differential input signals measured across the DQS
signal.
Vox(ac)DQS uses the DPOJET measurement, V–Diff–Xovr.
For more details, refer to the topic “V–Diff–Xovr” of the DPOJET help.

AC-Overshoot(DQS)
AC-Overshoot(DQS) is the positive-going amplitude, for each waveform event that exceeds the Vdd
reference voltage level on the DQS signal.
AC-Overshoot(DQS) uses the DPOJET measurement, Overshoot.

NOTE. If the input waveform never exceeds the specified reference level, the measurement will return a
population of 0 events.

For more details, refer to the topic “Overshoot” of the DPOJET help.

168 DDR Analysis

Algorithms AC-Overshoot(DQS#)

AC-Overshoot(DQS#)
AC-Overshoot(DQS#) is the positive-going amplitude, for each waveform event that exceeds the Vdd
reference level on the DQS# signal.
AC-Overshoot(DQS#) uses the DPOJET measurement, Overshoot.

NOTE. If the input waveform never exceeds the specified reference level, the measurement will return a
population of 0 events.

For more details, refer to the topic “Overshoot” of the DPOJET help.

AC-OvershootArea(DQS#)
AC-OvershootArea(DQS#) is defined as the triangular area obtained by considering the voltage value
closest to the maximum peak point on the DQS# signal. The triangular area is obtained using the overshoot
width and the amplitude. The units for OvershootArea is V-ns.

AC-OvershootArea(DQS#) uses the DPOJET measurement, DDR Over Area.

OvershootArea=0.5*Base*Height
Where:
Base is the overshoot width.
Height is the overshoot amplitude.
For more details, refer to the topic “DDR Over Area” of the DPOJET help.

DDR Analysis 169

Algorithms AC-OvershootArea(DQS)

AC-OvershootArea(DQS)
AC-OvershootArea(DQS) is defined as the triangular area obtained by considering the voltage value
closest to the maximum peak point on the CK# signal. The triangular area is obtained using the overshoot
width and the amplitude. The units for OvershootArea is V-ns.

AC-OvershootArea(DQS) uses the DPOJET measurement, DDR Over Area.

OvershootArea=0.5*Base*Height
Where:
Base is the overshoot width.
Height is the overshoot amplitude.
For more details, refer to the topic “DDR Over Area” of the DPOJET help.

AC-Undershoot(DQS)
AC-Undershoot(DQS) is the negative-going amplitude (expressed as a positive number), for each
waveform event that goes below the Vss reference level on the DQS signal.
AC-Undershoot(DQS) uses the DPOJET measurement, Undershoot.

NOTE. If the input waveform never goes below the specified reference level, the measurement will return a
population of 0 events.

For more details, refer to the topic “Undershoot” of the DPOJET help.

170 DDR Analysis

Algorithms AC-Undershoot(DQS#)

AC-Undershoot(DQS#)
AC-Undershoot(DQS#) is the negative-going amplitude (expressed as a positive number), for each
waveform event that goes below the reference level on the DQS# signal.
AC-Undershoot(DQS#) uses the DPOJET measurement, Undershoot.

NOTE. If the input waveform never goes below the specified reference level, the measurement will return a
population of 0 events.

For more details, refer to the topic “Undershoot” of the DPOJET help.

AC-UndershootArea(DQS#)
AC-UndershootArea(DQS#) is defined as the inverted triangular area obtained by considering the voltage
value closest to the maximum peak point on the DQS# signal. The triangular area is obtained using the
undershoot width and the amplitude. The units for UndershootArea is V-ns.

AC-UndershootArea(DQS#) uses the DPOJET measurement, DDR Under Area.

UndershootArea=0.5*Base*Height
Where:
Base is the undershoot width.
Height is the undershoot amplitude.
For more details, refer to the topic “DDR Under Area” of the DPOJET help.

DDR Analysis 171

Algorithms AC-UndershootArea(DQS)

AC-UndershootArea(DQS)
AC-UndershootArea(DQS) is defined as the inverted triangular area obtained by considering the voltage
value closest to the maximum peak point on the DQS signal. The triangular area is obtained using the
undershoot width and the amplitude. The units for UndershootArea is V-ns.

AC-UndershootArea(DQS) uses the DPOJET measurement, DDR Under Area.

UndershootArea=0.5*Base*Height
Where:
Base is the undershoot width.
Height is the undershoot amplitude.
For more details, refer to the topic “DDR Under Area” of the DPOJET help.

SSC Downspread(WCK)
SSC Downspread(WCK) measures the SSC downspread for WCK.
SSC Downspread(WCK) uses the DPOJET measurement, SSC-FREQ-DEV.
For more details, refer to the topic “SSC-FREQ-DEV” of the DPOJET help.

SSC Mod Freq(WCK)

SSC Mod Freq(WCK) measures the SSC modulation frequency for WCK.
SSC Mod Freq(WCK) uses the DPOJET measurement, SSC-MOD-FREQ.
For more details, refer to the topic “SSC-MOD-FREQ” of the DPOJET help.

172 DDR Analysis

Algorithms SSC Profile(WCK)

SSC Profile(WCK)
SSC Profile(WCK) measures the SSC profile.
SSC Profile(WCK) uses the DPOJET measurement, SSC-PROFILE.
For more details, refer to the topic “SSC-PROFILE” of the DPOJET help.

tDVAC(WCK)
tDVAC(WCK) is defined as the allowed time before ring back of WCK below VIDCK/WCK (AC)
reference levels.
tDVAC(WCK) uses the DPOJET measurement, Time Outside Level.
For more details, refer to the topic “Time Outside Level” of the DPOJET help.tDVAC(WCK) is used
for GDDR5 generation.

tWCK
tWCK measures the WCK clock cycle time.
tWCK uses the DPOJET measurement, Period.
For more details, refer to the topic “Period” of the DPOJET help.

tWCK-DJ
tWCK-DJ is defined as the WCK diff deterministic jitter.
tWCK-DJ uses the DPOJET measurement, DJ.
For more details, refer to the topic “DJ” of the DPOJET help.

tWCKH
tWCKH measures the WCK clock high-level width.
tWCKH uses the DPOJET measurement, Positive and Negative Width.
For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

DDR Analysis 173

Algorithms tWCKHP

tWCKHP
tWCKHP measures the minimum WCK clock half period.
tWCKHP uses the DPOJET measurement, Period.
For more details, refer to the topic “Period” of the DPOJET help.

tWCKL
tWCKL measures the WCK clock low-level width.
tWCKL uses the DPOJET measurement, Positive and Negative Width.
For more details, refer to the topic “Positive and Negative Width” of the DPOJET help.

tWCK-Rise-Slew
tWCK-Rise-Slew measures the WCK diff rise slew rate.
tWCK-Rise-Slew uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

tWCK-Fall-Slew
tWCK-Fall-Slew measures the WCK diff fall slew rate.
tWCK-Fall-Slew uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

tWCK-RJ
tWCK-RJ is defined as the WCK diff random jitter.
tWCK-RJ uses the DPOJET measurement, RJ.
For more details, refer to the topic “RJ” of the DPOJET help.

174 DDR Analysis

Algorithms tWCK-TJ

tWCK-TJ
tWCK-TJ is defined as the WCK diff total jitter.
tWCK-TJ uses the DPOJET measurement, TJ@BER.
For more details, refer to the topic “TJ@BER” of the DPOJET help.

VWCK-Swing
VWCK-Swing is defined as the WCK differential logic high voltage.
VWCK-Swing uses the DPOJET measurement, High-Low.
For more details, refer to the topic “High-Low” of the DPOJET help.

VIN(WCK)
VIN(WCK) measures the single ended WCK clock input voltage level.
VIN(WCK) uses the DPOJET measurement, High-Low.
For more details, refer to the topic “High-Low” of the DPOJET help.

VIN(WCK#)
VIN(WCK#) measures the single ended WCK clock input voltage level.
VIN(WCK#) uses the DPOJET measurement, High-Low.
For more details, refer to the topic “High-Low” of the DPOJET help.

DDR Analysis 175

Algorithms Vix(ac)WCK

Vix(ac)WCK
Vix(ac)WCK is defined as the cross-point voltage for differential input signals measured across the clock
signal.
Vix(ac)WCK uses the DPOJET measurement, V–Diff–Xovr.
For more details, refer to the topic “V–Diff–Xovr” of the DPOJET help.
For DDR3 generation, the measurement uses DPOJET measurement, DDR3 Vix(ac).
For more details, refer to the topic “DDR3 Vix(ac)” of the DPOJET help.

VOL(WCK)
VOL(WCK) measures the single ended logic low voltage of the WCK signal.
VOL(WCK) uses the DPOJET measurement, Low.
For more details, refer to the topic “Low” of the DPOJET help.

VOH(WCK)
VOH(WCK) measures the single ended logic high voltage of the WCK signal.
VOH(WCK) uses the DPOJET measurement, High.
For more details, refer to the topic “High” of the DPOJET help.

VOL(WCK#)
VOL measures the single ended logic low voltage of the WCK# signal.
VOL uses the DPOJET measurement, Low.
For more details, refer to the topic “Low” of the DPOJET help.

176 DDR Analysis

Algorithms VOH(WCK#)

VOH(WCK#)
VOH measures the single ended logic high voltage of the WCK# signal.
VOH uses the DPOJET measurement, High.
For more details, refer to the topic “High” of the DPOJET help.

WCKslew-Fall(WCK)
WCKslew-Fall(CK) measures the single ended WCK fall slew rate.
WCKslew-Fall(WCK) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

WCKslew-Fall(WCK#)
WCKslew-Fall(WCK#) measures the single ended WCK# fall slew rate.
WCKslew-Fall(WCK#) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

WCKslew-Rise(WCK)
WCKslew-Rise(WCK) measures the single ended WCK rise slew rate.
WCKslew-Rise(WCK) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

WCKslew-Rise(WCK#)
WCKslew-Rise(WCK#) measures the single ended WCK rise slew rate.
WCKslew-Rise(WCK#) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

DDR Analysis 177

Algorithms AC-Overshoot

AC-Overshoot
AC-Overshoot is the maximum positive-going amplitude relative to Vdd, for each waveform event that
exceeds the Vdd reference voltage level.

AC-Overshoot uses the DPOJET measurement, Overshoot.

AC-OvershootArea
AC-OvershootArea is defined as the triangular area obtained by considering the voltage value closest to
the maximum peak point. The triangular area is obtained using the overshoot width and the amplitude.
The units for OvershootArea is V-ns.

AC-OvershootArea uses the DPOJET measurement, DDR Over Area.

OverShoot Area=0.5*Base*Height
Where:
Base is the overshoot width.
Height is theovershoot amplitude.
For more details, refer to the topic “DDR Over Area” of the DPOJET help.

178 DDR Analysis

Algorithms AC-Undershoot

AC-Undershoot
AC-Undershoot is the negative-going amplitude (expressed as a positive number) relative to Vss, for each
waveform event that goes below the Vss reference voltage level.

AC-Undershoot uses the DPOJET measurement, Undershoot.

AC-UndershootArea
AC-UndershootArea is defined as the inverted triangular area obtained by considering the voltage value
closest to the maximum peak point. The triangular area is obtained using the undershoot width and the
amplitude. The units for UndershootArea is V-ns.

AC-UndershootArea uses the DPOJET measurement, DDR UnderArea.

The application calculates this measurement using the following equation:
UnderShoot Area=0.5*Base*Height
Where:
Base is the undershoot width.
Height is the undershoot amplitude.
For more details, refer to the topic “DDR Under Area” of the DPOJET help.

DDR Analysis 179

Algorithms Slew Rate-Hold-Fall(Addr/Cmd)

Slew Rate-Hold-Fall(Addr/Cmd)
Slew Rate-Hold-Fall(Addr/Cmd) measures the slew rate on the Addr/Cmd signal between the falling edge
from VREF to VIL(ac)max. This measurement is available for DDR2, DDR3, and LPDDR2 generation.
Slew Rate-Hold-Fall(Addr/Cmd) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.
Slew Rate-Hold-Fall(DQ) measures the slew rate on the DQ signal between the falling edge from VREF to
VIL(ac)max. This measurement is available for both DDR2 and DDR3 generation.

Slew Rate-Hold-Rise(Addr/Cmd)
Slew Rate-Hold-Rise(Addr/Cmd) measures the slew rate on the Addr/Cmd signal between the rising edge
from VREF to VIH(ac)min. This measurement is available for DDR2, DDR3, and LPDDR2 generation.
Slew Rate-Hold-Rise(Addr/Cmd) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

Slew Rate-Setup-Fall(Addr/Cmd)
Slew Rate-Setup-Fall(Addr/Cmd) measures the slew rate on the Addr/Cmd signal between the falling edge
from VREF to VIL(ac)max. This measurement is available for DDR2, DDR3, and LPDDR2 generation.
Slew Rate-Setup-Fall(Addr/Cmd) uses the DPOJET measurement, Fall Slew Rate.
For more details, refer to the topic “Fall Slew Rate” of the DPOJET help.

Slew Rate-Setup-Rise(Addr/Cmd)
Slew Rate-Setup-Rise(Addr/Cmd) measures the slew rate on the Addr/Cmd signal between the rising edge
from VREF to VIH(ac)min. This measurement is available for DDR2, DDR3, and LPDDR2 generation.
Slew Rate-Setup-Rise(Addr/Cmd) uses the DPOJET measurement, Rise Slew Rate.
For more details, refer to the topic “Rise Slew Rate” of the DPOJET help.

180 DDR Analysis

Algorithms tAH

tAH
tAH measures the address input hold time.
tAH uses the DPOJET measurement, Hold.
For more details, refer to the topic “Hold” of the DPOJET help.

tAPW
tAPW measures the address input pulse width.
tAPW uses the DPOJET measurement, Period.
For more details, refer to the topic “Period” of the DPOJET help.

tAS
tAS measures the address input setup time.
tAS uses the DPOJET measurement, Setup.
For more details, refer to the topic “Setup” of the DPOJET help.

tCMDH
tCMDH measures the command input hold time.
tCMDH uses the DPOJET measurement, Hold.
For more details, refer to the topic “Hold” of the DPOJET help.

tCMDPW
tCMDPW measures the command input pulse width.
tCMDPW uses the DPOJET measurement, Period.
For more details, refer to the topic “Period” of the DPOJET help.

DDR Analysis 181

Algorithms tCMDS

tCMDS
tCMDS measures the command input setup time.
tCMDS uses the DPOJET measurement, Setup.
For more details, refer to the topic “Setup” of the DPOJET help.

tIS(base)
tIS(base) is the input setup time measured on an address and command signal to the clock signal.
tIS(base) uses the DPOJET measurement, DDR Setup-Diff.
For more details, refer to the topic “DDR-Setup-Diff” of the DPOJET help.

tIH(base)
tIH(base) is the input hold time measured on an address and command signal to the clock signal.
tIH(base) uses the DPOJET measurement, DDR Hold-Diff.
For more details, refer to the topic “DDR Hold-Diff” of the DPOJET help.

tIS(derated)
Derating limits are calculated by adding the tIS(base) limit and ΔtIS(derating) value. ΔtIS for a rising
signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min,
and for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of Vil(ac)max.
tIS(derated) uses the DPOJET measurement, DDR Setup-Diff.
tIS= tIS(base)+ΔtIS
For more details, refer to the topic “DDR-Setup-Diff” of the DPOJET help.

182 DDR Analysis

Algorithms tIH(derated)

tIH(derated)
Derating limits are calculated by adding the tIH(base) limit and ΔtIH(derating) value. ΔtIH for a rising
signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc),
and for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first
crossing of VREF(dc).
tIH(derated) uses the DPOJET measurement, DDR Hold-Diff.
For more details, refer to the topic “DDR-Hold-Diff” of the DPOJET help.

tIPW-High
tIPW-High is the high input pulse width measured on an address and command signal.
tIPW-High uses the DPOJET measurement, High Time.
For more details, refer to the topic “High Time” of the DPOJET help.

tIPW-Low
tIPW-Low is the low input pulse width measured on an address and command signal.
tIPW-Low uses the DPOJET measurement, Low Time.
For more details, refer to the topic “Low Time” of the DPOJET help.

tCKSRE
tCKSRE measures the valid CK clocks required before self refresh exit.
tCKSRE uses the DPOJET measurement, tCKSRE.
For more details, refer to the topic “tCKSRE” of the DPOJET help.

tCKSRX
tCKSRX measures the valid CK clocks required before self refresh exit.
tCKSRX uses the DPOJET measurement, tCKSRX.
For more details, refer to the topic “tCKSRX” of the DPOJET help.

DDR Analysis 183

Algorithms tRFC

tRFC
tRFC measures the refresh command period.
tRFC uses the DPOJET measurement, tCMD-CMD.
For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

tREFTR(Read)
tREFTR(Read) measures the refresh to RDTR command delay.
tREFTR(Read) uses the DPOJET measurement, tCMD-CMD.
For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

tREFTR(Write)
tREFTR(Write) measures the refresh to WRTR command delay.
tREFTR(Write) uses the DPOJET measurement, tCMD-CMD.
For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

tXSNRW
tXSNRW measures the exit self refresh to non-read.write command delay.
tXSNRW uses the DPOJET measurement, tCMD-CMD.
For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

tPD
tPD measures the minimum power-down entry to exit time.
tPD uses the DPOJET measurement, tCMD-CMD.

184 DDR Analysis

Algorithms tRAS

For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

tRAS
tRAS measures the time elapsed from the ACTIVE to PRECHARGE command. This measurement is
available for the GDDR5 generation only.

tRAS uses the DPOJET measurement, tCMDtoCMD.

For more details, refer to the topic “tCMDtoCMD” of the DPOJET help.

tRC
tRC measures the time elapsed from the ACTIVE to ACTIVE command. This measurement is available
for GDDR5 generation only.

tRC uses the DPOJET measurement, tCMDtoCMD.

For more details, refer to the topic “tCMDtoCMD” of the DPOJET help.

DDR Analysis 185

Algorithms tRCDRD

tRCDRD
tRCDRD measures the time elapsed between the ACTIVE and READ commands. This measurement is
available for GDDR5 generation only.

tRCDRD uses the DPOJET measurement, tCMDtoCMD.

For more details, refer to the topic “tCMDtoCMD” of the DPOJET help.

tRCDWR
tRCDWR measures the time elapsed between the ACTIVE and WRITE commands. This measurement is
available for GDDR5 generation only.

tRCDWR uses the DPOJET measurement, tCMDtoCMD.

For more details, refer to the topic “tCMDtoCMD” of the DPOJET help.

186 DDR Analysis

Algorithms tPPD

tPPD
tPPD measures the elapsed time between the PRECHARGE and next PRECHARGE commands.

tPPD uses the DPOJET measurement, tCMDtoCMD. This measurement will be available for GDDR5
generation only.
For more details, refer to the topic “tCMDtoCMD” of the DPOJET help.

tRP(ACT)
tRP(ACT) measures the PRECHARGE command period from PRECHARGE to ACTIVE commands..

tRP(ACT) uses the DPOJET measurement, tCMDtoCMD. This measurement will be available for
GDDR5 generation only.
For more details, refer to the topic “tCMDtoCMD” of the DPOJET help.

DDR Analysis 187

Algorithms tRP(MRS)

tRP(MRS)
tRP(MRS) measures the PRECHARGE command period from PRECHARGE to MRS (Mode Register
Set) commands.
tRP(MRS) uses the DPOJET measurement, tCMDtoCMD. This measurement will be available for
GDDR5 generation only.
For more details, refer to the topic “tCMDtoCMD” of the DPOJET help.

tRP(REF)
tRP(REF) measures the precharge command period.
tRP(REF) uses the DPOJET measurement, tCMD-CMD.
For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

tRP(SRE)
tRP(SRE) measures the PRECHARGE command period from PRECHARGE to SELF REFRESH.
tRP(SRE) uses the DPOJET measurement, tCMD-CMD.
For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

tRTPL
tRTPL measures the READ to PRECHARGE command delay same bank with bank groups enabled.
tRTPL uses the DPOJET measurement, tCMD-CMD.
For more details, refer to the topic “tCMD-CMD” of the DPOJET help.

188 DDR Analysis

GPIB Commands About the GPIB Program

About the GPIB Program

You can use remote GPIB commands to communicate with the DDRA application. Query measurement
results using DPOJET commands. Sequence commands using DPOJET commands. Setup reports,
logging, statistics, and limits using DPOJET commands. An example of a GPIB program is included with
the DPOJET application in C:\Users\Public\Tektronix\TekApplications\DPOJET\Examples.
The example shows how a GPIB program executes the DPOJET application to do the following tasks:
1. Start the application.
2. Recall a setup.
3. Take a measurement.
4. View measurement results and plots.
5. Exit the application.

NOTE. Commands are not case and space sensitive. Your program will operate correctly even if you do
not follow the capitalization and spacing precisely.

GPIB Reference Materials

To use GPIB commands with your oscilloscope, you can refer to the following materials:
The GPIB Program Example in C:\TekApplications\DPOJET\Examples for guidelines to use
while designing a GPIB program.
The Parameters topics for range of values, minimum units and default values of parameters.
The programmer information in the online help of your oscilloscope.

DDR Analysis 189

GPIB Commands Argument Types

Argument Types
The syntax shows the format that the instrument returns in response to a query. This is also the preferred
format when sending the command to the instrument though any of the formats are accepted. This
documentation represents these arguments as follows:

Table 35: Argument types

Symbol Meaning
<NR1> Signed integer value.
<NR2> Floating point value without an exponent.
<NR3> Floating point value with an exponent.
double Double precision floating point with exponent.
xxx

DDRA:ADDMeas
This command selects the specified measurement in DDRA.

NOTE. If there is an error, the DDRA:LASTError? query returns measurement does not exist under the
generation or measurement type selected

Syntax
DDRA:ADDMeas {TCKABS | TCHABS | TCLABS | THP | TJITDUTY | TJITPER | TJITCC
| VIDAC | SRQDIFFRISEDQS | SRQDIFFFALLDQS | SRQDIFFRISECK | SRQSERISEDQ |
SRQSEFALLDQ | SRQDIFFFALLCK | INPUTSLEWDIFFRISEDQS | INPUTSLEWDIFFFALLDQS
| INPUTSLEWDIFFRISECK | INPUTSLEWDIFFFALLCK | TQH | TISBASE | TISDERATED |
TIHBASE | TIHDERATED | TDQSCK | TDQSCKDIFF | TDSSSE | TDSSDIFF | TDSHSE |
TDSHDIFF | TDQSSSE | TDQSSDIFF | TIPWHIGH | TIPWLOW | TDIPWSE | TDHSEBASE
| TDHSEDERATED | TDSSEBASE | TDSSEDERATED | TDSDIFFBASE | TDSDIFFDERATED
| TDHDIFFBASE | TDHDIFFDERATED | TDQSQSE | TDQSQDIFF | TACDIFF | TDQSH
| TDQSL | TCKAVG | TCLAVG | TCHAVG | TERR2PER | TERR3PER | TERR4PER |
TERR5PER | TERR6TO10PER | TERR11TO50PER | DATAEYEWIDTH | VIXACDQS | VIXACCK
| VIXACWCK | VOXACDQS | VOXACCK | ACOVRSHOOT | ACUNDSHOOT | ACOVRSHOOTDQS
| ACOVRSHOOTDQSBAR | ACUNDSHOOTC | ACOVRSHOOTCKBAR | ACUNDSHOOTDQS |
ACUNDSHOOTDQSBAR | ACUNDSHOOTCK | ACUNDSHOOTCKBAR | SETUPFALLADDRCMD |
SETUPRISEADDRCMD | SLEWFALLCK | SLEWRISECK | HOLDFALLADDRCMD | HOLDRISEADDRCMD
| SETUPFALLDQ | SETUPRISEDQ | SLEWSETUPFALLDQ | SLEWSETUPRISEDQ |
SLEWSETUPSEFALLDQS | SLEWSETUPSERISEDQS | SLEWDIFFFALLDQS | SLEWDIFFRISEDQS |
HOLDFALLDQ | HOLDRISEDQ | SLEHOLDFALLDQ | SLEWHOLDRISEDQ | SLEWHOLDSEFALLDQS
| SLEWHOLDSERISEDQS | SETUPSEFALLDQ | SETUPSERISEDQ | HOLDSEFALLDQ |
HOLDSERISEDQ | SLEWSEFALLDQS | SLEWSERISEDQS | TERR6PER | TERR7PER | TERR8PER

190 DDR Analysis

GPIB Commands DDRA:ADDMeas

| TERR9PER | TERR10PER | TERR11PER | TERR12PER | TERR13PER | TERR14PER |

TERR15PER | TERR16PER | TERR17PER | TERR18PER | TERR19PER | TERR20PER |
TERR21PER | TERR22PER | TERR23PER | TERR24PER | TERR25PER | TERR26PER |
TERR27PER | TERR28PER | TERR29PER | TERR30PER | TERR31PER | TERR32PER |
TERR33PER | TERR34PER | TERR35PER | TERR36PER | TERR37PER | TERR38PER |
TERR39PER | TERR40PER | TERR41PER | TERR42PER | TERR43PER | TERR44PER |
TERR45PER | TERR46PER | TERR47PER | TERR48PER | TERR49PER | TERR50PER | TCK
| TH | TCL | TDSSE | TDHSE | TRPRE | TWPRE | TWPST | TRPST | VSWINGMAXDQS |
VSWINGMAXDQSBAR | VSWINGMAXCK | VSWINGMAXCKBAR | DATAEYEHEIGHT | VSEHDQS |
VSEHDQSBAR | VSEHCK | VSEHCKBAR | VSELDQS | VSELDQSBAR | VSELCK | VSELCKBAR |
VSEHACDQ| VSEHACDQSBAR | VSEHACCK | VSEHACCKBAR | VSELACDQS | VSELACDQSBAR
| VSELACCK | VSELACCKBAR | SLEWHOLDFALLADDRCMD | SLEWHOLDRISEADDRCMD
| SLEWSETUPFALLADDRCMD | SLEWSETUPRISEADDRCMD | ACOVRSHOOTAREACKBAR |
ACOVRSHOOTAREACK | ACOVRSHOOTAREADQSBAR | ACOVRSHOOTAREADQS | ACOVRSHOOTAREA
| ACUNDSOOTAREACKBAR | ACUNDSHOOTAREACK | CKSLEWRISECK | CKSLEWFALLCK |
CKSLEWRISECKBAR | CKSLEWFALLCKBAR | ACUNDSHOOTAREADQSBAR | ACUNDSHOOTAREADQS
| ACUNDSHOOTAREA | TDSDIFFVREFBASED | TDHDIFFVREFBASED | VINCK | VINCKBAR
| VINWCK | VINWCKBAR | TCMDS | TCMDH | TAS | TAH | TCMDPW | TAPW |
WCKSLEWRISEWCK | WCKSLEWRISEWCKBAR | WCKSLEWFALLWCL | WCKSLEWFALLWCKBAR |
TWCK | TWCKHP | TWCKL | TWCKH | TDVACWCK | SSCDOWNSPREADWCK | SSCMODFREQWCK |
TDVACCCK | SSCDOWNSPREADCK | SSCMIDFREQCK | SSCPROVILECK | SSCPROVILEWCK | TRC
| TRAS | TRCDRD | TRCDWR | TRTPL | TPPD | TRPREF | TRPSRE | TRPMRS | TRPACT
| TRFC | TCKSRE | TCKSRX | TXSNRW | TREFTRWRITE | TREFTRREAD | TPD | TWRSRE
| TWRPDE | TRDSRE | TRDPDE | VMAXAC | VMINAC | TDQRISESLEW | TDQFALLSLEW |
TDQQTJ | TDQDJ | TDQRJ | VDQVOH | VDQVOL | TDQHP | TWCKRISESLEW | TWCKFALLSLEW
| TWCKTJ | TWCKDJ | TWCKRJ | VOHWCK | VOHWCKBAR | VOLWCK | VOLWCKBAR |
VWCKSWING | VIXDQ | VIXCA | ACOVRSHOOTAREADQ | ACUNDSHOOTAREADQ | ACOVRSHOOTDQ
| ACUNDSHOOTDQ | TDVACDQS | TDVACDQSBAR | TDVACDQ | TDVACADDRCMD | TRP |
TDQSS | TDVACADDRCMD | TRP | TDQSS | TDIPWHigh | TDIPWLow | VIHLAC | SRINRise
| SRINFall | TQSH | TQSL | TIPWHIGHCA | TIPWLOWCA | TIPWHIGHCS | TIPWLOWCS
| TISDERATEDCS | TISDERATEDCA | TISBASECS | TISBASECA | TIHDERATEDCS |
TIHDERATEDCA | TIHBASECS | TIHBASECA | TLZDQ | THZDQ | TLZDQS | THZDQS | TWR |
TWTR | TCCDRD | TCCDWR | DDRARXMASK | TRTP | CLOCKEYEWIDTH | CLOCKEYEDIAGRAM}

Inputs
See syntax for measurement options.

Outputs
None

DDR Analysis 191

GPIB Commands DDRA:ADDALLDiffdqs

DDRA:ADDALLDiffdqs
This command adds all the measurements listed under the differential DQS node.

NOTE. If there is an error, the DDRA:LASTError? query returns measurement group does not exist
under the generation or measurement type selected.

Syntax
DDRA:ADDALLDiffdqs

Inputs
None

Outputs
None

DDRA:ADDALLSEdqs
This command adds all the measurements listed under the Single-Ended DQS node.

NOTE. If there is an error, the DDRA:LASTError? query returns measurement group does not exist
under the generation or measurement type selected.

Syntax
DDRA:ADDALLSEdqs

Inputs
None

Outputs
None

192 DDR Analysis

GPIB Commands DDRA:ADDALLSLewdq

DDRA:ADDALLSLewdq
This command adds all the measurements listed under the Slew-Rate DQ node.

NOTE. If there is an error, the DDRA:LASTError? query returns measurement group does not exist
under the generation or measurement type selected.

Syntax
DDRA:ADDALLSLewdq

Inputs
None

Outputs
None

DDRA:ADDALLTerr
This command adds all the measurements listed under the Terr node.

NOTE. If there is an error, the DDRA:LASTError? query returns measurement group does not exist
under the generation or measurement type selected.

Syntax
DDRA:ADDALLTerr

Inputs
None

Outputs
None

DDR Analysis 193

GPIB Commands DDRA:CLEARALLMeas

DDRA:CLEARALLMeas
This command clears the entire list of defined measurements in DDRA.

Syntax
DDRA:CLEARALLMeas

Inputs
None

Outputs
None

DDRA:LASTError?
This query command returns a string containing the last DDRA error. If no errors have occurred since
startup or since the last call to :DDRA:LASTError?, this command returns an empty string.

Syntax
DDRA:HORizontalscaling?

Inputs
None

Outputs
String containing the last error.

194 DDR Analysis

GPIB Commands DDRA:GENeration

DDRA:GENeration
This command sets or queries the standard DDR generation.

Syntax
DDRA:GENeration {DDR | DDR2 | DDR3 | DDR3L | DDR4 | LPDDR | LPDDR2 | LPDDR3
| GDDR3 | GDDR5}

DDRA:GENeration?

Inputs
{DDR | DDR2 | DDR3 | DDR3L | DDR4 | LPDDR | LPDDR2 | LPDDR3 | GDDR3 | GDDR5}

Outputs
{DDR | DDR2 | DDR3 | DDR3L | DDR4 | LPDDR | LPDDR2 | LPDDR3 | GDDR3 | GDDR5}

DDR Analysis 195

GPIB Commands DDRA:DATARate

DDRA:DATARate
This command sets or queries the standard data rate for a particular DDR generation.

NOTE. If there is an error, the DDRA:LASTError? query returns invalid data rate value, for the generation
selected.

Syntax
DDRA:DATARate {”200” | “266” | “333” | “400” | “533” | “667” | “800” | “933” |
“1066” | “1333” | “1466” | “1600” | “1866” | “2133” | “2400” | “2666” | “3200”
| “370” | “500” | “600” | “700” | “800” | “900” | “1000” | “4000” | “4800” |
“5000” | “5500” | “CUSTOM”}

DDRA:DATARate?

Inputs
String.

Outputs
The current data rate. A query for DDRA:LASTError returns Invalid data rate value, for the generation
selected.

196 DDR Analysis

GPIB Commands DDRA:CUSTOMRate

DDRA:CUSTOMRate
This command sets or queries the custom data rate for a particular DDR generation.

NOTE. If there is an error, the DDRA:LASTError? query returns set the data rate to custom.

Syntax
DDRA:CUSTOMRate <NR3>

DDRA:CUSTOMRate?

Inputs
<NR3>

Outputs
<NR3>

DDR Analysis 197

GPIB Commands DDRA:MEASType

DDRA:MEASType
This command sets or queries the measurement type for a particular DDR generation.

Syntax
DDRA:MEASType {WRITEbursts | READbursts | CKDiff | CKSE | DQSSE | ADDRCMD |
WCKDiff | WCKSE | REFResh | PRECHArge | POWERDown | ACTive | DQSSERead}

DPOJET:MEASType?

Inputs
{WRITEbursts | READbursts | CKDiff | CKSE | DQSSE | ADDRCMD | WCKDiff | WCKSE
| REFResh | PRECHArge | POWERDown | ACTive | DQSSERead}

Outputs
The selected measurement type.

DDRA:VDDMode
This command sets or queries the VDD mode for a particular DDR generation.

Syntax
DDRA:VDDMode {JEDec | Manual}

DDRA:VDDMode?

Inputs
{JEDec | Manual}

Outputs
The currently selected VDD mode {JEDec | Manual}.

198 DDR Analysis

GPIB Commands DDRA:VDD

DDRA:VDD
This command sets or queries the user-defined VDD value for a particular DDR generation.

NOTE. If there is an error, the DDRA:LASTError? query returns select user defined mode to configure
Vdd/Vref value.

Syntax
DDRA:VDD <NR3>

DDRA:VDD?

Inputs
<NR3>

Outputs
<NR3>

DDRA:VREFMode
This command sets or queries the Vref mode for a particular DDR generation.

Syntax
DDRA:VREFMode {JEDec | Manual}

DDRA:VREFMode?

Inputs
{JEDec | Manual}

Outputs
The currently selected Vref mode {JEDec | Manual}.

DDR Analysis 199

GPIB Commands DDRA:VREF

DDRA:VREF
This command sets or queries the user-defined Vref value for a particular DDR generation.

NOTE. If there is an error, the DDRA:LASTError? query returns select user defined mode to configure
Vdd/Vref value.

Syntax
DDRA:VREF <NR3>

DDRA:VREF?

Inputs
<NR3>

Outputs
<NR3>

DDRA:VIHACMin?
This query-only command returns the VIHACMin value.

Syntax
DDRA:VIHACMin?

Inputs
None.

Outputs
<NR3>

200 DDR Analysis

GPIB Commands DDRA:VIHDCMin?

DDRA:VIHDCMin?
This query-only command returns the VIHDCMin value.

Syntax
DDRA:VIHDCMin?

Inputs
None

Outputs
<NR3>

DDRA:VREFDC?
This query-only command returns the VREFDC value.

Syntax
DDRA:VREFDC?

Inputs
None

Outputs
<NR3>

DDR Analysis 201

GPIB Commands DDRA:VILDCMax?

DDRA:VILDCMax?
This query-only command returns the VILDCMax value.

Syntax
DDRA:VILDCMax?

Inputs
None

Outputs
<NR3>

DDRA:VILACMax?
This query-only command returns the VILACMax value.

Syntax
DDRA:VILACMax?

Inputs
None

Outputs
<NR3>

202 DDR Analysis

GPIB Commands DDRA:SOURCE?

DDRA:SOURCE?
This branch-query command returns the sources selected for the measurement.

Syntax
DDRA:SOURCE?

Inputs
None

Outputs
String

DDRA:SOURCE:STROBE
This command sets or queries the sources for the strobe source type.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:SOURCE:STROBE {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 |
REF1 | REF2 | REF3 | REF4}

DDRA:SOURCE:STROBE?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

DDR Analysis 203

GPIB Commands DDRA:SOURCE:STRObebar

DDRA:SOURCE:STRObebar
This command sets or queries the sources for the strobe bar source type.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:SOURCE:STRObebar {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4
| REF1 | REF2 | REF3 | REF4}

DDRA:SOURCE:STRObebar?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

204 DDR Analysis

GPIB Commands DDRA:SOURCE:DATa

DDRA:SOURCE:DATa
This command sets or queries the sources for the data source type.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:SOURCE:DATa {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1
| REF2 | REF3 | REF4}

DDRA:SOURCE:DATa?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

DDR Analysis 205

GPIB Commands DDRA:SOURCE:CLOCK

DDRA:SOURCE:CLOCK
This command sets or queries the sources for the clock source type.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:SOURCE:CLOCK {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 |
REF1 | REF2 | REF3 | REF4}

DDRA:SOURCE:CLOCK?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

206 DDR Analysis

GPIB Commands DDRA:SOURCE:CLOCKBar

DDRA:SOURCE:CLOCKBar
This command sets or queries the sources for the clock bar source type.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:SOURCE:CLOCKBar {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4
| REF1 | REF2 | REF3 | REF4}

DDRA:SOURCE:CLOCKBar?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

DDR Analysis 207

GPIB Commands DDRA:SOURCE:WCK

DDRA:SOURCE:WCK
This command sets or queries the sources for the WCK source type.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:SOURCE:WCK {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1
| REF2 | REF3 | REF4}

DDRA:SOURCE:WCK?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3
| REF4}.

208 DDR Analysis

GPIB Commands DDRA:SOURCE:WCKBar

DDRA:SOURCE:WCKBar
This command sets or queries the sources for the WCK bar source type.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:SOURCE:WCKBar {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 |
REF1 | REF2 | REF3 | REF4}

DDRA:SOURCE:WCKBar?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3
| REF4}.

DDR Analysis 209

GPIB Commands DDRA:BURSTDETectmethod

DDRA:BURSTDETectmethod
This command sets or queries the Burst Detection method used for the measurement.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement and set the
applicable source type.

Syntax
DDRA:BURSTDETectmethod {DQDQS | CHIPselectd | LOGICstate | VISUALSEARCH |
NONE}

DDRA:BURSTDETectmethod?

Inputs
{DQDQS | CHIPselectd | LOGICstate | VISUALSEARCH | NONE}

Outputs
{DQDQS | CHIPselectd | LOGICstate | VISUALSEARCH | NONE}

210 DDR Analysis

GPIB Commands DDRA:BUS

DDRA:BUS
This command sets or queries the Bus to be used for the measurements. The bus needs to be configured
before being selected.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement, before selecting
a bus.

Syntax
DDRA:BUS {bus_name}

DDRA:BUS?

Inputs
String

Outputs
String

DDR Analysis 211

GPIB Commands DDRA:SYMBOLFile

DDRA:SYMBOLFile
This command sets or queries the symbol file used for the selected bus. Select and configure the bus
before selecting a symbol file for the particular bus.

NOTE. If there is an error, the DDRA:LASTError? query returns a bus has to be selected and configured.

Syntax
DDRA:SYMBOLFile {file_name}

DDRA:SYMBOLFile?

Inputs
String

Outputs
String

DDRA:LOGICTrigger
This command sets or queries the symbol that needs to be triggered for the selected bus. Select and
configure the bus before selecting a symbol for the particular bus.

NOTE. If there is an error, the DDRA:LASTError? query returns a bus has to be selected and configured.

Syntax
DDRA:LOGICTrigger {READ | WRITE |...}

DDRA:LOGICTrigger?

Inputs
<string> {READ | WRITE |...}

Outputs
<string> {READ | WRITE |...}

212 DDR Analysis

GPIB Commands DDRA:BURSTTOlerance

DDRA:BURSTTOlerance
This command sets or queries the burst tolerance required for the selected bus. Select and configure the
bus before setting the burst tolerance.

NOTE. If there is an error, the DDRA:LASTError? query returns a bus has to be selected and configured.

Syntax
DDRA:BURSTTOlerance <NR3>

DDRA:BURSTTOlerance?

Inputs
<NR3>

Outputs
<NR3>

DDRA:BURSTLAtency
This command sets or queries the Burst Latency required for the selected bus. Select and configure
the bus before setting the burst latency.

NOTE. If there is an error, the DDRA:LASTError? query returns a bus has to be selected and configured.

Syntax
DDRA:BURSTLAtency <NR3>

DDRA:BURSTLAtency?

Inputs
<NR3>

Outputs
<NR3>.

DDR Analysis 213

GPIB Commands DDRA:BURSTLEngth

DDRA:BURSTLEngth
This command sets or queries the burst length required for the selected bus. Select and configure the bus
before setting the burst length.

NOTE. If there is an error, the DDRA:LASTError? query returns a bus has to be selected and configured.

Syntax
DDRA:BURSTLEngth <NR3>

DDRA:BURSTLEngth?

Inputs
<NR3>

Outputs
<NR3>

214 DDR Analysis

GPIB Commands DDRA:ALTernatethresholds

DDRA:ALTernatethresholds
This command sets or queries the alternate thresholds for the measurements selected in a particular
generation.

NOTE. If there is an error, the DDRA:LASTError? query returns alternate threshold is not supported for
the generation selected select a measurement, before selecting the alternate threshold.

Syntax
DDRA:ALTernatethresholds {AC175 | AC150 | AC225 | AC300}

DDRA:ALTernatethresholds?

Inputs
{AC175 | AC150 | AC225 | AC300}

Outputs
{AC175 | AC150 | AC225 | AC300}

DDR Analysis 215

GPIB Commands DDRA:VERTicalscaling

DDRA:VERTicalscaling
This command sets or queries the vertical scaling enabled or disabled for the measurements selected in a
particular generation.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement, before selecting
any of the scaling method.

Syntax
DDRA:VERTicalscaling {0 | 1}

DDRA:VERTicalscaling?

Inputs
{0 | 1}

Outputs
{0 | 1}

216 DDR Analysis

GPIB Commands DDRA:HORIzontalscaling

DDRA:HORIzontalscaling
This command sets or queries the horizontal scaling enabled or disabled for the measurements selected in a
particular Generation.

NOTE. If there is an error, the DDRA:LASTError? query returns select a measurement, before selecting
any of the scaling method.

Syntax
DDRA:HORIzontalscaling {0 | 1}

DDRA:HORIzontalscaling?

Inputs
{0 | 1}

Outputs
{0 | 1}

DDRA:CSSOUrce
This command sets or queries the sources for the chip select source type..

Syntax
DDRA:CSSOUrce {CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1
| REF2 | REF3 | REF4}

DDRA:CSSOUrce?

Inputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

Outputs
{CH1 | CH2 | CH3 | CH4 | MATH1 | MATH2 | MATH3 | MATH4 | REF1 | REF2 | REF3 |
REF4}

DDR Analysis 217

GPIB Commands DDRA:CASMIN

DDRA:CASMIN
This command sets or queries the CAS Min value for the chip select burst detection method.

Syntax
DDRA:CASMIN <NR3>

DDRA:CASMIN?

Inputs
<NR3>

Outputs
<NR3>

DDRA:CASMAX
This command sets or queries the CAS Max value for the chip select burst detection method.

Syntax
DDRA:CASMIN <NR3>

DDRA:CASMIN?

Inputs
<NR3>

Outputs
<NR3>

218 DDR Analysis

GPIB Commands DDRA:CSLEvel

DDRA:CSLEvel
This command sets or queries the chip select level.

Syntax
DDRA:CSLEvel <NR3>

DDRA:CSLEvel?

Inputs
<NR3>

Outputs
<NR3>

DDRA:CSMOde
This command sets or queries the chip select mode.

Syntax
DDRA:CSMOde {AUTO | MANUAL}

DDRA:CSMOde?

Inputs
{AUTO | MANUAL}

Outputs
{AUTO | MANUAL}

DDR Analysis 219

GPIB Commands DDRA:CSACTive

DDRA:CSACTive
This command sets or queries the chip select active mode.

Syntax
DDRA:CSACTive {L | H}

DDRA:CSACTive?

Inputs
{L | H}

Outputs
{L | H}

DDRA:VERsion?
This command queries the DDRA Version.

Syntax
DDRA:VERsion?

Outputs
String

220 DDR Analysis

GPIB Commands DDRA:BURSTLevelmode

DDRA:BURSTLevelmode
This command sets or queries the burst level mode for the DQ and DQS settings.

Syntax
DDRA:BURSTLevelmode {AUTO | MANUAL}

DDRA:BURSTLevelmode?

Inputs
{AUTO | MANUAL}

Outputs
{AUTO | MANUAL}

DDRA:STROBEHIGH
This command sets or queries the strobe high value for the DQ and DQS settings.

Syntax
DDRA:STROBEHIGH <NR3>

DDRA:STROBEHIGH?

Inputs
<NR3>

Outputs
<NR3>

DDR Analysis 221

GPIB Commands DDRA:STROBELOW

DDRA:STROBELOW
This command sets or queries the strobe low value for the DQ and DQS settings.

Syntax
DDRA:STROBELOW <NR3>

DDRA:STROBELOW?

Inputs
<NR3>

Outputs
<NR3>

DDRA:STROBEMID
This command sets or queries the strobe mid value for the DQ and DQS settings.

Syntax
DDRA:STROBEMID <NR3>

DDRA:STROBEMID?

Inputs
<NR3>

Outputs
<NR3>

222 DDR Analysis

GPIB Commands DDRA:DATALOW

DDRA:DATALOW
This command sets or queries the data low value for the DQ and DQS settings.

Syntax
DDRA:DATALOW <NR3>

DDRA:DATALOW?

Inputs
<NR3>

Outputs
<NR3>

DDRA:DATAHIGH
This command sets or queries the data high value for the DQ and DQS settings.

Syntax
DDRA:DATAHIGH <NR3>

DDRA:DATAHIGH?

Inputs
<NR3>

Outputs
<NR3>

DDR Analysis 223

GPIB Commands DDRA:DATAMID

DDRA:DATAMID
This command sets or queries the data mid value for the DQ and DQS settings.

Syntax
DDRA:DATAMID <NR3>

DDRA:DATAMID?

Inputs
<NR3>

Outputs
<NR3>

DDRA:HYSTEREsis
This command sets or queries the edge detection hysteresis value for the DQ and DQS settings.

Syntax
DDRA:HYSTEREsis <NR3>

DDRA:HYSTEREsis?

Inputs
<NR3>

Outputs
<NR3>

224 DDR Analysis

GPIB Commands DDRA:MARGIN

DDRA:MARGIN
This command sets or queries the termination logic margin value for the DQ and DQS settings.

Syntax
DDRA:MARGIN <NR3>

DDRA:MARGIN?

Inputs
<NR3>

Outputs
<NR3>

DDRA:DQDQSLEVELSTAtus?
This command queries the DQ and DQS level status.

Syntax
DDRA:DQDQSLEVELSTAtus?

Outputs
{AUTO | MANUAL

DDR Analysis 225

GPIB Commands DDRA:VCENTDQ

DDRA:VCENTDQ
This command sets or queries VCENTDQ.

Syntax
DDRA:VCENTDQ<NR3>

DDRA:VCENTDQ?

Inputs
<NR3>

Outputs
<NR3>

DDRA:FLTtype
This command sets or queries the interposer filter type.

Syntax
DDRA:FLTtype {None| USERDefined | DIRECTAttached | Socketed}

DDRA:FLTtype?

Inputs
{None | USERDefined | DIRECTAttached | Socketed}

Outputs
{None | USERDefined | DIRECTAttached | Socketed}

226 DDR Analysis

GPIB Commands DDRA:PTYPDQS

DDRA:PTYPDQS
This command sets or queries the probing type for DQS Signal.

Syntax
DDRA:PTYPDQS {DIFFerential | SINGLEended}

DDRA:PTYPDQS?

Inputs
{DIFFerential | SINGLEended}

Outputs
{DIFFerential | SINGLEended}

DDRA:PTYPCLK
This command sets or queries the probing type for Clock Signal.

Syntax
DDRA:PTYPCLK {DIFFerential | SINGLEended}

DDRA:PTYPCLK?

Inputs
{DIFFerential | SINGLEended}

Outputs
{DIFFerential | SINGLEended}

DDR Analysis 227

GPIB Commands DDRA:PTYPWCK

DDRA:PTYPWCK
This command sets or queries the probing type for WCK Signal.

Syntax
DDRA:PTYPWCK {DIFFerential | SINGLEended}

DDRA:PTYPWCK?

Inputs
{DIFFerential | SINGLEended}

Outputs
{DIFFerential | SINGLEended}

DDRA:SEFLTFile
This command sets or queries the Single Ended interposer filter file used for the User Defined filter type.

Syntax
DDRA:SEFLTFile {file_name}

DDRA:SEFLTFile?

Inputs
string

Outputs
string

228 DDR Analysis

GPIB Commands DDRA:DIFFFLTFile

DDRA:DIFFFLTFile
This command sets or queries the Differential interposer filter file used for the User Defined filter type.

Syntax
DDRA:DIFFFLTFile {file_name}

DDRA:DIFFFLTFile?

Inputs
string

Outputs
string

DDRA:TCKAVGMIN
This command sets or queries TCKAVGMIN.

Syntax
DDRA:TCKAVGMIN<NR3>

DDRA:TCKAVGMIN?

Inputs
<NR3>

Outputs
<NR3>

DDR Analysis 229

GPIB Commands DDRA:TCKAVG

DDRA:TCKAVG
This command sets or queries TCKAVG.

Syntax
DDRA:TCKAVG<NR3>

DDRA:TCKAVG?

Inputs
<NR3>

Outputs
<NR3>

230 DDR Analysis

 Index

Index

A Recalc, 14 E
About DDRA, 10 Run, 14 E1001, 126
AC 150, 54 Show Plots, 14 E1002, 126
AC 175, 53 Single, 14 E1003, 126
AC-Overshoot, 178 Conventions, 4 E1004, 126
AC-Overshoot(CK), 159 Customer Feedback, 5 E1005, 126
AC-Overshoot(CK#), 158 E1006, 126
AC-Overshoot(DQS), 168 D E1007, 126
AC-Overshoot(DQS#), 169 D, 18 E1008, 126
AC-OvershootArea, 178 Data Eye Height, 133 E1009, 126
AC-OvershootArea(CK), 160 Data Eye Width E1010, 126
AC-OvershootArea(CK#), 159 superimposed eye, 132 E1012, 126
AC-OvershootArea(DQS), 170 Data Rate, 68 E1013, 126
AC-OvershootArea(DQS#), 169 DDR, 4 E102, 125
AC-Undershoot, 179 DDR Analysis, 30 E1020, 126
AC-Undershoot(CK), 161 DDR Generation, 68 E1021, 126
AC-Undershoot(CK#), 160 DDR Method, 27 E1022, 126
AC-Undershoot(DQS), 170 DDR104, 128 E1026, 126
AC-Undershoot(DQS#), 171 DDR105, 128 E1027, 126
AC-UndershootArea, 179 DDR106, 128 E1028, 126
AC-UndershootArea(DQS), 172 DDR107, 128 E1029, 126
AC-UndershootArea(DQS#), 171 DDR2-tDQSCK, 148 E103, 125
Address/Command, 24 DDRA, 4 E1035, 126
Algorithms, 131 DDRA Prerequisites, 7 E104, 125
Alternate Thresholds, 52 Derating, 182 E1040, 126
Argument Types, 190 Directories, 13 E105, 125
64–bit systems, 13 E1054, 126
B DPOJET, 4 E1055, 126
DQ/DQS Phase Alignment, 41 E1056, 126
Browse, 11
DQS(Single Ended), 23 E1057, 126
DUT, 4 E1058, 126
C Dynamic Limits, 18 E1059, 126
Check Boxes, 11 Dynamic Limits for DDR, 111 E106, 125
Chip Select, 43 Dynamic Limits for DDR2, 112 E1061, 127
CKslew-Fall(CK), 162 Dynamic Limits for DDR3, 113 E1062, 127
CKslew-Fall(CK#), 162 Dynamic Limits for DDR3L, 114 E1063, 127
CKslew-Rise(CK), 163 Dynamic Limits for DDR4, 115 E2001, 127
CKslew-Rise(CK#), 163 Dynamic Limits for LPDDR, 108 E2002, 127
Clock(Diff), 21 Dynamic Limits for E2003, 127
Clock(Single Ended), 22 LPDDR2, 109 E2004, 127
Command button, 11 Dynamic Limits for E2005, 127
Control Panel LPDDR3, 110 E2006, 127
Advanced Setup DPOJET, 14 E2007, 127
Clear, 14 E2008, 127

DDR Analysis 231

Index

E202, 125 DDRA:ADDALLD- DDRA:SOURCE:STROBE-

E3001, 127 iffdqs, 192 , 203
E3002, 127 DDRA:ADDALLSEdqs, 192 DDRA:SOURCE:WCK, 208
E3003, 127 DDRA:ADDALL- DDRA:SOURCE:WCK-
E3004, 127 SLewdq, 193 Bar, 209
E3005, 127 DDRA:ADDALLTerr, 193 DDRA:STRObebar, 204
E3006, 127 DDRA:ADDMeas, 190 DDRA:STROBEHIGH, 221
E3007, 127 DDRA:ALTernatethresh- DDRA:STROBELOW, 222
E3008, 127 olds, 215 DDRA:STROBEMID, 222
E3010, 127 DDRA:BURSTDETect- DDRA:SYMBOLFile, 212
E3011, 127 method, 210 DDRA:TCKAVG, 230
E3012, 127 DDRA:BURSTLAtency, 213 DDRA:TCKAVGMIN, 229
E400, 125 DDRA:BURSTLEngth, 214 DDRA:VCENTDQ, 226
E4000, 127 DDRA:BURSTTOler- DDRA:VDD, 199
E4001, 127 ance, 213 DDRA:VDDMode, 198
E4002, 127 DDRA:BUS, 211 DDRA:VERsion, 220
E4003, 127 DDRA:CASMAX, 218 DDRA:VERTicalscal-
E4004, 127 DDRA:CASMIN, 218 ing, 216
E4005, 127 DDRA:CLEAR- DDRA:VIHACMin, 200
E4006, 128 ALLMeas, 194 DDRA:VIHDCMin, 201
E4007, 128 DDRA:CSACTive, 220 DDRA:VILACMax, 202
E4027, 128 DDRA:CSLEvel, 219 DDRA:VILDCMax, 202
E4028, 128 DDRA:CSMOde, 219 DDRA:VREF, 200
E4029, 128 DDRA:CSSOUrce, 217 DDRA:VREFDC, 201
E4030, 128 DDRA:CUSTOMRate, 197 DDRA:VREFMode, 199
E4031, 128 DDRA:DATAHIGH, 223 DPOJET:MEAS<x>:RE-
E411, 126 DDRA:DATALOW, 223 SULts?, 194
E424, 126 DDRA:DATAMID, 224 DPOJET:MEASType, 198
E425, 126 DDRA:DATARate, 196 GPIB Program, 189
E500, 126 DDRA:DIFFFLTFile, 229 GPIB Reference Materials, 189
DDRA:DQDQSLEVELSTA-
F tus, 225 H
DDRA:FLTtype, 226
File Name Hints, 56
DDRA:HORizontalscal-
.csv, 13
ing, 217
.mht, 13 I
DDRA:HYSTEREsis, 224
.set, 13
DDRA:LOGICTrigger, 212 Input Slew-Diff-Fall(CK), 158
.wfm, 13
DDRA:MARGIN, 225 Input Slew-Diff-Fall(DQS), 134
DDRA:PTYPCLK, 227 Input Slew-Diff-Rise(CK), 157
G DDRA:PTYPDQS, 227 Input Slew-Diff-Rise(DQS), 134
Generations DDRA:PTYPWCK, 228
DDR, 7 DDRA:SEFLTFile, 228
DDR2, 7 DDRA:SOURCE?, 203
L
DDRA:SOURCE:CLOCK- Limits, 16
DDR3, 7
, 206 Logic State, 44
GDDR3, 7
LPDDR, 7 DDRA:SOURCE:CLOCK-
GPIB Commands Bar, 207 M
DDRA: GENeration, 195 DDRA:SOURCE:DATa, 205 Measurement Levels, 55

232 DDR Analysis

 Index

Measurement Sources Results, 57 tAPW, 181

DDR, 86 tAS, 181
DDR2, 89 S tCH, 151
DDR3, 93 tCH(abs), 152
Safety Summary, xi
DDR3L, 97 tCH(avg), 153
Saving a Setup, 15
DDR4, 100 tCK, 152
Search and Mark, 1
GDDR5, 104 tCK(abs), 153
Slew Rate-Hold-
LPDDR, 75 tCK(avg), 153
Fall(Addr/Cmd), 180
LPDDR2, 77 tCKSRE, 183
Slew Rate-Hold-Fall(DQ), 150
LPDDR3, 82 tCKSRX, 183
Slew Rate-Hold-
Measurement Type tCL, 152
Rise(Addr/Cmd), 180
Active, 35 tCL(abs), 154
Slew Rate-Hold-Rise(DQ), 150
Address/Command, 35 tCL(avg), 154
Slew Rate-Hold-SE-
Clock (Single Ended), 35 tCMDH, 181
Fall(DQS), 139
Clock(Diff), 35 tCMDPW, 181
Slew Rate-Hold-SE-
DQS(Single Ended), 35 tCMDS, 182
Rise(DQS), 139
Power Down, 35 tDH-Diff(base), 135
Slew Rate-Setup-
Precharge, 35 tDH-Diff(derated), 135
Fall(Addr/Cmd), 180
Read Bursts, 35 tDH-Diff(Vref-based), 135
Slew Rate-Setup-Fall(DQ), 150
Refresh, 35 tDH-SE(base), 141
Slew Rate-Setup-
Slew Rate(Diff), 35 tDIPW-SE, 140
Rise(Addr/Cmd), 180
WCK(Diff), 35 tDQSCK-Diff, 144
Slew Rate-Setup-Rise(DQ), 151
WCK(Single Ended), 35 tDQSCK-SE, 147
Slew Rate-Setup-SE-
Write Bursts, 35 tDQSH, 138
Fall(DQS), 139
tDQSL, 138
Slew Rate-Setup-SE-
N tDQSQ-Diff, 144
Rise(DQS), 140
tDQSQ-SE, 147
nominal metho, 27 Speed Bins, 33
tDQSS-Diff, 139
Nominal Method, 27 SRQdiff-Fall(DQS), 146
tDQSS-SE, 141
SRQdiff-Rise(DQS), 146
tDS-Diff(base), 135
O SRQse-Fall(DQ), 148
tDS-Diff(derated), 137
SRQse-Rise(DQ), 149
Opt. ASM, 1 tDS-Diff(Vref-based), 137
SSC Downspread(CK), 151
Oscilloscope model number, 5 tDS-SE(base), 140
SSC Downspread(WCK), 172
Overshoot, 178 tDSH-Diff, 139
SSC Mod Freq(CK), 151
tDSH-SE, 140
SSC Mod Freq(WCK), 172
tDSS-Diff, 138
P SSC Profile(CK), 151
tDSS-SE, 140
Parameters, 67 SSC Profile(WCK), 173
tDVAC(CK), 141
Plots, 58 Step1, 31
tDVAC(WCK), 173
probes, 8 Step2, 34
tERR
Step4, 40
tERR(m–nper), 155
Step5, 40
R Step6, 51
tERR(nper), 155
Read Bursts, 20 tHP, 154
Symbol file, 45
Recalling a Default Setup, 16 tIH(base), 182
Ref Levels Setup, 55 tIH(derated), 183
Related Documentation, 3 T tIPW-High, 183
Reports, 58 tAC-Diff, 145 tIPW-Low, 183
Requirements, 7 tAH, 181 tIS(base), 182

DDR Analysis 233

Index

tIS(derated), 182 tWCKHP, 174 Vox(ac)DQS, 168

tJIT(cc), 156 tWCKL, 174 VSEH(AC)CK, 165
tJIT(duty), 156 tWPRE, 142 VSEH(AC)CK#, 166
tJIT(per), 157 tWPST, 143 VSEH(CK), 166
tPD, 184 tWRPDE, 143 VSEH(CK#), 166
tPPD, 187 tWRSRE, 143 VSEL(AC)CK, 167
tQH, 145 tXSNRW, 184 VSEL(AC)CK#, 166
tRAS, 185 VSEL(CK), 167
tRC, 185 U VSEL(CK#), 167
tRCDRD, 186 VSWING(MAX)CK, 165
Undershoot, 179
tRCDWR, 186 VSWING(MAX)CK#, 164
tRDPDE, 149 VWCK-Swing, 175
tRDSRE, 149 V
tREFTR(Read), 184 Vdd and Vref, 33 W
TREFTR(Write), 184 VID(ac), 157
W1011, 126
tRFC, 184 VIN(CK), 163
W1051, 126
tRP(ACT), 187 VIN(CK#), 163
W1053, 126
tRP(MRS), 188 VIN(WCK), 175
W4008, 128
tRP(REF), 188 VIN(WCK#), 175
W4009, 128
tRP(SRE), 188 Virtual Keypad, 12
W410, 125
tRPRE, 150 Vix(ac)CK, 164
WCKslew-Fall(WCK), 177
tRPST, 150 Vix(ac)DQS, 168
WCKslew-Fall(WCK#), 177
tRTPL, 188 Vix(ac)WCK, 176
WCKslew-Rise(WCK), 177
tWCK, 173 VOH, 176
WCKslew-Rise(WCK#), 177
tWCK-DJ, 173 VOH(WCK), 176
Write Bursts, 19
tWCK-Fall-Slew, 174 VOH(WCK#), 177
tWCK-Rise-Slew, 174 VOL, 176
tWCK-RJ, 174 VOL(WCK), 176 X
tWCK-TJ, 175 VOL(WCK#), 176 XML, 16
tWCKH, 173 Vox(ac)CK, 164

234 DDR Analysis