A High Linearity LNA using 180 nm CMOS

Technology for S-Band

Alican Çağlar Mustafa Berke Yelten
Electronics and Communication Engineering Electronics and Communication Engineering
Istanbul Technical University Istanbul Technical University
Istanbul, TURKEY Istanbul, TURKEY
Email: caglara@itu.edu.tr Email: yeltenm@itu.edu.tr

Abstract— In this paper, a single-stage cascode low noise cryogenic temperatures, but IIP3 may degrade due to low carrier
amplifier (LNA) was designed using UMC 180 nm complementary density. In this work, simulations of the designed LNA were
metal oxide semiconductor (CMOS) technology for 2.025-2.12 performed with respect to room temperature, but the DC biasing
GHz (S-Band), specifically aimed for cryogenic applications. All of the common source stage has been kept adjustable through an
transistor gates have electrostatic discharge (ESD) protectıon. The external voltage source so that the necessary carrier density for
LNA achieved 15.8 dB gain, +2 dBm IIP3, and 1.6 dB noise figure high IIP3 at 77 K can be accomplished.
(NF) at 2.075 GHz drawing 7.66 mA current from a 1.8 V supply.
With regard to its counterparts, the LNA performs better in terms In Section II, NF at room temperature, which is targeted to
of its IIP3 outcome. be near 1 dB at 77 K, was approximately calculated. Then a dual
diode structure for electrostatic discharge (ESD) protection was
Keywords—Low noise amplifier (LNA), complementary metal designed with regard to the NF objective and the required
oxide semiconductor (CMOS), electrostatic discharge (ESD), resilience against ESD in Section III. In Section IV, the
cryogenic. schematic and layout of the ESD protected LNA with high IIP3
and low NF are presented. After post-layout simulations, input
I. INTRODUCTION
and output matching were accomplished by discrete components
Interest in cryogenic circuits has been increasing with the since on-chip matching components such as spiral inductors
research progress in quantum computing and deep space have very large sizes leading to low quality factors that degrade
research. In quantum computing, qubits should be held close to the NF performance of the LNA. Finally, simulation results have
the liquid helium temperature for increased quantum coherence been provided, and the LNA was compared with its previously
time, which leads to high computational power [1]. Operation published counterparts in Section V.
temperature range of circuits is wider in space research.
According to National Aeronautics and Space Administration II. NOISE FIGURE
(NASA), recorded maximum and minimum temperature values To achieve sub-1 dB NF goal at 77 K, NF of LNA at room
on the surface of Mars are 303 K and 133 K, respectively, which temperature corresponding to 1 dB at 77 K has to be
are much lower than conventional industry standards [2]. In approximately calculated. To achieve this, one should start with
addition to space applications, cryogenic low noise amplifiers computing the contributions of different noise sources in CMOS
(LNAs) are preferred in infrared sensors to achieve high like the thermal noise, shot noise, and the flicker noise. Metal
sensitivity by mitigating thermal noise limitation. oxide semiconductor field-effect transistors (MOSFETs) exhibit
Heterojunction bipolar transistors (HBTs) and high electron considerable shot noise in subthreshold region. However, LNA
mobility transistors (HEMTs) are widely employed in space transistors operate in saturation region; thus, contribution of the
applications due to their lower noise and higher speed shot noise to NF can be neglected. Flicker noise is the dominant
characteristics, as well as higher transition frequency compared noise source in low frequency, and its power density is
to complementary metal oxide semiconductor (CMOS) proportional to 1/f. Thus, flicker noise is also negligible
technology. However, with scaling, CMOS yields better compared to thermal noise in S-Band. Hence, thermal noise is
performance and it retains its popularity in integrated circuit (IC) the major noise source in S-Band. Previous research studies on
design due to its low cost and high integration capabilities. cryogenic LNAs show that NF is proportional to temperature
[4], as the average thermal noise power of a system with a real
In this paper, the LNA design has been realized with UMC impedance R can be given as:
180 nm technology considering cryogenic environment
conditions. The design goal is to achieve sub-1 dB noise figure =4 , (1)
(NF) and high IIP3 at 77 K. However, transistor models for
cryogenic temperatures are not available. Therefore, firstly where kB is the Boltzmann's constant and T is the temperature in
previous research studies on cryogenic LNAs have been Kelvin. Considering thermal noise to be the dominant noise
investigated, and variations of their characteristics like NF, gain source, relationship between NFs at room temperature and
and IIP3 at cryogenic temperatures were examined. According cryogenic temperature can be defined as in (2). Here, 1 dB NF
to recently published cryogenic LNAs, NF and gain improve at

978-1-5386-3974-0/17/$31.00 ©2017 IEEE

at 77 K corresponds to 3.03 dB NF at 300 K. This is a simple VCC
expression providing insight, but for a detailed analysis, other
important factors like impedance matching should be taken into
account. Nevertheless, (2) is quite consistent with LNA
measurements at 77 K and 300 K provided in [4]. Including LD CD 2.5n RFOUT
other neglected factors, the design objective is to obtain NF
value to be less than 2 dB at room temperature. VBIAS 1.5p 1n
M3 M4
RB
= 10 ∗ log 10 −1 ∗ + 1 (2) DP
RFIN 9n
M1 M2
1n CGS1 CGS2
III. ESD 1p DN
In this work, dual-diode structure (p-diode DP and n-diode
DN) is used for ESD protection. It is a robust ESD structure,
however, due to its large junction capacitance, it severely
Fig. 1. Schematic of the LNA including external components. Dotted lines
degrades the RF performance of common source LNAs. As
indicate the chip boundary.
indicated in [5], the capacitance mainly depends on the bottom
plate of the diode. The current flows through the p-n junction carriers requires more energy. Therefore, carrier density will
interface of the diode; thus, the robustness of ESD diodes is extremely decrease at deep cryogenic temperatures, which is
directly related to the junction perimeter of the diodes. A called freeze-out. It brings about low current density, which may
multiple finger structure is used to increase the perimeter and excessively degrade NF and IIP3 of the LNA as demonstrated
reduce the capacitance. Smallest finger sizes in the UMC 180 by simulations of the cryogenic LNA in [3]. Thus, proper bias
nm technology (W = 940 nm and L = 940 nm) were chosen to voltage for 77 K will most likely be different from the bias
maximize the perimeter. voltage for 300 K. To provide the bias voltage directly from
outside of the chip allows tuning the operating point of the input
There are different types of ESD models like Human Body transistor to achieve high IIP3 during measurements. RB is
Model (HBM), Machine Model (MM), and Charged Device chosen to be large to reduce its noise contribution. Bondwires
Model (CDM). In this work, the main purpose of the ESD have generally a higher quality factor than on-chip spiral
protection is to keep the designed LNA robust enough against inductors; thus, to reduce the bondwire resistance, as well as the
ESD events that may possibly happen during manufacturing and thermal noise originating from it, the source degeneration
measurements. The preferred protection level for HBM is about inductor was realized by two parallel bondwires. By the same
2 kV. HBM protection can easily be established in the token, the RF input is bonded with two bondwires to the package
measurement environment by proper grounding; thus, HBM lead. Inductance provided by the bondwires has been estimated
ESD protection may be allayed. Since all LNA pads will be considering the distance between the pads of the die and the
bonded to QFN16 (5 x 5 mm2) package, transistor gates will be leads of the package. The width of the input transistor was
vulnerable against CDM events during manufacturing. In CDM determined based on a trade-off between the NF, IIP3, and the
based ESD events very high current levels can be reached within power consumption of the LNA. Noise figure of a source
a very short time. Recommended CDM protection level by [6] degenerated cascode amplifier as given in Fig. 2 can be
should be 250 V for safe manufacturing. CDM current peak expressed as in (3) by neglecting the channel length modulation,
level depends on the package size and its value at 250 V stress body effect, and the noise contribution of the common gate (CG)
voltage is around 1 A for 25 mm2 package size [6]. Thus, ESD transistor, as well as considering input match realized by CGS, LS
diodes should be designed such that transistors survive at 1 A and M1 [8].
CDM current level. Tsai et. al. reported that ESD dual diodes
with 25 fingers (width W = 2 µm and length L = 0.15 µm of each =1+ (3)
finger) whose perimeter is equal to 107.5 µm can provide
protection up to 1.8 A CDM current level, which yields In [8], gm1 is the transconductance of M1, RS is the source
sufficient protection against 250 V CDM events [7]. Therefore, impedance, and is the excess noise coefficient. is equal to
finger number of the ESD diodes at the RF input has been ( + ) , and is / . Simplified version of (3) can
determined to be 25 thereby making the junction perimeter of be written as in (4):
the diodes close to the 107.5 µm. Pads connected to the gates of
other transistors also have ESD protection by dual-diode
structure; however, their sizes are much larger since the impact =1+ (4)
of those transistors on the circuit performance is small. ( + )

IV. DESIGN PROCEDURE RFIN LG

M1
The schematic of the LNA is shown in Fig. 1. A simple CGS
single-stage cascode structure is used in the design. The DC bias
circuit has not been employed, as there is no available transistor LS
model to design a bandgap reference circuit at cryogenic
temperatures. Due to lack of thermal energy, ionization of
Fig. 2. Common source (CS) stage of a source degenerated cascode amplifier.
 From (4), it can be inferred that NF can be improved by
increasing the transconductance of M1, yet the power
consumption goes up as well. However, a larger current density
yields higher IIP3. The width of M1 was chosen such that IIP3
will be more than 0 dBm. Due to the finger number constraint of
the RF transistor in the UMC library, an extra parallel transistor
was attached to both CS and CG transistors, and sources of the
parallel CS transistors were not connected to each other to make
the layout design straightforward.
Before realizing the matching for NF and S11
simultaneously, minimum NF point should be shifted such that
it will be close to the unit circle in the Smith Chart to improve
NF. CGS was inserted between the gate and the source of the
input transistor to shift the minimum NF as illustrated in Fig 3.
Subsequently, the series inductor LG was added to the RF input
to complete the input matching. Gain of the LNA was adjusted
by LD. Output matching was performed by discrete components.
Finally, the layout of the LNA was drawn as shown in Fig 4. A
clamp circuit, which contains 6 series diodes, was added to
provide a low impedance track between VCC and the ground
during instantaneous high voltages in an ESD event. Size of
ESD diodes at the RF input is much smaller than the ESD
protection placed to the input pads of VCC and VBIAS so that
further performance degradation can be avoided. Moreover,
with a purpose of testing, ESD diodes of various sizes were put
in the layout to examine their ESD protection capabilities. To Fig. 4. Layout of the LNA (754 x 654 µm2).
prevent any small signal variation on VCC and VBIAS,
decoupling capacitors were inserted on DC lines. After post- V. SIMULATION RESULTS
layout simulations, matching components were optimized, and Post-layout simulation results at room temperature including
a parallel capacitor was added to the input matching circuit. external matching circuits are presented in Figs. 5-9. Input and
Parameters of on-chip circuit elements are given in Table 1. output reflection coefficients of the LNA are less than −10 dB
within 2.025-2.12 GHz. IIP3 simulations have been carried out
TABLE I. PARAMETERS OF CIRCUIT ELEMENTS
by a two-tone test at 2.075 GHz and 2.1 GHz. IIP3 and gain
Parameters Value
Width of M1, M2, M3, M4 130 µm
RB 113 K
CGS1 and CGS2 103 fF
LD 4.8 nH
CD 600 fF
VBIAS 740 mV

Fig. 5. Post-layout simulation of the LNA input return ratio (S11).

Fig. 3. Noise Figure optimization with CGS on Smith Chart. Fig. 6. Post-layout simulation of the LNA output return ratio (S22).
 TABLE II. PERFORMANCE COMPARISON WITH PREVIOUS STUDIES

Parameters This Work [9] [10] [11]

FOM 32.75 27.2 23.13 33.8
Frequency (GHz) 2.075 5.7 2.4 2.5
Technology 180 nm 180 nm 180 nm 180 nm
Power (mW) 13.8 17.53 4.5 2.5
Noise Figure (dB) 1.6 3.08 3.6 1.42
Gain (dB) 15.8 20.73 11.8 10
IIP3 (dBm) 2 −14 −8 −2.45
S11 (dB) −19.2 −36.32 −16 −32
Fig. 7. Post-layout simulation of the LNA gain. S22 (dB) −21.7 −21.17 - −30
ESD Yes N/A N/A N/A

VI. CONCLUSION
In this work, a S-Band LNA with high linearity is presented
with post-layout simulation outcomes performed at room
temperature. Finalized layout of the LNA has been sent to
fabrication. Manufactured LNA will be measured at 77 K.
Instead of designing a bias circuit, the bias voltage is externally
provided to adjust the required current density for high linearity
at 77 K considering the threshold voltage variations at low
temperatures. ESD diodes with a large perimeter and low
capacitance were added to avoid ESD failure that may take
Fig. 8. Post-layout simulation of the LNA NF. place during manufacturing.
ACKNOWLEDGEMENTS
This work was sponsored by the Technological Research
Council of Turkey under the project TÜBİTAK 1001 215E080
and Istanbul Technical University Department of Scientific
Research Projects under the project 39465.
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